ETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on January 27, 2026. Claims 1 and 11 have been amended. New claim 14 has been added. Claims 2-5, 9 and 13 have been canceled. Currently, claims 1, 6-8, 10-12 and 14 are pending.
Response to Arguments
Applicant’s arguments, filed on January 27, 2026, with respect to the rejection of claims 1 and 11 under U.S.C. 103 have been fully considered and are persuasive. Therefore, the final rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of newly found prior art references.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 6-8, 10 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 1, the claim recites, “the perimeter of the solder” which is indefinite and lacks antecedent basis.
Claims 6-8, 10 and 12 depend upon claim 1 and do not rectify the problem therefore, they are also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-7, 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ochi (JP 2004119568A) in view of Kuramochi (US 2007/0045870 A1).
Regarding claim 1, Ochi teaches a method of manufacturing a semiconductor device (see e.g., Figure 1) comprising:
preparing an insulating substrate including an insulating layer (see e.g., ceramic substrate 1, Para [0016], Figure 1) and a circuit pattern disposed on a surface of the insulating layer (see e.g., metal circuit board 2 disposed on the surface of the ceramic substrate 1, Para [0019], Figure 1); and
bonding a semiconductor element to a mount of a surface of the circuit pattern via solder (see e.g., semiconductor element 5 such as an IGBT (Insulated Gate Bipolar Transistor) or a MOS-FET (Metal Oxide Semiconductor-Field Effect Transistor) is bonded to a mount of a surface of the metal circuit board 2 via an adhesive such as solder 4 as shown in Figure 1, Paras [0007], [0025]),
wherein at least a portion of a groove is provided in a surface of the mount (see e.g., the frame-shaped groove 6 is provided in a surface of the mount as shown in Figure 1, Paras [0013], [0026]),
the solder (see e.g., solder 4, Figure 1), which bonds the semiconductor element to the mount (see e.g., solder paste made of lead-tin is printed on a mounting portion of the semiconductor element 5 on the upper surface of the metal circuit board 2 in a predetermined pattern corresponding to the shape of the semiconductor element 5 using a screen-printing technique. Next, the semiconductor element 5 is mounted on the solder 4, and the semiconductor element 5 is bonded to the upper surface of the metal circuit board 2 by heating and melting the solder at a temperature of about 300 ° C., Para [0025]), includes an outermost perimeter (see e.g., the solder disposed on the surface of the mount has an outermost perimeter perimeter),
upon bonding the semiconductor element to the mount of the surface of the circuit pattern,
the outermost perimeter of the solder includes … a second portion where the solder is in the groove (see e.g., upon bonding the semiconductor element 5 to the upper surface of the metal circuit board 2 the outermost perimeter of the solder is in the groove, Figure 1),
the surface of the mount being above the groove (see e.g., as shown in Figure 1 the surface of the mount is above the frame-shaped groove 6).
Ochi does not explicitly teach
“upon bonding the semiconductor element to the mount of the surface of the circuit pattern,
the outermost perimeter of the solder includes a first portion where the solder contacts the surface of the mount…,
and the portion of the perimeter of the solder contacting the surface of the mount is continuous around a majority of the perimeter of the solder”.
In a similar field of endeavor Kuramochi teaches a similar concept, in the context of an underfill resin 20 rather than a solder layer, where the underfill has an outermost perimeter with a portion contacting the surface of the mount and a portion in a recess 24.
Kuramochi teaches
upon bonding the semiconductor element to the mount of the surface of the circuit pattern (see e.g., semiconductor element 14 bonded to the mounted on the surface of a printed wiring board 12 in a flip chip connection, Para [0030], Figures 3-4),
the outermost perimeter of the solder includes a first portion where the solder contacts the surface of the mount, …. (see e.g., the outermost portion of the underfill resin 20 includes an outermost perimeter where a portion of it is in contact with the surface mount and a portion is in the recess 24, Figures 3-4),
and the portion of the perimeter of the solder contacting the surface of the mount is continuous around a majority of the perimeter of the solder (see e.g., a recess portion 24 is formed in the solder resist layer 22 in a region between the corner portion of the semiconductor chip 14 and the corner portion of the frame-shaped dam 16 being opposed to the corner portion of the frame-shaped dam 16. The region in which the recess portion in the solder resist layer is formed is limited to the corner region in which an outflow of the underfill 20 tends to occur, and a region other than the corner region is left as its original state in which the initial thickness of the solder resist layer is maintained. The perimeter of the underfill contacting the surface of the mount is mostly continuous, Paras [0032], [0044], Figures 3-4).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Kuramochi’s teachings of upon bonding the semiconductor element to the mount of the surface of the circuit pattern, the outermost perimeter of the solder includes a first portion where the solder contacts the surface of the mount, … and the portion of the perimeter of the solder contacting the surface of the mount is continuous around a majority of the perimeter of the solder in the method of Ochi in order to prevent overflow of the underfill.
Regarding claim 6, Ochi, as modified by Kuramochi, teaches the limitations of claim 1 as mentioned above. Ochi further teaches
disposing the solder on the mount (see e.g., solder paste made of lead-tin is printed on the upper surface of the metal circuit board 2 where the semiconductor element 5 is to be mounted, Para [0025], Figure 1);
disposing the semiconductor element on the solder (see e.g., the semiconductor element 5 is mounted on the solder 4, Para [0025], Figure 1);
heating the solder and thereby melting the solder (see e.g., the solder is heated and melted at a temperature of about 300 ° C., Para [0025]);
and after disposing the solder, disposing the semiconductor element, and heating the solder, curing the solder by cooling the melted solder to thereby bond the semiconductor element to the mount (see e.g., after disposing the solder paste on the mounting portion on the upper surface of the circuit board 2, disposing the semiconductor element 5 on the solder and heating and melting the solder, subsequently the curing/cooling step takes place to solidify the solder in order to bond the semiconductor element 5 to the circuit board 2), wherein
the groove is provided in a region around a location from where a portion of the melted solder that is not yet cured squirts out during the curing (see e.g., as the solder melts it spreads on the surface of the mount and flows in the frame-shaped groove 6. The frame-shaped groove 6 is provided in a region in which the outer periphery of the semiconductor element 5 is located between the groove’s inner and out peripheries, Paras [0025] – [0029], Figure 1).
Regarding claim 7, Ochi, as modified by Kuramochi, teaches the limitations of claim 1 as mentioned above. Ochi further teaches
wherein the groove is hemispherical (see e.g., the cross -sectional shape of the frame-shaped groove 6 maybe a semicircle, Para [0028]).
Ochi does not explicitly teach
“wherein the groove is provided in a region including any of four corners of the mount”.
In a similar field of endeavor Kuramochi teaches
wherein the groove is provided in a region including any of four corners of the mount (see e.g., A recess portion 24 is formed in the solder resist layer 22 in a region between the corner portion of the semiconductor chip 14 and the corner portion of the frame-shaped dam 16 being opposed to the corner portion of the frame-shaped dam 16, Para [0032], Figures 3-4).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Kuramochi’s teachings of wherein the groove is provided in a region including any of four corners of the mount in the method of Ochi in order to prevent overflow of the underfill.
Regarding claim 10, Ochi, as modified by Kuramochi, teaches the limitations of claim 6 as mentioned above. Ochi further teaches
wherein upon melting the solder, the solder squirts into the groove (see e.g., semiconductor element 5 is bonded to the upper surface of the metal circuit board 2 by heating and melting the solder at a temperature of about 300°C. As the solder melts it spreads over the mount and flows into the frame-shaped groove 6, Paras [0025] – [0029], Figure 1).
Regarding claim 12, Ochi, as modified by Kuramochi, teaches the limitations of claim 1 as mentioned above. Ochi does not explicitly teach
“wherein the groove is positioned asymmetrically with respect to the semiconductor element when viewed in plan view after bonding the semiconductor element to the mount”.
In a similar field of endeavor Kuramochi teaches
wherein the groove is positioned asymmetrically with respect to the semiconductor element when viewed in plan view after bonding the semiconductor element to the mount (see e.g., a recess portion 24 is formed in the solder resist layer 22 in a region between the corner portion of the semiconductor chip 14 and the corner portion of the frame-shaped dam 16 being opposed to the corner portion of the frame-shaped dam 16 hence is asymmetrically positioned with respect to the semiconductor chip 14, Para [0032], Figures 3-4).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Kuramochi’s teachings of wherein the groove is positioned asymmetrically with respect to the semiconductor element when viewed in plan view after bonding the semiconductor element to the mount in the method of Ochi in order to prevent the underfill from overflowing.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ochi (JP 2004119568A) in view of Kuramochi (US 2007/0045870 A1) and further in view of Mori et al. (JP 2004349399A; hereafter Mori).
Regarding claim 8, Ochi, as modified by Kuramochi, teaches the limitations of claim 1 as mentioned above. Ochi does not explicitly teach
“wherein the groove is the only groove in the mount”.
A rearrangement of parts is held to be an obvious matter of design choice. See In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); See also In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
In a similar field of endeavor Mori teaches a single concave portion 105 formed outside the position of the chip size package 102 on the mounting substrate 100 (see e.g., Paras [0014], [0020], Figure 1).
In the instance, Mori discloses positioning the groove outside the position of the chip size package 102. Positioning the groove such that it is in the mount would be obvious as a mere rearrangement of parts.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Mori’s teachings of wherein the groove is the only groove in the mount in the method of Ochi as it is a routine design choice to achieve predictable results.
Claims 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ochi (JP 2004119568A) in view of Kuramochi (US 2007/0045870 A1) and further in view of Mori et al. (JP 2004349399A; hereafter Mori).
Regarding claim 11, Ochi teaches a method of manufacturing a semiconductor device (see e.g., Figure 1) comprising:
preparing an insulating substrate including an insulating layer (see e.g., ceramic substrate 1, Para [0016], Figure 1) and a circuit pattern disposed on a surface of the insulating layer (see e.g., metal circuit board 2 disposed on the surface of the ceramic substrate 1, Para [0019], Figure 1); and
bonding a semiconductor element to a mount of a surface of the circuit pattern via solder (see e.g., semiconductor element 5 such as an IGBT (Insulated Gate Bipolar Transistor) or a MOS-FET (Metal Oxide Semiconductor-Field Effect Transistor) is bonded to a mount of a surface of the metal circuit board 2 via an adhesive such as solder 4 as shown in modified Figure 1, Paras [0007], [0025]),
wherein at least a portion of a groove is provided in a surface of the mount (see e.g., the frame-shaped groove 6 is provided in a surface of the mount as shown in modified Figure 1, Paras [0013], [0026]),
the solder (see e.g., solder 4, Figure 1), which bonds the semiconductor element to the mount (see e.g., solder paste made of lead-tin is printed on a mounting portion of the semiconductor element 5 on the upper surface of the metal circuit board 2 in a predetermined pattern corresponding to the shape of the semiconductor element 5 using a screen-printing technique. Next, the semiconductor element 5 is mounted on the solder 4, and the semiconductor element 5 is bonded to the upper surface of the metal circuit board 2 by heating and melting the solder at a temperature of about 300 ° C., Para [0025]), includes a perimeter (see e.g., the solder disposed on the surface of the mount has a perimeter),
the surface of the mount being above the groove (see e.g., as shown in modified Figure 1 the surface of the mount is above the frame-shaped groove 6),
Ochi does not explicitly teach
“upon bonding the semiconductor element to the mount of the surface of the circuit pattern, the perimeter of the solder includes at least a portion where the solder contacts the surface of the mount,..
the groove is positioned asymmetrically with respect to the semiconductor element when viewed in plan view after bonding the semiconductor element to the mount”.
In a similar field of endeavor Kuramochi teaches a similar concept, in the context of an underfill resin 20 rather than a solder layer, where the underfill has an outermost perimeter with a portion contacting the surface of the mount and a portion in a recess 24.
Kuramochi teaches
upon bonding the semiconductor element to the mount of the surface of the circuit pattern (see e.g., semiconductor element 14 bonded to the mounted on the surface of a printed wiring board 12 in a flip chip connection, Para [0030], Figures 3-4),
the perimeter of the solder includes a first portion where the solder contacts the surface of the mount, (see e.g., the portion of the underfill resin 20 includes a perimeter where a portion of it is in contact with the surface mount and a portion is in the recess 24, Figures 3-4),
the groove is positioned asymmetrically with respect to the semiconductor element when viewed in plan view after bonding the semiconductor element to the mount (see e.g., a recess portion 24 is formed in the solder resist layer 22 in a region between the corner portion of the semiconductor chip 14 and the corner portion of the frame-shaped dam 16 being opposed to the corner portion of the frame-shaped dam 16 hence is asymmetrically positioned with respect to the semiconductor chip 14, Para [0032], Figures 3-4).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Kuramochi’s teachings of upon bonding the semiconductor element to the mount of the surface of the circuit pattern, the perimeter of the solder includes at least a portion where the solder contacts the surface of the mount,.. the groove is positioned asymmetrically with respect to the semiconductor element when viewed in plan view after bonding the semiconductor element to the mount in the method of Ochi in order to prevent overflow of the underfill.
Ochi does not explicitly teach
“the groove is the only groove in the mount,”
A rearrangement of parts is held to be an obvious matter of design choice. See In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); See also In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
In a similar field of endeavor Mori teaches a single concave portion 105 formed outside the position of the chip size package 102 on the mounting substrate 100 (see e.g., Paras [0014], [0020], Figure 1).
In the instance, Mori discloses positioning the groove outside the position of the chip size package 102. Positioning the groove such that it is in the mount would be obvious as a mere rearrangement of parts.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Mori’s teachings of wherein the groove is the only groove in the mount in the method of Ochi as it is a routine design choice to achieve predictable results.
Regarding claim 14, Ochi, as modified by Kuramochi and Mori, teaches the limitations of claim 11 as mentioned above. Ochi further teaches
wherein the perimeter of the solder is an outermost perimeter of the solder, and the outermost perimeter of the solder includes another portion where the solder is in the groove (see e.g., upon bonding the semiconductor element 5 to the upper surface of the metal circuit board 2 the outermost perimeter of the solder is in the groove, Figure 1).
Ochi does not explicitly teach
“wherein the perimeter of the solder is an outermost perimeter of the solder, and the outermost perimeter of the solder includes the portion where the solder contacts the surface of the mount”.
In a similar field of endeavor Kuramochi teaches
wherein the perimeter of the solder is an outermost perimeter of the solder, and the outermost perimeter of the solder includes the portion where the solder contacts the surface of the mount (see e.g., the outermost portion of the underfill resin 20 includes an outermost perimeter where a portion of it is in contact with the surface mount and a portion is in the recess 24, Figures 3-4).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Kuramochi’s teachings of wherein the perimeter of the solder is an outermost perimeter of the solder, and the outermost perimeter of the solder includes the portion where the solder contacts the surface of the mount in the method of Ochi in order to prevent overflow of the underfill.
Conclusion
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/FAKEHA SEHAR/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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