DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 12-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Paynter et al. (“Paynter” US 2021/0307218).
Regarding claim 1, Paynter discloses a semiconductor mounting structure (Figure 2) comprising:
a first semiconductor component (area enclosed shown in modified Figure 2);
a first board (204 and area between solder balls 291, shown in modified Figure 2) on which the first semiconductor component is mounted (shown in Figure 2);
a second board (290) on which the first board is mounted (shown in Figure 2); and
a housing (206 is considered a housing for the device because it structurally supports the device and provides protection for the device, namely EMI shielding) disposed outside the second board (290, see Figure 2) and disposed with a space interposed between the housing and the second board (290, see Figure 2, which shows a space separating the second board 290 and the housing 206),
wherein a second semiconductor component (282) is mounted on a surface of the first board (204, modified Figure 2) facing the second board (290, shown in Figure 2),
the second board (290) has an opening portion (cavity 292, also labeled in modified Figure 2) at least at a position facing the second semiconductor component (282) of the first board (240, shown in Figure 2), and
the opening portion (292, labeled in modified Figure 2) is exposed to the space between the second board (290) and the housing (206, see Figure 2 which shows that the opening 292 of the second board is exposed to or connected to the space interposed between the second board 290 and the housing 206), and heat generated in the second semiconductor component (282) is radiated toward the space through the opening portion (heat generated by the semiconductor component 282 would be radiated to the external environment, and the opening is between the second board 290 and the housing 206, see Figure 2, heat would be transferred through the opening to the external space).
Regarding claim 2, Paynter discloses wherein the first semiconductor component (area enclosed shown in modified Figure 2) is a semiconductor package in which a first semiconductor element (210) is sealed with a resin (207, area enclosed in modified Figure 2, para. [0039] discloses 207 as a resin), and the second semiconductor component (282) is a second semiconductor element in which an external terminal (one solder ball 241, shown in modified Figure 2)) is formed on a mounting surface (bottom surface of first board 204) of the second semiconductor component (282, shown in Figure 2).
Regarding claim 3, Paynter discloses wherein in the first semiconductor component (area enclosed shown in modified Figure 2), a peripheral portion of a mounting surface (portion of mounting surface with solder balls 291) of the first semiconductor component is mounted on the first board (204, shown in modified Figure 2), and in the second semiconductor component (282), a mounting surface of the second semiconductor component (282, mounting surface of 282 is the surface of 282 with solder balls 283) is mounted to face the first board (282 mounting surface faces the first board 204, shown in Figure 2), and
mounting locations of the first semiconductor component (locations of solder balls 291) and the second semiconductor component (283) are formed at positions that do not overlap in a longitudinal direction of the first board (shown in Figure 2, vertical axes intersecting the center of the solder balls 291 and 283 do not intersect).
Regarding claim 4, Paynter discloses wherein a width of the first semiconductor component in a longitudinal direction (shown in modified Figure 2) is larger than a width of the second semiconductor component in the longitudinal direction (282, shown in modified Figure 2), and a solder pattern of the first board on which the first semiconductor component is mounted (solder balls 291) is formed outside an outer shape of the second semiconductor component (282, shown in Figure 2, the solder balls are mounted outside the perimeter of the component 282).
Regarding claim 5, Paynter discloses wherein the opening portion (shown in modified Figure 2) of the second board (290) is larger than an outer shape of the second semiconductor component (282, demonstrated in Figure 2).
Regarding claim 6, Paynter discloses wherein the first board (shown in modified Figure 2) includes a member (280, shown as part of the first board in modified Figure 2) having the same material property (both 280 and 282 are integrated devices/dies, which are comprised of the same materials) and dimension (Figure 2 shows 280 and 282 are both chips and have the same dimension, which is interpreted to be appearing as a 2D object in the plan view in Figure 2) as the second semiconductor component (282) on a surface opposite to a surface on which the second semiconductor component (282) is mounted (see Figure 2).
Regarding claim 7, Paynter discloses wherein the member (280) is disposed at a position overlapping the second semiconductor component (282) via the first board (280 is overlapping 282, shown in Figure 2).
Regarding claim 12, Paynter discloses wherein a third thermal conductor (222, interconnects are metallic, thus also conduct heat) is connected to the first semiconductor component (210, connection shown in Figure 2, as 222 is the metallization of substrate 202).
Regarding claim 13, Paynter discloses wherein the third thermal conductor (222) is connected to a housing (207, area shown in modified Figure 2, portion of housing 207 is in contact, thus connected, with 222).
Regarding claim 14, Paynter discloses wherein the first board (shown in modified Figure 2) has first solder patterns (labeled in modified Figure 2) in which solder patterns match each other on both surfaces of the first board (shown in modified Figure 2).
Regarding claim 15, Paynter discloses wherein the second board (290) has at least one second solder pattern (261, shown in Figure 2).
Regarding claim 16, Paynter discloses:
The semiconductor mounting structure according to claim 15, wherein a plurality of the second solder patterns (261) are provided around the opening portion (shown in modified Figure 2) of the second board (290, shown in modified Figure 2, solder patterns 261 are around the opening).
Regarding claim 17, Paynter discloses wherein an area of the second solder pattern (261) is larger than an area of individual solder forming the first solder pattern (241, demonstrated in modified Figure 2).
Regarding claim 18, Paynter discloses wherein the first semiconductor (210) component is a semiconductor memory (para. [0038] discloses 210 as including a memory).
Regarding claim 19, Paynter discloses wherein the first board (shown in modified Figure 2) is a system-on-chip board.
While Paynter does not explicitly disclose the first board as an SoC board, Paynter’s first board (shown in modified Figure 2) comprises conductive interconnects and dielectric materials (elements 242 and 240, para. [0023], [0071]), which the present invention discloses in the specification (para. [0040]) as an example structure for the SoC board. Thus, Paynter has disclosed applicant’s intended structure for an SoC board.
Modified Figure 2, Paynter
PNG
media_image1.png
579
1076
media_image1.png
Greyscale
PNG
media_image2.png
627
975
media_image2.png
Greyscale
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Paynter (US 2021/0307218) as applied to claim 1 above, and further in view of Machida (US 2007/0096292).
Regarding claim 8, Paynter does not disclose wherein a thermal conductive member is connected to the second semiconductor component.
Machida discloses wherein a thermal conductive member (16) is connected to the second semiconductor component (14, shown in Figure 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Machida into the teachings of Paynter to include a thermal conductive member connected to the second semiconductor component for the purpose of radiating heat generated in the semiconductor component to the outside of the device (Machida, para. [0079]).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Paynter (US 2021/0307218) and Machida (US 2007/0096292) as applied to claim 8 above, and further in view of Yu et al. (“Yu” US 2019/0006316).
Regarding claim 9, Paynter and Machida do not disclose wherein the thermal conductive member includes a first thermal conductor connected to the second semiconductor component, and
a second thermal conductor having one end connected to the first thermal conductor via the opening portion and the other end disposed outside the second board, and
the first thermal conductor is softer than the second thermal conductor.
Yu discloses wherein the thermal conductive member includes a first thermal conductor (128) connected to the second semiconductor component (102, shown in Figure 14), and
a second thermal conductor (130) having one end connected to the first thermal conductor (portion of 130 shown in modified Figure 14) via the opening portion (shown in processing step 15J, the opening is the niche defined by inner sides of housing 124 and the bottom surface of component 102) and the other end disposed outside the second board (108A, shown in modified Figure 14), and
the first thermal conductor (128) is softer than the second thermal conductor (130, para. [0040] discloses 128 as a polymer, and 130 as a metal, and a polymer is softer than metal).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Yu into the teachings of Machida and Paynter to include the thermal conductive member includes a first thermal conductor connected to the second semiconductor component, and a second thermal conductor having one end connected to the first thermal conductor via the opening portion and the other end disposed outside the second board, and the first thermal conductor is softer than the second thermal conductor for the purpose of improving dissipation of heat through the bottom surface of the die rather than heat dissipating upwards towards other dies which would reduce thermal cross-talk (Yu, para. [0096]).
Regarding claim 10, Paynter and Machida do not disclose wherein the other end of the second thermal conductor is connected to a housing disposed outside the second board.
Yu discloses wherein the other end of the second thermal conductor (130, portion shown in modified Figure 14) is connected to a housing (molding compound 124, labeled in process step 15C) disposed outside the second board (108A).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Yu into the teachings of Machida and Paynter to include the other end of the second thermal conductor is connected to a housing disposed outside the second board for the purpose of improving dissipation of heat through the bottom surface of the die rather than heat dissipating upwards towards other dies which would reduce thermal cross-talk and providing structural support from the housing (Yu, para. [0039] and [0096]).
Regarding claim 11, Paynter does not disclose wherein the second board includes a notched portion communicating with the opening portion, and
the second thermal conductor is disposed along the notched portion.
Machida discloses wherein the second board (101) includes a notched portion (shown in modified Figure 3) communicating with the opening portion (shown in modified Figure 3, “communicating with” is interpreted as being a part of, or being connected to), and
the second thermal conductor (16) is disposed along the notched portion (16 is disposed along the notched portion of 101, shown in modified Figure 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Machida into the teachings of Paynter to include wherein the second board includes a notched portion communicating with the opening portion, and the second thermal conductor is disposed along the notched portion for the purpose of improving heat radiating efficiency by exposing more surface area of the thermal conductor (Machida, para. [0080]).
Modified Figure 3, Machida
PNG
media_image3.png
344
672
media_image3.png
Greyscale
Modified Figure 14, Yu
PNG
media_image4.png
582
756
media_image4.png
Greyscale
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are not persuasive. Applicant argues that Paynter fails to disclose or suggest the features recited in amended claim 1 because “the connection [of solder joints between two boards] is generally completed by filling a space between the connected terminals with underfill resin. In light of this, Applicant contends that the patch substrate 206 of Paynter is not a member that is arranged with a space interposed between itself and the second board but a member that is fixed to the second board without any space therebetween and seals the cavity. As such, Applicant contends that the patch substrate 206 is obviously different in structure from the "housing" according to amended claim 1.” The Examiner respectfully disagrees.
Applicant’s argument relies on the presence of an underfill material filling a gap between the patch substrate 206 and the board 290 of Paynter. However, there is no suggestion or teaching of such an underfill in Paynter, and Figure 2 does not show any underfill material filling the gap between patch substrate 206 and board 290. While the Examiner understands underfill material is commonly used in the art to protect and insulate solder joints, Paynter has not disclosed any underfill material for the solder joints 261 between the patch substrate and the board 290. Thus, Paynter discloses a space between the patch substrate 206 and board 290 as claimed in amended claim 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Genevieve G Bullard-Connor/ Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899