DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Fulford et al (US Publication No. 2021/0217666) in view of Liu (US Publication No. 2019/0096898).
Regarding claim 1, Fulford discloses a long channel transistor structure Fig 1-15 comprising: a first transistor array Fig 2, 200A_1 adjacent to a second transistor array Fig 2, 200A_2; a third transistor array Fig 2, 200B_1 adjacent to a fourth transistor array Fig 2, 200B_2, wherein the third transistor array Fig 2, 200B_1 and the fourth transistor array Fig 2, 200B_2 are arranged above the first transistor array Fig 2, 200A_1 and the second transistor array Fig 2, 200A_2 ¶0054-0057; and a continuous channel path through channels of the first transistor array Fig 2, 200A_1 ¶0054-0057, the second transistor array Fig 2, 200A_2 ¶0054-0057; a second continuous channel path through channels the third transistor array, and the fourth transistor array¶0048, 0054-0057 Fig 1-15. Fulford discloses all the limitations but silent on the single continuous channel path for first transistor array to fourth transistor array. Whereas Liu discloses a transistor structure Fig 1 comprising: a first transistor array Fig 1, 102_1 adjacent to a second transistor array Fig 1,102_2; a third transistor array Fig 1,102_3 adjacent to a fourth transistor array Fig 1,102_m, and a continuous channel path through channels of the first transistor array¶0019-0022, the second transistor array¶0019-0022, the third transistor array, and the fourth transistor array¶0019-0022 Fig 1. Fulford and Liu are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fulford because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fulford and incorporate the teachings of Liu to improve scaling design and efficiency.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Fulford et al (US Publication No. 2021/0217666) in view of Liu (US Publication No. 2019/0096898)and in further view of Liebmann et al (US Publication No. 2022/0181441).
Regarding 2, Fulford discloses all the limitations but silent on having a common gate. Whereas Liebmann discloses a common gate electrically connected to all individual gates of the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array ¶0005, 0053. Fulford and Liebmann are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fulford because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fulford and incorporate the teachings of Liebmann to improve scaling of logic design and efficiency.
Claims 3, 5, 7-8, 10 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Fulford et al (US Publication No. 2021/0217666) in view of Liu (US Publication No. 2019/0096898) and in further view of Or Bach et al (US Publication No. 2023/0033173).
Regarding claim 3, Fulford discloses all the limitations but silent on the specifics of the contacts. Whereas Or Bach discloses : a first source drain contact arranged at one end of the continuous channel path; and a second source drain contact arranged at the other end of the continuous channel path Fig 23D. Fulford and Or Bach are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fulford because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fulford and incorporate the teachings of Or Bach as an alternative arrangement to improve interconnectivity.
Regarding claim 5, Or Bach discloses wherein the continuous channel path comprises: a first electrical connection between the channel of the first transistor array and the channel of the third transistor array, a second electrical connection between the channel of the first transistor array and the channel of the second transistor array, and a third electrical connection between the channel of the second transistor array and the channel of the fourth transistor array Fig 23D.
Regarding claim 7, Or Bach discloses wherein the first electrical connection and the second electrical connection are arranged at opposite ends of the first transistor array; and wherein the second electrical connection and the third electrical connection are arranged at opposite ends of the second transistor array Fig 23D.
Regarding claim 8, Fulford discloses a long channel transistor structure comprising Fig 1-15: a first transistor array Fig 2, 200A_1 adjacent to a second transistor array Fig 2, 200A_2; a third transistor array Fig 2, 200B_1 adjacent to a fourth transistor array Fig 2, 200B_2, wherein the third transistor array and the fourth transistor array are arranged above the first transistor array and the second transistor array Fig 1-15. Fulford discloses all the limitation but silent on the connection. Fulford discloses all the limitations but silent on the single continuous channel path for first transistor array to fourth transistor array. Whereas Liu discloses a transistor structure Fig 1 comprising: a first transistor array Fig 1, 102_1 adjacent to a second transistor array Fig 1,102_2; a third transistor array Fig 1,102_3 adjacent to a fourth transistor array Fig 1,102_m, and a continuous channel path through channels of the first transistor array¶0019-0022, the second transistor array¶0019-0022, the third transistor array, and the fourth transistor array¶0019-0022 Fig 1. Fulford and Liu are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fulford because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fulford and incorporate the teachings of Liu to improve scaling design and efficiency. Fulford discloses all the limitations but silent on the specifics of the contacts. Whereas Or Bach discloses interconnect structures forming a continuous electrical path through channels of the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array Fig 23D. Fulford and Or Bach are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fulford because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fulford and incorporate the teachings of Or Bach as an alternative arrangement to improve interconnectivity.
Regarding claim 10, Fulford discloses all the limitations but silent on the specifics of the contacts. Whereas Or Bach discloses : a first source drain contact arranged at one end of the continuous electrical path; and a second source drain contact arranged at the other end of the continuous electrical path Fig 23D. Fulford and Or Bach are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fulford because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fulford and incorporate the teachings of Or Bach as an alternative arrangement to improve interconnectivity.
Regarding claim 12,Or Bach in view of Fulford discloses wherein the interconnect structures comprise: a first electrical connection between the channel of the first transistor array and the channel of the third transistor array, a second electrical connection between the channel of the first transistor array and the channel of the second transistor array, and a third electrical connection between the channel of the second transistor array and the channel of the fourth transistor array Fig 23D.
Regarding claim 13, Or Bach in view of Fulford discloses wherein the first electrical connection and the second electrical connection are arranged at opposite ends of the first transistor array; and wherein the second electrical connection and the third electrical connection are arranged at opposite ends of the second transistor array Fig 23D.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Fulford et al (US Publication No. 2021/0217666) in view of Liu (US Publication No. 2019/0096898)and in further view of Lilak et al (US Publication No. 2022/0344376).
Regarding 4, Fulford discloses all the limitations but silent on the self-aligned contact. Whereas Lilak discloses wherein the first source drain contact is self-aligned to an end-most gate spacer of the third transistor array; and wherein the second source drain contact is self-aligned to an end-most gate spacer of the fourth transistor array Fig 1A. Fulford and Lilak are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fulford because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fulford and incorporate the teachings of Lilak for ease in manufacturing.
Claim 6 is are rejected under 35 U.S.C. 103 as being unpatentable over Fulford et al (US Publication No. 2021/0217666) in view of Liu (US Publication No. 2019/0096898) and in further view of Or Bach et al (US Publication No. 2023/0033173) and Lilak et al (US Publication No. 2022/0344376).
Regarding claim 6, Fulford discloses all the limitations but silent on arrangement of the interconnect. Lilak in view of Fulford discloses wherein the first electrical connection extends from a fin of the first transistor array to a fin of the third transistor array, wherein the third electrical connection extends from a fin of the second transistor array and the fourth transistor array Fig 1G-1J. Fulford and Lilak are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fulford because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fulford and incorporate the teachings of Lilak for ease in manufacturing.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Fulford et al (US Publication No. 2021/0217666) in view of Liu (US Publication No. 2019/0096898) and Or Bach et al (US Publication No. 2023/0033173) and in further view of Liebmann et al (US Publication No. 2022/0181441).
Regarding 9, Fulford discloses all the limitations but silent on having a common gate. Whereas Liebmann discloses a common gate electrically connected to all individual gates of the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array ¶0005, 0053. Fulford and Liebmann are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fulford because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fulford and incorporate the teachings of Liebmann to improve scaling of logic design and efficiency.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Fulford et al (US Publication No. 2021/0217666) in view of Liu (US Publication No. 2019/0096898) and Or Bach et al (US Publication No. 2023/0033173) and in further view of Lilak et al (US Publication No. 2022/0344376).
Regarding 11, Fulford discloses all the limitations but silent on the self-aligned contact. Whereas Lilak discloses wherein the first source drain contact is self-aligned to an end-most gate spacer of the third transistor array; and wherein the second source drain contact is self-aligned to an end-most gate spacer of the fourth transistor array Fig 1A. Fulford and Lilak are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fulford because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fulford and incorporate the teachings of Lilak for ease in manufacturing.
Claims 14, 17, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Thomas et al (US Publication No. 2023/0395697) in view of Or Bach et al (US Publication No. 2023/0033173).
Regarding claim 14, Thomas discloses a long channel transistor structure comprising: a first transistor array Fig 1A-1D, Fig 2A-2B, 102b1/102b2 and 102b2/102a2 comprising a first series of short channel devices ¶0027-0030 and a first continuous channel¶0027-0030; a second transistor array Fig 1A-1D, Fig 2A-2B, 102b1/102b2 and 102b2/102a2 comprising a second series of short channel devices and a second continuous channel¶0027-0030. Thomas discloses all the limitations but silent on the vertical interconnect. Whereas Or Bach discloses and a vertical interconnect structure electrically connecting the first continuous channel to the second continuous channel Fig 23D. Thomas and Or Bach are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Thomas because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Thomas and incorporate the teachings of Or Bach as an alternative arrangement to improve interconnectivity.
Regarding claim 17, Or Bach discloses a first source drain contact arranged at one end of the first transistor array opposite the vertical interconnect structure; and a second source drain contact arranged at the other end of the second transistor array opposite the vertical interconnect structure Fig 23D.
Regarding claim 19, Or Bach discloses wherein the vertical interconnect structure comprises: an electrical connection between a first channel of the first transistor array and a second channel of the second transistor array Fig 23D.
Regarding claim 20, Or Bach discloses wherein the first electrical connection and the second electrical connection are arranged at opposite ends of the first transistor array; and wherein the second electrical connection and the third electrical connection are arranged at opposite ends of the second transistor array Fig 23D.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Thomas et al (US Publication No. 2023/0395697) in view of Or Bach et al (US Publication No. 2023/0033173) and in further view of Liebmann et al (US Publication No. 2022/0181441).
Regarding 15, Fulford discloses all the limitations but silent on having a common gate. Whereas Liebmann discloses a common gate electrically connected to the devices ¶0005, 0053. Thomas and Liebmann are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Thomas because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Thomas and incorporate the teachings of Liebmann to improve scaling of logic design and efficiency.
Claim 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Thomas et al (US Publication No. 2023/0395697) in view of Or Bach et al (US Publication No. 2023/0033173) and in further view of Lilak et al (US Publication No. 2022/0344376).
Regarding 16, Thomas discloses all the limitations but silent on the self-aligned contact. Whereas Lilak discloses wherein the vertical interconnect structure is self-aligned to an end-most gate spacers of each of the first transistor array and the second transistor array Fig 1A. Fulford and Lilak are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fulford because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fulford and incorporate the teachings of Lilak for ease in manufacturing.
Regarding claim 18, Lilak discloses wherein the first source drain contact is self-aligned to an end-most gate spacer of the first transistor array; and wherein the second source drain contact is self-aligned to an end-most gate spacer of the second transistor array Fig 1A.
Response to Arguments
Applicant’s arguments, see Page 8-25, filed 12/18/2025, with respect to the rejection(s) of claims 1-20 under USC 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811