DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9 December 2025 has been entered.
Response to Amendment
The Office acknowledges receipt on 9 December 2025 of Applicants’ amendments in which claims 1 and 11 are amended. The Office withdraws the claim objections identified in the Office Communication dated 10 October 2025 in view of the amendments, but maintains the indefiniteness rejection of claim 1.
Response to Arguments
Applicants’ arguments filed 9 December 2025 have been considered but are not persuasive. With the exceptions discussed below, Applicants’ arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Applicants argue in the penultimate paragraph of page 7 and with respect to independent claim 1 that “in the paragraph that applies the cited reference Hong there is a random citation to Paul, but no explanation is given about this reference. Therefore, the statement of the rejection and the body of the rejection do not correspond to each other.” The Office cites Paul for the motivation – identified in italic print (for emphasis of quotation) immediately preceding both the reference to Paul and the paragraph number within Paul’s disclosure from which the quoted material is acquired – for modifying the teachings of Sengupta with those of Hong.
Applicants argue in the second paragraph of page 8 through page 10 and with respect to amended independent claim 11 that in Provisional Application 63/335,137 – which provides the basis of priority with respect to the instant application for the applied reference of Wang et al. (US2023/0345693) – the “identified source/drains do not appear to connect to the identified contact.” See, e.g., first paragraph of page 9 of Applicants’ arguments.
Amended independent claim 11 is rejected over the combined teachings of Sengupta, Hwang, and Wang and recites, in relevant part, “a shared contact, wherein the shared contact is connected to an upper source/drain of the upper transistor and a bottom the bottom source/drain of the bottom transistor, and wherein the shared contact is in contact and extends along a surface of a nanosheet of the plurality of nanosheets of the bottom dummy device, wherein the shared contact further contacts the gate structure.” Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance, Sengupta teaches in Figs. 2A, 3, and 4 a shared contact (208-Y), wherein the shared contact (208-Y) is connected (indirectly/directly/ electrically/thermally) to an upper source/drain (210/212) of the upper transistor ([246/254]) and the bottom source/drain (222/224) of the bottom transistor ([239/244]) {¶0070, 0071}.
Wang teaches in Fig. 1C and paragraph [0064] a shared contact (134, BCT2 and potentially central 113 and/or central 116) [that is indirectly/directly/electrically/thermally connected to an upper source/drain (e.g., 114/118) of an upper transistor (e.g., N1/PG1) and a bottom source/drain (e.g., 114/116) of a bottom transistor (e.g., P1)] is in contact (electrical/physical) [with] and extends along a surface (e.g., bottom/left-side surface) of a nanosheet (112) of a plurality of nanosheets (112) of the bottom dummy device (D1), wherein the shared contact (134, BCT2 and potentially central 113 and/or central 116) further contacts the gate structure (109, 120, 122 of D1). These features disclosed by Wang’s non-provisional application are similarly illustrated in the drawings on pages 6 and 8-10 and described in the written material of pages 5 and 14 of Wang’s Provisional Application 63/335,137. The motivation for combining the teachings of Wang with those of Sengupta is identified below in the rejection of claim 11.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following subject matter must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 11, lines 8 and 9, recites “the inner spacer is only located adjacent to the bottom source/drain,” which is not illustrated by the drawings because the drawing do not illustrate an inner spacer in isolation from everything other than a bottom source/drain.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1 and 11 are objected to because of the following informalities:
Claim 1, lines 8 and 9, recites “a shared gate that extends through the oxide layer to connected a plurality of upper channel layers,” which should read “a shared gate that extends through the oxide layer to connect a plurality of upper channel layers” for proper composition.
Claim 11, lines 13 and 14, recites “the shared contact is in contact and extends along a surface of a nanosheet,” which should read “the shared contact is in contact with and extends along a surface of a nanosheet” for proper composition.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 11, lines 8 and 9, recites “the inner spacer is only located adjacent to the bottom source/drain,” which is new matter because the application does not disclose an inner spacer in isolation from everything other than a bottom source/drain. Claims 12-17 are rejected due to their dependence from base claim 11.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 7, recites “the upper transistors and the bottom transistors,” which is indefinite because it lacks a proper antecedent basis.” For the purpose of compact prosecution and to better comport with the remainder of the claim, this subject matter will be interpreted as “the upper transistor and the bottom transistor.” Claims 2-10 are rejected due to their dependence from base claim 1.
Claim 1, line 13, recites “the lower gate regions,” which is indefinite because it lacks a proper antecedent basis.” For the purpose of compact prosecution and to better comport with the remainder of the claim, this subject matter will be interpreted as “lower gate regions.” Claims 2-10 are rejected due to their dependence from base claim 1.
Claim 11, lines 8 and 9, recites “the inner spacer is only located adjacent to the bottom source/drain,” which is indefinite because the application does not disclose an inner spacer in isolation from everything other than a bottom source/drain and the Office is unable to determine how this feature may be achieved based on the application. For the purpose of compact prosecution and to better comport with the application, this subject matter will be interpreted as “the inner spacer is located adjacent to the bottom source/drain.” Claims 12-17 are rejected due to their dependence from base claim 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sengupta et al. (US20200135735A1) in view of Hwang et al. (US20230354570A1), Wu et al. (US20200203355A1), Hong et al. (US20220367520A1), Paul et al. (US20200111798A1), and Fan et al. (US20230422520A1).
Regarding claim 1, as interpreted in view of the indefiniteness rejection, Sengupta teaches in Figs. 2A, 3, and 4 a microelectronic structure comprising:
a plurality of stacked transistors ([239/244], [246/254]) {¶0062, 0063}; and
wherein the plurality of stacked transistors (214 and/or 226, 239 and/or 244, 246 and/or 254) includes a shared device (214 and/or 226, 239 and/or 244, 246 and/or 254) that includes a bottom transistor ([239/244]) and an upper transistor ([246/254]), wherein the upper transistor ([246/254]) is not in vertical alignment (e.g., laterally offset) with the bottom transistor ([239/244]) {¶0069};
wherein the plurality of stacked transistors (214 and/or 226, 239 and/or 244, 246 and/or 254) includes an isolated upper transistor ([254/246]), wherein a gate region (214) of the isolated upper transistor ([254/246]) is not connected (physically and directly) to a lower gate (226) located in a bottom region of the plurality of stacked transistors (214 and/or 226, 239 and/or 244, 246 and/or 254).
Sengupta does not teach a static random-access memory (SRAM) device.
In an analogous art, Hwang teaches in Fig. 2 and paragraphs [0016] and [0019] a static random-access memory (SRAM) device having a pair of inverters in which an upper transistor (in S2) and a lower transistor (in S1) are stacked. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sengupta’s microelectronic structure based on the teachings of Hwang to achieve a memory device with reduced area and/or simplified connections between transistors. Hwang ¶0016.
Sengupta does not teach:
wherein the plurality of stacked transistors includes an oxide layer located between the upper transistor and the bottom transistor,
wherein the shared device includes a shared gate that extends through the oxide layer and is connected to a plurality of upper channel layers of the upper transistor and a plurality of lower channel layers of the bottom transistor.
In an analogous art, Wu teaches in Figs. 9A-11 and paragraphs [0005], [0006], and [0078]-[0080] a plurality of stacked transistors (51, 52 of adjacent 50, 54) includes an oxide layer (30; ¶0068) located between an upper transistor (52 of 50) and a bottom transistor (51 of 50), a shared device (50) includes a shared gate (46) that extends through the oxide layer (30) and is connected (indirectly/directly/ electrically/thermally) to a channel layer of an upper transistor (channel of 52) and a channel layer of a bottom transistor (channel of 51). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sengupta’s microelectronic structure as modified by Hwang based on the teachings of Wu – such that a plurality of stacked transistors includes an oxide layer located between an upper transistor and a bottom transistor, and the shared device includes a shared gate that extends through the oxide layer and is connected to a channel layer of the upper transistor and a channel layer of the bottom transistor – so as to form a complementary metal-oxide-semiconductor (CMOS) structure. Wu ¶0003, 0078.
In an analogous art, Hong teaches in Fig. 1C and paragraph [0023] an upper transistor (TG-U) includes a plurality of channels (NS-U) and a lower transistor (TG-L) includes a plurality of channels (NS-L). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sengupta’s microelectronic structure as modified by Hwang and Wu based on the teachings of Hong – such that Wu’s upper transistor includes a plurality of channels and Wu’s lower transistor includes a plurality of channels – to improve drive current and electrostatics and to allow for device size scaling, increased device density and reduced area consumption. See Paul ¶0002 the quoted motivation identified in the preceding sentence.
Sengupta does not teach:
wherein the plurality of stacked transistors includes a plurality of upper gate cuts and a plurality of lower gate cuts,
wherein the upper gate cuts separate gate regions of adjacent upper transistors from each other and the lower gate cuts separate lower gate regions from each other;
wherein one of the upper gate cuts separates the isolated upper transistor and the upper transistor of the shared device.
In an analogous art, Fan teaches in Fig. 5A and paragraph [0129] that gate cuts 545 can penetrate semiconductor layer 541 and extend into isolation layer 540 to separate semiconductor layer 541 into a plurality of segments … [that] form a plurality of … transistors separated from each other by the plurality of … gate cuts 545. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sengupta’s microelectronic structure as modified by Hwang, Wu, Hong, and Paul based on the teachings of Fan – such that Sengupta’s modified plurality of stacked transistors includes a plurality of upper gate cuts and a plurality of lower gate cuts, wherein the upper gate cuts separates gate regions of Sengupta’s modified upper transistors from each other and the lower gate cuts separate Sengupta’s modified lower gate regions from each other, wherein one of the upper gate cuts separates the isolated upper transistor and the upper transistor of the shared device – so as to form a plurality of … transistors separated from each other. Fan ¶0129.
Regarding claim 2, Sengupta as modified by Hwang, Wu, Hong, Paul, and Fan teaches the microelectronic structure of claim 1, and Sengupta further teaches further comprising: a plurality of contacts (208-A, 208-VDD, 208-Y, 208-GND, 208-B, and/or similarly-hatched features) to connect to components (e.g., S, D, G) of the plurality of stacked transistors ([239/244], [246/254]) {¶0070}.
Regarding claim 3, Sengupta as modified by Hwang, Wu, Hong, Paul, and Fan teaches the microelectronic structure of claim 2, and Sengupta further teaches wherein the plurality of contacts (208-A, 208-VDD, 208-Y, 208-GND, 208-B, and/or similarly-hatched features) includes an upper gate contact (208-B), wherein the upper gate contact (208-B) is connected to a gate (214) located around the upper transistor ([246/254]) {¶0070, 0071}.
Examiner’s Note: The American Heritage Dictionary, 4th edition, defines the seventh sense (i.e., most common usage) of “around” meaning “[n]earby.”
Regarding claim 4, Sengupta as modified by Hwang, Wu, Hong, Paul, and Fan teaches the microelectronic structure of claim 2, and Sengupta further teaches wherein the plurality of contacts (208-A, 208-VDD, 208-Y, 208-GND, 208-B, and/or similarly-hatched features) includes an upper source/drain contact (208-Y), wherein the upper source/drain contact (208-Y) is connected to an upper source/drain (210/212) of the upper transistor ([246/254]) {¶0055, 0070}.
Regarding claim 5, Sengupta as modified by Hwang, Wu, Hong, Paul, and Fan teaches the microelectronic structure of claim 2, and Sengupta further teaches wherein the plurality of contacts (208-A, 208-VDD, 208-Y, 208-GND, 208-B, and/or similarly-hatched features) includes a bottom source/drain contact (208-Y), wherein the bottom source/drain contact (208-Y) is connected to a bottom source/drain (222/224) of the bottom transistor ([239/244]) {Fig. 2A; ¶0056, 0070}.
Regarding claim 6, Sengupta as modified by Hwang, Wu, Hong, Paul, and Fan teaches the microelectronic structure of claim 2, and Sengupta further teaches wherein the plurality of contacts (208-A, 208-VDD, 208-Y, 208-GND, 208-B, and/or similarly-hatched features) includes a shared contact (208-Y), wherein the shared contact (208-Y) is connected to an upper source/drain (210/212) of the upper transistor ([246/254]) and a bottom source/drain (222/224) of the bottom transistor ([239/244]) {Fig. 2A}.
Regarding claim 7, Sengupta as modified by Hwang, Wu, Hong, Paul, and Fan teaches the microelectronic structure of claim 6, and Sengupta further teaches wherein the shared contact (208-Y) includes a bottom protrusion (portion of 228/230 directly overtop 222/224) and an upper protrusion (portion of 216/218 directly overtop 210/212) {Fig. 2A}.
Regarding claim 8, Sengupta as modified by Hwang, Wu, Hong, Paul, and Fan teaches the microelectronic structure of claim 7, and Sengupta further teaches wherein the bottom protrusion (portion of 228/230 directly overtop 222/224) and the upper protrusion (portion of 216/218 directly overtop 210/212) are connected to each other by a via (portion of 216/218 disposed laterally to left of 210/212) {Fig. 2A}.
Regarding claim 9, Sengupta as modified by Hwang, Wu, Hong, Paul, and Fan teaches the microelectronic structure of claim 8, and Sengupta further teaches wherein the bottom protrusion (portion of 228/230 directly overtop 222/224) extends along a first axis (x-axis) and the upper protrusion (portion of 216/218 directly overtop 210/212) extends along a second axis (y-axis) {Fig. 2A}.
Regarding claim 10, Sengupta as modified by Hwang, Wu, Hong, Paul, and Fan teaches the microelectronic structure of claim 9, and Sengupta further teaches wherein the first axis (x-axis) is perpendicular to the second axis (y-axis) {Fig. 2A}.
Claim(s) 11-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sengupta in view of Hwang and Wang et al. (US20230345693A1), relying on Wang et al. U.S. Provisional Application Number 63/335,137 for a priority date of 4/26/22.
Regarding claim 11, as interpreted in view of the indefiniteness rejection, Sengupta teaches in Figs. 2A, 3, and 4 a microelectronic structure comprising:
a plurality of stacked transistors ([239/244], [246/254]) {¶0062, 0063};
each of the plurality of stacked transistors ([239/244], [246/254]) includes a bottom transistor ([239/244]) and an upper transistor ([246/254]), wherein the upper transistor ([246/254]) is not in vertical alignment (e.g., laterally offset) with the bottom transistor ([239/244]) {¶0069};
a shared contact (208-Y), wherein the shared contact (208-Y) is connected (indirectly/directly/electrically/thermally) to an upper source/drain (210/212) of the upper transistor ([246/254]) and the bottom source/drain (222/224) of the bottom transistor ([239/244]) {¶0070, 0071}.
Sengupta does not teach a static random-access memory (SRAM) device.
In an analogous art, Hwang teaches in Fig. 2 and paragraphs [0016] and [0019] a static random-access memory (SRAM) device having a pair of inverters in which an upper transistor (in S2) and a lower transistor (in S1) are stacked. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sengupta’s microelectronic structure based on the teachings of Hwang – to include static random-access memory (SRAM) device having a plurality of stacked transistors – so to achieve a memory device with reduced area and/or simplified connections between transistors. Hwang ¶0016.
Sengupta does not teach:
a bottom dummy device, wherein the dummy device includes a plurality of nanosheets that extends laterally from a bottom source/drain, wherein an inner spacer is located between the plurality of nanosheets, wherein the inner spacer is located adjacent to the bottom source/drain, wherein a gate structure surrounds the plurality of nanosheets and the gate structure contacts the inner spacer; and the shared contact is in contact [with] and extends along a surface of a nanosheet of the plurality of nanosheets of the bottom dummy device, wherein the shared contact further contacts the gate structure.
In an analogous art, Wang teaches in Fig. 1C and paragraph [0064] a bottom dummy device (D1), wherein the bottom dummy device (D1) includes a plurality of nanosheets (112) that extends laterally from a bottom source/drain (116), wherein an inner spacer (2nd from bottommost 126 in D1) is located between the plurality of nanosheets (112), wherein the inner spacer (2nd from bottommost 126 in D1) is located adjacent to the bottom source/drain (116), wherein a gate structure (109, 120, 122) surrounds the plurality of nanosheets (112) and the gate structure (109, 120, 122) contacts the inner spacer (2nd from bottommost 126 in D1), and a shared contact (134, BCT2 and potentially central 113 and/or central 116) [that is indirectly/directly/electrically/thermally connected to an upper source/drain (e.g., 114/118) of an upper transistor (e.g., N1/PG1) and a bottom source/drain (e.g., 114/116) of a bottom transistor (e.g., P1)] is in contact (electrical/physical) [with] and extends along a surface of a nanosheet (112) of a plurality of nanosheets (112) of the bottom dummy device (D1), wherein the shared contact (134, BCT2 and potentially central 113 and/or central 116) further contacts the gate structure (109, 120, 122) {see pages 5, 6, and 14 of Wang’s priority application 63/335,137; and see Examiner’s Note below}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sengupta’s microelectronic structure as modified by Hwang based on the teachings of Wang, as identified immediately above, so as to serially connect two inverters. Wang ¶0027 and pages 5, 6, and 14 of Wang’s priority application 63/335,137.
Examiner’s Note: The American Heritage Dictionary, 4th edition, defines the second sense (i.e., second most common usage) of “along” as “[o]n a course parallel and close to.”
Regarding claim 12, Sengupta as modified by Hwang and Wang teaches the microelectronic structure of claim 11, and Sengupta further teaches wherein the shared contact (208-Y) includes a bottom protrusion (portion of 228/230 directly overtop 222/224) and an upper protrusion (portion of 216/218 directly overtop 210/212) {Fig. 2A}.
Regarding claim 13, Sengupta as modified by Hwang and Wang teaches the microelectronic structure of claim 12, and Sengupta further teaches wherein the bottom protrusion (portion of 228/230 directly overtop 222/224) and the upper protrusion (portion of 216/218 directly overtop 210/212) are connected to each other by a via (portion of 216/218 disposed laterally to left of 210/212) {Fig. 2A}.
Regarding claim 14, Sengupta as modified by Hwang and Wang teaches the microelectronic structure of claim 13, and Sengupta further teaches wherein the bottom protrusion (portion of 228/230 directly overtop 222/224) extends along a first axis (x-axis) and the upper protrusion (portion of 216/218 directly overtop 210/212) extends along a second axis (y-axis) {Fig. 2A}.
Regarding claim 15, Sengupta as modified by Hwang and Wang teaches the microelectronic structure of claim 14, and Sengupta further teaches wherein the first axis (x-axis) is perpendicular to the second axis (y-axis).
Regarding claim 16, Sengupta as modified by Hwang and Wang teaches the microelectronic structure of claim 15, but Sengupta does not teach wherein the bottom protrusion of the shared contact is in contact with a gate of the bottom dummy device.
Wang teaches in Fig. 1C and paragraph [0037] a bottom protrusion of a shared contact (134, BCT2 and potentially central 113 and/or central 116) is in contact with a gate (109) of a bottom dummy device (D1) {see pages 5, 6, and 14 of Wang’s priority application 63/335,137}. The motivation for this modification is identified with respect to base claim 11.
Regarding claim 17, Sengupta as modified by Hwang and Wang teaches the microelectronic structure of claim 16, and Sengupta further teaches wherein a bottom surface of the bottom protrusion (portion of 228/230 directly overtop 222/224) of the shared contact (208-Y) is in contact with the bottom source/drain (222/224) {Fig. 2A}.
Sengupta does not teach a bottom surface of the bottom protrusion of the shared contact is in contact with the dummy device.
Wang teaches in Fig. 1C and paragraph [0037] a bottom surface of the bottom protrusion of the shared contact (134, BCT2 and potentially central 113 and/or central 116) is in contact with the dummy device (D1) {see pages 5, 6, and 14 of Wang’s priority application 63/335,137}. The motivation for this modification is identified with respect to base claim 11.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Anderson et al. (US20190287957A1) teaches a semiconductor structure includes a vertical transport static random-access memory (SRAM) cell having a first active region and a second active region. The first active region and the second active region are linearly arranged in first and second rows, respectively. The first row of the first active region includes a first pull-up transistor, a first pull-down transistor and a first pass gate transistor, and the second row of the second active region includes a second pull-up transistor, a second pull-down transistor and a second pass gate transistor. A first gate region of the first active region extends orthogonal from the first row to the second active region, and a second gate region of the second active region extends orthogonal from the second row to the first active region.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891