DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Independent claim(s) 1, 10 and 20 and dependent claims 2, 7-8, 12-13, and 16-17 have been amended by applicant' s amendments received 24 November 2025.
Claims 14 and 15 have been canceled, and therefore the prior objections and rejections are moot.
Claims 21 and 22 were added, with no new matter being introduced.
Prior objections in relation to minor informalities, and rejections in relation to35 USC § 112(b) to claim 17 have been overcome by applicant’s amendments received 24 November 2025 and are therefore withdrawn.
Response to Arguments
Applicant's arguments filed 24 November 2025 have been fully considered but they are not persuasive.
As discussed in the interview, and noted in applicant remarks submitted 24 November 2025, the applicant suggests that the prior art of record (Veig et al., US 20210203868 A1) does not teach where a first signal path of first circuitry and a second signal path of second circuitry are connected via a first switch, and additionally where the first signal path of first circuitry and the second signal path of second circuitry are connected via an additional switch, ultimately to combine two similar portions of two columns’ readout signals (a first portion of each signal readout are combined, for example). It is also noted that the instant application is based on a single signal path for the first signal circuitry and a single second path for the second signal circuitry.
Veig notes that signal lines indicated as singular may be provided in plurality, and one of ordinary skill in the art would understand that this also includes the opposite, where signal lines indicated in plurality may be performed by a singular signal line ([0025] – [0027]), though the inclusion of additional separate tap (signal) lines of Veig allows for more diverse readout mode options ([0025] – [0027]). A ‘signal path’ which carries both tap components of a pixel’s signal is anticipated by Veig in that a singular signal line would encompass (420a) and (420b) in a single signal pathway which may carry differential signals. The inclusion of additional tap lines to support more complex readout modes does not negate the anticipation, and therefore Veig continues to anticipate some claims, including the independent claims 1, 10 and 20, as presented.
Claim Objections
Claim 22 is objected to because of the following informalities:
The verbiage introduced in line 2 “…the further switch are a single-ended switches having…” is a bit disjointed. A suggested edit for clarity would be “…are each a single-ended switch…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, 7-8, 10, 12, 16-18, 20 and 22 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Veig et al. (hereinafter Veig, US 20210203868 A1).
Regarding claim 1, Veig anticipates a method for pixel binning in a time-of-flight sensor ([0003], [0049]; Fig. 7), the method comprising:
receiving, by first circuitry, a first readout signal from a first column of a pixel array of the time-of- flight sensor ([0025] - [0026]; Fig. 2, 4 sensor (200) where pixels (211, 410) in first column have signals output to vertical signal lines (213a-213d, 420a-420d), which connect to switching circuitry (232, 431, 432) and readout circuit (231));
receiving, by second circuitry, a second readout signal from a second column of the pixel array ([0025] - [0026]; Fig. 2, 4 sensor (200) where pixels (211, 410) in second column have signals output to vertical signal lines (unlabeled), which connect to switching circuitry (232, 431, 432) and readout circuit (231));
and combining the first readout signal and the second readout signal to obtain a common analog signal ([0028], [0031], [0039]; Fig. 3A, 4 where vertical signal lines carry analog signals and two columns are connected by switching circuit (430)) useable to determine a distance based on at least two pixels of the time-of-flight sensor ([0022] - [0024], where the system operates to perform one or more time-of-flight distance determinations based on combined information from multiple pixels),
wherein the first readout signal and the second readout signal are differential signals each comprising a first signal portion and a second signal portion, ([0034], [0040], where each column is read out in multiple Taps, where Tap A may be a different time period or phase from Tap B),
and wherein combining the first readout signal and the second readout signal comprises;
connecting, by a first switch, a first signal path of the first circuitry and a second signal path of the second circuitry such that the first signal portion of the first readout signal and the first signal portion of the second readout signal are combined into a first portion of the common analog signal ([0039]; Fig. 4, where switching circuitry (431) includes multiple sets of single switches, and the first set includes a first switch connected to first vertical signal line (420a) of the left column, and a third switch connected to the first vertical signal line (unlabeled) of the right column);
and connecting, by a further switch, the first signal path of the first circuitry and the second signal path of the second circuitry such that the second signal portion of the first readout signal and the second signal portion of the second readout signal are combined into a second portion of the common analog signal ([0039]; Fig. 4, where switching circuitry (431) includes multiple sets of single switches, and the second set includes a first switch connected to second vertical signal line (420b) of the left column, and a third switch connected to the second vertical signal line (unlabeled) of the right column).
Regarding claim 2, Veig anticipates the method according to claim 1, further comprising:
controlling a switching circuit comprising at least the first switch connecting the first signal path of the first readout signal and the second signal path of the second readout signal to obtain the common analog signal ([0039] - [0040]; Fig. 4, where switches connected to both columns vertical signal lines are coupled via switches to a comparator (450)).
Regarding claim 4, Veig anticipates the method according to claim 1, further comprising:
combining signals from at least two neighboring pixels of the first column to generate the first readout signal ([0038]; Fig. 4 where the lower four pixels of left column are connected by vertical signal lines (420a) and (420b));
and combining signals from at least two neighboring pixels of the second column to generate the second readout signal ([0038]; Fig. 4 where the lower four pixels of right column are connected by vertical signal lines (unlabeled)).
Regarding claim 5, Veig anticipates the method according to claim 1, further comprising:
using correlated double sampling for the first readout signal and the second readout signal before combining the first readout signal and the second readout signal ([0029], [0039] - [0040]; Fig. 4, where the output of each tap may undergo the correlated double sampling (CDS) method before signals are combined from both columns at a comparator (450))
Regarding claim 7, Veig anticipates the method according to claim 2, wherein:
wherein controlling the switching circuit enables a combination of the first signal portion of the first readout signal and the first signal portion of the second readout signal and a combination of the second signal portion of the first readout signal and the second signal portion of the second readout signal ([0040]; Fig. 4, where readout lines from first column (420a-420d) are connected to a similar readout line from the second column at switch circuitry (431, 432) which allow for combination of similar signal portions).
Regarding claim 8, Veig anticipates the method according to claim 2, wherein:
controlling the switching circuit comprises controlling the first switch and a second switch of the switching circuit, the second switch connecting the first switch and the second signal path of the second readout signal ([0039]; Fig. 4, where switching circuitry (431) includes multiple sets of switches, and the first set includes a first switch connected to first vertical signal line (420a) of the left column, and a third switch connected to the first vertical signal line (unlabeled) of the right column).
Regarding claim 10, Veig anticipates a switched device for a time-of-flight sensor, comprising:
first circuitry configured to receive a first readout signal from a first column of a pixel array of the time-of-flight sensor ([0025] - [0026]; Fig. 2, 4 sensor (200) where pixels (211, 410) in first column output signals to vertical signal lines (213a-213d, 420a-420d), which connect to switching circuitry (232, 431, 432) and readout circuit (231));
second circuitry configured to receive a second readout signal from a second column of the pixel array ([0025] - [0026]; Fig. 2, 4 sensor (200) where pixels (211, 410) in second column output signals to vertical signal lines (unlabeled), which connect to switching circuitry (232, 431, 432) and readout circuit (231));
and a switching circuit comprising at least a first switch, the switching circuit is configured to connect a first signal path of the first circuitry and a second signal path of the second circuitry ([0039] - [0040]; Fig. 4, where switches connected to both columns vertical signal lines are coupled via switches to a comparator (450)) such that the first readout signal and the second readout signal are combined into a common analog signal ([0028], [0031], [0039]; Fig. 3A, 4 where vertical signal lines carry analog signals and two columns are connected by switching circuit (430)),
wherein the first readout signal and the second readout signal are differential signals each comprising a first signal portion and a second signal portion, ([0034], [0040], where each column is read out in multiple Taps, where Tap A may be a different time period or phase from Tap B),
wherein the first switch is configured to connect the first signal path of the first circuitry and the second signal path of the second circuitry such that the first signal portion of the first readout signal and the first signal portion of the second readout signal are combined into a first portion of the common analog signal ([0039]; Fig. 4, where switching circuitry (431) includes multiple sets of single switches, and the first set includes a first switch connected to first vertical signal line (420a) of the left column, and a third switch connected to the first vertical signal line (unlabeled) of the right column);
and wherein the switching circuit further comprises a further switch configured to connect the first signal path of the first circuitry and the second signal path of the second circuitry such that the second signal portion of the first readout signal and the second signal portion of the second readout signal are combined into a second portion of the common analog signal ([0039]; Fig. 4, where switching circuitry (431) includes multiple sets of single switches, and the second set includes a first switch connected to second vertical signal line (420b) of the left column, and a third switch connected to the second vertical signal line (unlabeled) of the right column).
Regarding claim 12, Veig anticipates the switched device according to claim 10 wherein:
each circuitry of the first and the second circuitry comprises a switched capacitor circuit enabling correlated double sampling for a respective one of the first readout signal and the second readout signal ([0029], [0038] - [0040]; Fig. 4, where each pixel includes multiple capacitors, connected to similar taps and the output of each tap may undergo the correlated double sampling (CDS) method before signals are combined from both columns at a comparator (450)).
Regarding claim 16, Veig anticipates the switched device according to claim 10, wherein:
the switching circuit further comprises a second switch configured to connect at least the first switch and the second signal path of the second circuitry such that the first readout signal and the second readout signal are combinable into the common analog signal ([0039]; Fig. 4, where switching circuitry (431) includes multiple sets of switches, and the first set includes a third switch connecting the first vertical signal line (unlabeled) of the right column to the vertical signal lines (420a) and (420c) of the left column, and all outputs are sent to a comparator (450) for combination).
Regarding claim 17, Veig anticipates the switched device according to claim 16, wherein:
the second switch connects such that the first signal portion of the first readout signal and the first signal portion of the second readout signal are combined into a first portion of the common analog signal ([0039]; Fig. 4, where switching circuitry (431) includes multiple sets of switches, and the second set includes a first switch connected to second vertical signal line (420b) of the left column, and a third switch connected to the second vertical signal line (unlabeled) of the right column),
wherein the switching circuit further comprises an additional switch connecting a third signal path of the further switch and the second signal path of the second circuitry such that the second signal portion of the first readout signal and the second signal portion of the second readout signal are combined into a second portion of the common analog signal ([0039]; Fig. 4, where switching circuitry (431) includes multiple sets of switches, and the second set includes a first switch connected to second vertical signal line (420b) of the left column, and an additional, third switch connected to the second vertical signal line (unlabeled) of the right column).
Regarding claim 18, Veig anticipates the switched device according to claim 16, wherein:
the at least first switch and the second switch are connected directly to each other ([0039]; Fig. 4, where switching circuitry (431) includes multiple sets of switches, and the first and third of the switches within a set are coupled so that their signals travel together to a first input of comparator (450)).
Regarding claim 20, Veig anticipates a non-transitory computer-readable medium having computer-readable instructions stored thereon which when executed by a computer system causes the computer system to perform a method for pixel binning in a time-of-flight sensor ([0022];Fig. 1A, where system includes controller (113) and memory (114)), the method comprising:
Receiving, by first circuitry, a first readout signal from a first column of a pixel array of the time-of- flight sensor ([0025] - [0026]; Fig. 2, 4 sensor (200) where pixels (211, 410) in first column have signals output to vertical signal lines (213a-213d, 420a-420d), which connect to switching circuitry (232, 431, 432) and readout circuit (231));
Receiving, by second circuitry, a second readout signal from a second column of the pixel array ([0025] - [0026]; Fig. 2, 4 sensor (200) where pixels (211, 410) in second column have signals output to vertical signal lines (unlabeled), which connect to switching circuitry (232, 431, 432) and readout circuit (231));
and combining the first readout signal and the second readout signal to obtain a common analog signal ([0028], [0031], [0039]; Fig. 3A, 4 where vertical signal lines carry analog signals and two columns are connected by switching circuit (430)) useable to determine a distance based on at least two pixels of the time-of-flight sensor ([0022] - [0024], where the system operates to perform one or more time-of-flight distance determinations based on combined information from multiple pixels),
wherein the first readout signal and the second readout signal are differential signals each comprising a first signal portion and a second signal portion, ([0034], [0040], where each column is read out in multiple Taps, where Tap A may be a different time period or phase from Tap B),
and wherein combining the first readout signal and the second readout signal comprises;
connecting, by a first switch, a first signal path of the first circuitry and a second signal path of the second circuitry such that the first signal portion of the first readout signal and the first signal portion of the second readout signal are combined into a first portion of the common analog signal ([0039]; Fig. 4, where switching circuitry (431) includes multiple sets of single switches, and the first set includes a first switch connected to first vertical signal line (420a) of the left column, and a third switch connected to the first vertical signal line (unlabeled) of the right column);
and connecting, by a further switch, the first signal path of the first circuitry and the second signal path of the second circuitry such that the second signal portion of the first readout signal and the second signal portion of the second readout signal are combined into a second portion of the common analog signal ([0039]; Fig. 4, where switching circuitry (431) includes multiple sets of single switches, and the second set includes a first switch connected to second vertical signal line (420b) of the left column, and a third switch connected to the second vertical signal line (unlabeled) of the right column).
Regarding claim 22, Veig anticipates the switched device according to claim 10, wherein the first switch and the further switch are a single-ended switches having a single respective input and a single respective output ([0039]; Fig. 4, where each set of switches (431, 432) within the switching circuitry includes three individual, single ended switches which connect portions of the circuitry).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Veig et al. (hereinafter Veig, US 20210203868 A1), in view of Iwane (US 20220408050 A1).
Regarding claim 3, Veig teaches the method according to claim 1.
Veig is silent on the data analysis of the readout signals including averaging.
Iwane teaches combining readout signals in a photoelectric conversion device, such as a time-of-flight camera ([0032]) which comprises averaging the first readout signal and second readout signal ([0044], [0098] - [0102]; Fig. 9, where averaging unit (8) is connected to peripheral circuit column signal lines (RVL0-RVL3), which carry inputs from pixel columns, and may average the potentials of four columns).
Therefore, to one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to modify Veig to incorporate the teachings of Iwane to average the readout signals from at least two columns within a sensor comprising a pixel array with a reasonable expectation of success. Averaging signals output from all or portions of a pixel array within a sensor is known work in the field of LIDAR. Averaging signals allows for data analysis which may mitigate erroneous outputs from pixels such as dead or hot pixels, and therefore would have predictable results to one of ordinary skill in the art of reducing the impact the signals might have on the data set.
Claim 11 is similarly rejected to claim 3.
Claim(s) 6 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Veig et al. (hereinafter Veig, US 20210203868 A1), in view of Wang et al. (hereinafter Wang, US 20160309140 A1).
Regarding claim 6, Veig teaches the method according to claim 1.
Veig does not teach activating a first or second analog-to-digital converter, while the other is deactivated, to generate a digital signal based on the common analog signal.
Wang teaches activating a first analog-to-digital converter corresponding to the first readout signal and deactivating a second analog-to-digital converter corresponding to the second readout signal or vice versa to generate a digital signal based on the common analog signal ([0063] – [0065]; Figs. 6, &A, &B, where the column ADC unit (153) may determine to choose readout from column-specific ADCs, while not reading out from others, depending on input from decoder unit (145)).
Therefore, to one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to modify Veig to incorporate the teachings of Wang to utilize analog-to-digital converters (ADCs), which are column specific, to determine which column to readout, with a reasonable expectation of success. The comparators of Veig already intake analog signals and output digital signals ([0028]), and ADCs are common in the art of image processing in LIDAR. Incorporating the column-specific ADCs of Wang in place of, or in addition to, the plurality of comparators of Veig would have a predictable result of reading out specific columns’ signals before digitizing the output which is sent for further signal processing.
As Veig and both teach a device in addition to a method, claim 13 is similarly rejected to claim 6.
Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Veig et al. (hereinafter Veig, US 20210203868 A1), in view of Yang et al. (hereinafter Yang, US 20140240569 A1).
Regarding claim 9, Veig teaches the method according to claim 2.
Veig does not teach generating a digital signal with a common analog-to-digital converter.
Yang teaches an imaging sensor (and readout method of said sensor) which generates a digital signal based on a common analog signal using a common analog-to-digital converter coupled to the switching circuit ([0014], [0046] - [0050]; Fig. 1 ADC(140) outputs digital signal input from CDS block (130), where both are common to pixel array (110) and collects input from all columns).
Therefore, to one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to modify Veig to incorporate the teachings of Yang to incorporate a common analog-to-digital converter (ADC) to digitize the analog signals together for all columns within a sensor pixel array, to create a common signal, with a reasonable expectation of success. The comparators of Veig already intake analog signals and output digital signals ([0028]), and ADCs are common in the art of image processing in LIDAR. Incorporating the common ADC of Yang in place of the comparators of Veig would have a predictable result of collecting all column (analog) signals before digitizing the output which is sent for further signal processing.
As Veig and Yang both teach a device in addition to a method, claim 19 is similarly rejected to claim 9.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Veig et al. (hereinafter Veig, US 20210203868 A1), in view of Wang et al. (hereinafter Wang, US 20160309140 A1) and further in view of Iwane (US 20220408050 A1).
Regarding claim 21, Veig as modified above teaches the switched device according to claim 13.
Veig is silent on the data analysis of the readout signals including averaging, including on the first and second signal portions of the readout signals individually.
Iwane teaches combining readout signals in a photoelectric conversion device, such as a time-of-flight camera ([0032]) which can comprise averaging a first signal portion of both the first readout signal and second readout signal and separately averaging a second signal portion of both the first readout signal and second readout signal ([0044], [0098] - [0102]; Fig. 9, where averaging unit (8) is connected to peripheral circuit column signal lines (RVL0-RVL3), which carry inputs from pixel columns, and may average the potentials of four columns).
Therefore, to one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to modify Veig to incorporate the teachings of Iwane to separately average similar portions of the readout signals from at least two columns within a sensor comprising a pixel array with a reasonable expectation of success. Averaging signals output from all or portions of a pixel array within a sensor is known work in the field of LIDAR. Averaging signals allows for data analysis which may mitigate erroneous outputs from pixels such as dead or hot pixels, and therefore would have predictable results to one of ordinary skill in the art of reducing the impact the signals might have on the data set.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Okada et al. (US 20040263645 A1) teaches an imaging device which includes an array of pixels, where pixel binning may occur separately for first and second binning lines.
Min et al. (US 20130169756 A1) teaches a depth sensor and calculation method for a time-of-flight principle, which includes a CDS/ADC circuit which may perform correlated double sampling as well as analog-to-digital converting for individual pixel signals.
Thompson et al. (US 20190082132 A1) teaches a time-of-flight sensor readout circuit, which incorporates correlated double sampling circuitry, a plurality of analog-to-digital converters for pixels and/or columns of a sensor array, and a method of readout.
Kim et al. (US 20210084245 A1) teaches an image sensor which includes averaging monitoring signal outputs for a time-of-flight sensor array which may include a correlated double sampling circuit.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kara Richter whose telephone number is (571)272-2763. The examiner can normally be reached Monday - Thursday, 8A-5P EST, Fridays are variable.
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/K.M.R./Examiner, Art Unit 3645
/ROBERT W HODGE/Supervisory Patent Examiner, Art Unit 3645