Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 10/13/2025 have been fully considered but they are not persuasive.
Regarding the rejection of claims 1 – 4, 7 – 11, and 18 – 21:
The applicant claims that “there is no feedback network as recited in claim 1” and “Loop filter 308 was identified as the recited ‘feedback network’.”
However, the examiner identified the feedback network as “feedback network 308.” The feedback network 308 is part of the sensor cell 204 (See paragraph [0033], “FIG. 3 shows a schematic diagram for an example of an optical sensor cell 300 that includes a first stage of a distributed amplifier in accordance with this description. The optical sensor cell 300 is an implementation of the sensor cell 204”). The sensor cell 204 is connected to the output of the transimpedance amplifier 602 (See paragraph [0042], “The transimpedance amplifier 602 sinks the currents output by the sensor cells 204 that are connected in parallel to the current-to-voltage converter 600.”).
Regarding the rejection of claim 5:
The applicant claims that claim 5 is not rendered obvious over the prior arts for the same reasons that claims 1 and 2 are not rendered obvious.
The examiner respectfully disagrees. Claim 5 was rejected as being unpatentable over Seyed Aliroteh in view of Fisher, as shown below.
Regarding the rejection of claims 6 and 12 - 16:
The applicant claims that claims 6 and 12- 16 are not rendered obvious over the prior arts for the same reasons that claims 1 and 2 are not rendered obvious.
The examiner respectfully disagrees. Claims 6 and 12 - 16 were rejected as being unpatentable over Seyed Aliroteh in view of Odabaee, as shown below.
Regarding the rejection of claim 17:
The applicant claims that claim 17 is not rendered obvious over the prior arts for the same reasons that claims 1 and 10 are not rendered obvious.
The examiner respectfully disagrees. Claim 17 was rejected as being unpatentable over Seyed Aliroteh in view of Lyden, as shown below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7-11 and 18-21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Seyed Aliroteh (US 20200212854 A1).
Regarding Independent Claim 1, Seyed Aliroteh teaches,
A sensor circuit (See Figs. 2C, 3, and 6), comprising:
a transimpedance amplifier (amplifier 602, Fig. 6) having a first input for receiving a measured signal (first input 220 and signal from Iout+, Fig. 6), a second input for receiving a reference signal (second input 218 and signal from Iout-, Fig. 6), and an output (output of amplifier 602, Fig. 6);
a feedback network (Feedback network 308, Fig. 3) comprising a capacitor (capacitor 504, Fig. 5) and a variable resistor (resistor 612, Fig. 6) each coupled between said output and said first input of said transimpedance amplifier (both capacitor and resistor are coupled between the input and output of the amplifier); and
a readout circuit (control circuit 208, Fig. 2C) coupled to said feedback network and having an output for providing a readout signal;
(“Referring back to FIG. 2C, in operation of the optical sensor circuit 200, the control circuit 208 may read out the sensor cells 204 as read-cells that include a two-dimensional sub-array of the sensor array 202 (i.e., a P×Q sub-array of the sensor array 202). Some implementations may employ a different sized read-out cell. The control circuit 208 controls formation of the read-out cell by enabling select sensor cells 204 of the sensor array 202 to provide output currents to the current-to-voltage conversion circuit 206. The currents output by the different sensor cells 204 of a row are summed on the conductor connecting the sensor cells 204 to the current-to-voltage conversion circuit 206. The control circuit 208 enables, and provides weighting values to, one of the summation circuits 212 to sum the signals produced by the different rows of the read-out cell 234.
In some implementations of the optical sensor circuit 200, the control circuit 208 may also enable output by the sensor cells 204 that are adjacent to the read-out cell 234 for ambient light measurement. The difference of the signal on the input 218 and the input 220 may be applied to improve noise immunity.” Paragraphs [0040] – [0041])
wherein in a conversion mode, said readout circuit provides said readout signal based on one sample of said output of said transimpedance amplifier; and
(“Each of the sensor cells 204 includes an output 214 and an output 216. In a row, the outputs 214 of the sensor cells 204 are connected and provided to an input 218 of the current-to-voltage conversion circuit 206. Similarly, the outputs 216 of the sensor cells 204 are connected and provided to an input 220 of the current-to-voltage conversion circuit 206. The current-to-voltage conversion circuit 206 converts the difference of the current flowing in the input 218 and the current flowing in the input 220 to a voltage that is provided at the output 230 of the current-to-voltage conversion circuit 206. Each of the current-to-voltage conversion circuits 206 also includes an output 222 and an output 224. In a row, the output 222 of the current-to-voltage conversion circuit 206 is provided to an input 226 of each of the sensor cells 204. Similarly, the output 224 of the current-to-voltage conversion circuit 206 is provided to an input 228 of each of the sensor cells 204 of the row.” Paragraph [0028])
wherein in an integration mode, said readout circuit provides said readout signal based on a plurality of samples of said output of said transimpedance amplifier (in integration mode, the summation circuits 212 are active).
(“The optical sensor circuit 200 includes a control circuit 208 that is coupled to and provides control signals to the multiplexer 210, each of the summation circuits 212, each of the bias circuits 238 and each of the sensor cells 204. The control circuit 208 is also coupled to the optical signal source 102 to control the timing of optical signal generation. The control circuit 208 may include a state machine circuit in some implementations. The control circuit 208 controls read out of the sensor array 202. The control circuit 208 is programmable to allow the sensor cells 204 to be read in any combination and any sequence. The control circuit 208 provides control signals to the multiplexer 210 that select the routing of outputs of the summation circuits 212 to the outputs of the optical sensor circuit 200. The control circuit 208 provides control signals to the summation circuits 212 that set the summation weights applied to the voltage signals received from the current-to-voltage conversion circuits 206, and activate the summation circuits 212 needed to sum the outputs of the current-to-voltage conversion circuits 206 corresponding to incidence of laser light. The number of summation circuits 212 activated may correspond to the number of laser spots expected on the sensor array 202 at a given time. The control circuit 208 provides control signals to each of the bias circuits 238 that enable or disable bias voltage or bias current output. The control circuit 208 provides control signals to the sensor cells 204 that enable or disable the outputs of the sensor cells 204, and that enable or disable the inputs of the sensor cells 204.” Paragraph [0032])
Regarding claim 2,
The sensor circuit of claim 1, wherein:
said variable resistor comprises a plurality of serially coupled resistors (resistor 612 is comprised of multiple resistors, See Fig. 6) selectively switched between a current sense node (node connected to Iout+, Figs. 2A, 2C, 3, and 6) and an output sense node (node connected to Iout-, Figs. 2A, 2C, 3, and 6); and
said readout circuit has a first input coupled to said current sense node, and a second input coupled to said output sense node (control circuit 208 is coupled to the nodes connected to Iout+ and Iout-, Figs. 2A, 2C, 3, and 6).
Regarding claim 3,
The sensor circuit of claim 2, wherein:
said plurality of serially coupled resistors are selectively switched between said current sense node and said output sense node using a plurality of low-leakage switches (“The optical sensor cell 300 includes a photodiode 302, a preamplifier circuit 304, a global feedback network 310, a switch 312, a switch 314, a switch 316, a switch 318, a switch 320, and a switch 322” Paragraph [0033]).
Regarding claim 4,
The sensor circuit of claim 2, wherein:
in said conversion mode, said feedback network couples outputs of selected ones of said plurality of serially coupled resistors to said current sense node and said output sense node (See Paragraph [0028] as shown above); and
in said integration mode, said feedback network couples a first terminal of said capacitor to said current sense node and a second terminal of said capacitor to said output sense node (See Paragraph [0032] as shown above).
Regarding claim 7,
The sensor circuit of claim 1, wherein said readout circuit comprises at least one low-noise and low-offset stage (buffers 606 and 608 function as buffers and achieve low offset and low noise, Fig. 6).
(“The sensor array 106 includes an array of sensor cells that detect the reflected optical signals. The array of sensor cells includes a spatially distributed low-noise amplifier that increases detection sensitivity without substantially increasing circuit area. The distributed amplifier includes a first stage that is located within each sensor cell, and a second stage that spatially separated from the sensor cells.” Paragraph [0025])
Regarding claim 8,
The sensor circuit of claim 7, wherein said readout circuit comprises:
a chopper stabilized input stage (stage comprised of buffers 606 and 608, Fig. 6) for providing a voltage on first and second buffered output nodes (nodes of buffers 606 and 608, Fig. 6); and
a conversion stage (The signal processing circuitry 108 includes analog-to-digital converters, See paragraph [0028] as shown below) having inputs coupled to said first and second buffered output nodes, and an output for providing a digital readout signal.
Regarding claim 9,
The sensor circuit of claim 8, wherein said conversion stage comprises:
an analog-to-digital converter (The signal processing circuitry 108 includes analog-to-digital converters, “The signal processing circuitry 108 processes the electrical signals received from the sensor array 106 to generate a three-dimension point cloud representing the environment scanned by the optical scanning system 100. The signal processing circuitry 108 may include amplifiers, filters, analog-to-digital converters, digital processing circuitry, and other components and systems to process the signals received from the sensor array 106. In some implementations of the optical scanning system 100, the sensor array 106 and the signal processing circuitry 108 may be provided on a same integrated circuit.” Paragraph [0024]) having first and second inputs coupled to said first and second buffered output nodes, respectively, and an output; and
an accumulator stage (All the components of the accumulator stage are present in the summation circuits, See Paragraphs [0030] - [0032] as shown above) having an input coupled to said output of said analog-to-digital converter, and an output for providing said digital readout signal, wherein in said integration mode, said accumulator stage provides said readout signal based on a plurality of outputs of said analog-to-digital converter.
Regarding claim 10,
The sensor circuit of claim 1, wherein:
a said feedback network comprises a capacitor and a variable resistor (resistor 612, Fig. 6) each coupled between said output and said first input of said transimpedance amplifier, wherein said feedback network forms an output signal on a current sense node (node connected to Iout+, Figs. 2A, 2C, 3, and 6) and an output sense node (node connected to Iout-, Figs. 2A, 2C, 3, and 6); and
said readout circuit is coupled to said current sense node and said output sense node
Regarding claim 11,
The sensor circuit of claim 10, wherein said readout circuit uses chopper stabilization to provide said readout signal. (the chopper stabilization stage is comprised of buffers 606 and 608, Fig. 6).
Regarding independent claim 18, Seyed Aliroteh teaches,
A method of reading out a condition of a sensor (See Fig. 2C for block diagram of sensor, 3 for schematic diagram of sensor, and 6 for schematic diagram of circuit), comprising:
converting a current conducted by the sensor into a voltage using a transimpedance amplifier (amplifier 602, Fig. 6) having a first input adapted to be coupled to the sensor;
forming a voltage using a feedback network (Feedback network 308, Fig. 3) comprising a capacitor and a resistor (capacitor 504, Fig. 5 and resistor 612, Fig. 6. See Paragraph [0034] as shown above) each coupled between an output and said first input of said transimpedance amplifier (both capacitor and resistor are coupled between the input and output of the amplifier);
in a conversion mode (See Paragraph [0028] as shown above), measuring a voltage across said resistor and providing a readout signal (See Paragraphs [0040] – [0041] as shown above) based on one sample of said voltage across said resistor; and
in an integration mode (See Paragraph [0032] as shown above), measuring a voltage across said capacitor and providing said readout signal based on a plurality of samples of said voltage across said capacitor.
Regarding claim 19,
The method of claim 18, wherein said resistor comprises a variable resistor (See Paragraph [0034] as shown above) and said forming said voltage comprises:
varying a resistance (See Paragraph [0034] as shown above) of said variable resistor based on a desired current range of the sensor.
Regarding claim 20,
The method of claim 19, wherein varying said resistance of said variable resistor comprises:
selectively coupling an external resistor (See Paragraph [0034] as shown above) between said output and said first input of said transimpedance amplifier.
Regarding claim 21,
The method of claim 18, wherein providing said readout signal comprises:
converting a selected one of said voltage across said resistor and said voltage across said capacitor into a digital signal, thereby forming a digital readout signal (See Paragraph [0032] as shown above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 are rejected under 35 U.S.C. 103 as being unpatentable over Seyed Aliroteh in view of Fisher et al. (US 20230188100 A1), hereinafter Fisher.
Regarding claim 5, Seyed Aliroteh is silent regarding,
The sensor circuit of claim 2, wherein said feedback network is implemented on a monolithic integrated circuit, and said monolithic integrated circuit further comprises:
a first integrated circuit terminal coupled to said current sense node; and
a second integrated circuit terminal coupled to said output sense node, wherein:
in an internal resistance mode, said feedback network couples said variable resistor between said current sense node and said output sense node and decouples said first integrated circuit terminal from said current sense node and said second integrated circuit terminal from said output sense node; and
in an external resistance mode, said feedback network couples said first integrated circuit terminal to said current sense node and said second integrated circuit terminal to said output sense node and decouples said variable resistor from said current sense node and said output sense node.
Fisher discloses,
The sensor circuit of claim 2, wherein said feedback network is implemented on a monolithic integrated circuit (See Fig. 8A, and “The gate bus 612 and the gate fingers 622 may be implemented as a first monolithic metal pattern.” Paragraph [0092]), and said monolithic integrated circuit further comprises:
a first integrated circuit terminal coupled to said current sense node (terminal 612, Fig. 8A); and
a second integrated circuit terminal coupled to said output sense node (terminal 614, Fig. 8A), wherein:
in an internal resistance mode (The resistors can be modified to reach an internal resistance mode, See Paragraphs [0059] – [0061] as shown below), said feedback network couples said variable resistor between said current sense node and said output sense node and decouples said first integrated circuit terminal from said current sense node and said second integrated circuit terminal from said output sense node; and
in an external resistance mode (The resistors can be modified to reach an external resistance mode, See Paragraphs [0059] – [0061] as shown below),, said feedback network couples said first integrated circuit terminal to said current sense node and said second integrated circuit terminal to said output sense node and decouples said variable resistor from said current sense node and said output sense node.
(“FIG. 2 is a circuit diagram of one example implementation of the RF transistor amplifier circuit 100 of FIG. 1. As shown in FIG. 2, the first Group III nitride based depletion mode high electron mobility transistor 112 of the self-bias circuit 110 includes a gate terminal G1 that is coupled to a reference voltage (e.g., a ground voltage), a drain terminal D1 that is coupled to a direct current voltage source VDD, and a source terminal S1 that is coupled to the current setting circuit 114. A gate resistor Rg is coupled between the gate G1 of the first Group III nitride based depletion mode high electron mobility transistor 112 and electrical ground, and a drain resistor Rd is provided between the drain D1 of the first Group III nitride based depletion mode high electron mobility transistor 112 and the power supply voltage VDD. The resistors Rg, Rd can reduce or prevent oscillations in the first Group III nitride based depletion mode high electron mobility transistor 112. The current setting circuit 114 is shown as being implemented as a resistor Rs that is coupled to a reference voltage (e.g., electrical ground. While the current setting circuit 114 is typically implemented on the semiconductor die 101 to reduce the overall size of the RF transistor amplifier circuit 100, it will be appreciated that in some embodiments the current setting circuit 114 may be implemented off of the semiconductor die 101 (e.g., on a customer printed circuit board) and may be electrically connected to the first Group III nitride based depletion mode high electron mobility transistor 112 by a bond wire or other electrical connection.
The inverting circuit 120 is embodied as a differential amplifier 122, such as an operational amplifier. The differential amplifier includes an inverting input 124 (denoted by a “−” sign in FIG. 2), a non-inverting input 126 (denoted by a “+” sign in FIG. 2), and an output 128. The non-inverting input 126 is connected to a reference voltage, such as electrical ground. The inverting input 124 is connected to the output 116 of the self-bias circuit 110 (which corresponds to the node that connects the source S1 of the first Group III nitride based depletion mode high electron mobility transistor 112 to the current setting circuit 114). First and second resistors R1 and R2 are provided to set the amplification factor of the differential amplifier 122. In some embodiments, the resistance value of R1 may be equal to the resistance value of R2, which sets the inverting differential amplifier 122 to have unity gain.
The output 128 of inverting circuit 120 is connected to the gate terminal 132 (G2) of the RF transistor amplifier 130, which is implemented as a second Group III nitride based depletion mode high electron mobility transistor 134. The RF input (RF IN) for the RF transistor amplifier 130 is also coupled to the gate terminal 132 (G2) of the RF transistor amplifier 130. A first DC blocking capacitor C1 is coupled between the RF input RF IN and the gate terminal 132 of RF transistor amplifier 130 in order to isolate the RF input from the DC gate bias voltage output from the differential amplifier 122. An inductor L1 and/or a resistor R3 are provided between the output 128 of the inverting circuit 120 and the RF input RF IN that form a gate choke that isolates differential amplifier 122 from the RF swing of the RF signals input at the RF input RF IN. The gate choke can be all inductive, all resistive or a combination of inductance and resistance. In other embodiments, a shunt capacitor to electrical ground may be used in place of inductor L1 and resistor R3 to form the gate choke. The drain D2 of the second Group III nitride based depletion mode high electron mobility transistor 134 acts as the RF output for RF transistor amplifier circuit 100. A second DC blocking capacitor C2 is coupled between the RF output RF OUT and the RF transistor amplifier 130. An output choke L2 is also provided that isolates the power supply voltage VDD from the RF output signals. In FIG. 2, all of the illustrated components may be implemented in the common semiconductor die 101.” Paragraphs [0059] – [0061])
Seyed Aliroteh and Fisher are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a monolithic integrated circuit in Seyed Aliroteh’s design in order to modify and adjust the coupling of resistors to reach either internal or external resistance in accordance with Fisher’s design.
Claims 6, and 12 - 16 are rejected under 35 U.S.C. 103 as being unpatentable over Seyed Aliroteh in view of Odabaee et al. (US 20210358895 A1), hereinafter Odabaee.
Regarding claim 6, Seyed Aliroteh is silent regarding;
The sensor circuit of claim 2, wherein:
said plurality of serially coupled resistors comprise silicon-chromium (SiCr) resistors.
Odabaee discloses,
The sensor circuit of claim 2, wherein:
said plurality of serially coupled resistors comprise silicon-chromium (SiCr) resistors.
(“The substrates for integrated-passive devices may be thin-film substrates such as silicon, alumina, or glass. For example, the integrated-passive resistors may be manufactured from high-accuracy thin-film silicon chromium (SiCr). The integrated-passive capacitors may be manufactured as metal-insulator-metal (MIM) capacitors.” Paragraph [0033])
Seyed Aliroteh and Odabaee are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include silicon-chromium (SiCr) resistors in Seyed Aliroteh’s design in order to provide low conversion temperature drift in accordance with Odabaee’s design.
Regarding claim 12, Seyed Aliroteh discloses;
The sensor circuit of claim 11, wherein said readout circuit comprises:
a system chopping circuit (the chopper stabilization stage is comprised of buffers 606 and 608, Fig. 6) having a first input coupled to said output sense node, a second input coupled to said current sense node (each buffer is coupled to each node respectively), a clock input for receiving a system chop clock signal, and first and second outputs;
a first buffer (buffer 606, Fig. 6) having an input coupled to said first output of said system chopping circuit,
and an output;
a second buffer (buffer 608, Fig. 6) having an input coupled to said second output of said system chopping circuit, and an output; and
a conversion stage (See paragraph [0028] as shown above) having inputs coupled to said output of said first buffer and said output of said second buffer, respectively, and an output for providing a digital readout signal.
Seyed Aliroteh is silent regarding;
a clock input for receiving a system chop clock signal, and first and second outputs;
Odabaee discloses,
a clock input for receiving a system chop clock signal (“The control circuitry logically combines this signal with a clock signal received by the control circuitry to turn the common loop switch 132A ON or OFF and to control companion switches 132B and 132C.” Paragraph [0042]), and first and second outputs;
Seyed Aliroteh and Odabaee are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a clock signal in Seyed Aliroteh’s design in order to have the peak current regulated to maintain a regulated output voltage at each channel in accordance with Odabaee’s design.
Regarding claim 13, Seyed Aliroteh discloses;
The sensor circuit of claim 12, wherein:
said first input of said system chopping circuit is coupled to said output sense node through a first lowpass filter (The signal processing circuitry 108 includes filters, See paragraph [0024] as shown above); and
said second input of said system chopping circuit is coupled to said current sense node through a second lowpass filter (The signal processing circuitry 108 includes filters, See paragraph [0024] as shown above).
Regarding claim 14, Seyed Aliroteh discloses;
The sensor circuit of claim 12, wherein said conversion stage comprises:
an analog-to-digital converter (The signal processing circuitry 108 includes analog-to-digital converters, See paragraph [0024] as shown above) having first and second inputs coupled to said output of said first buffer and said output of said second buffer, respectively. and an output;
and an accumulator stage (All the components of the accumulator stage are present in the summation circuits, See Paragraphs [0030] - [0032] as shown above) having an input coupled to said output of said analog-to-digital converter, and an output for providing said digital readout signal.
Regarding claim 15, Seyed Aliroteh discloses;
The sensor circuit of claim 14, wherein:
in a conversion mode (See Paragraphs [0028] – [0032] as shown above), said accumulator stage provides said digital readout signal in response to one sample of said output of said analog-to-digital converter; and
in an integration mode (See Paragraphs [0028] – [0032] as shown above), said accumulator stage provides said digital readout signal in response to a plurality of samples of said output of said analog-to-digital converter.
Regarding claim 16, Seyed Aliroteh discloses;
The sensor circuit of claim 15, wherein in said integration mode, said analog-to-digital converter monitors each of said plurality of samples of said output of said first buffer and said second buffer, and detects a saturation condition in response to an output of at least one of said first buffer and said second buffer exceeding a threshold (See Paragraph [0032] as shown above).
Claim 17 are rejected under 35 U.S.C. 103 as being unpatentable over Seyed Aliroteh in view of Lyden et al. (US 20160112037 A1), hereinafter Lyden.
Regarding claim 17, Seyed Aliroteh is silent regarding;
The sensor circuit of claim 10, further comprising:
a calibration circuit coupled to said first input of said transimpedance amplifier, for measuring leakage current at said first input of said transimpedance amplifier.
Lyden discloses;
The sensor circuit of claim 10, further comprising:
a calibration circuit (See Fig. 1) coupled to said first input of said transimpedance amplifier, for measuring leakage current at said first input of said transimpedance amplifier.
(“The voltage reference 52 may be arranged to generate a DC voltage pulse, in which case it is desirable to measure the evolution of current with respect to time. However, for checking and calibration purposes it may also be desirable for the voltage reference 52 to generate a changing signal, for example an alternating sinusoid, and in which case it becomes desirable for the measurement circuit 8 to have knowledge of the phase of the sinusoidal signal such that a magnitude and phase change of the current flow may be measured, for example to deduce a complex impedance of the cell 10. The complex impedance may be determined by comparing the magnitude and phase of the voltage difference between the first and second measurement terminals with the magnitude and phase of current flow through the sensor.” Paragraph [0029]).
Seyed Aliroteh and Lyden are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a calibration circuit in Seyed Aliroteh’s design in order to measure the magnitude and phase change of the current flow in accordance with Lyden’s design.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE E PINERO whose telephone number is (703)756-4746. The examiner can normally be reached M-F 8:00 AM - 5:00 PM (ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSE E PINERO/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843