DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on April 13, 2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15 and 21-26 have been considered but are moot on grounds of new rejection and interpretation of newly found prior art. Notice of allowability has been withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-15 and 21-26 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Elsherbini et al. (Elsherbini) (US 2023/0187362 A1).
The applied reference has common inventor(s) and assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In regards to claims 1-15 and 21-26, Elsherbini (Figs. 1A-4 and associated text) discloses the Applicant’s claimed invention.
Claim(s) 1-7 and 22-26 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Elsherbini et al. (Elsherbini’977) (US 2019/0385977 A1).
In regards to claim 1, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses a microelectronic assembly (item 100), comprising: a plurality of layers (items 104-1, 104-2, 104-3, 104-4, 104-5 or 104-6) of IC dies (items 114-1, 114-2, 114-3, 114-4, 114-5, 114-7, 114-8, 114-9) in a dielectric material (item 104), adjacent layers in the plurality of layers (items 104-1, 104-2, 104-3, 104-4, 104-5, 104-6) being coupled together by first interconnects (item 130, 150 or 155) having a pitch of less than 10 micrometers between adjacent first interconnects (paragraph 180); a package substrate (item 102) coupled to a first side of the plurality of layers (items 104-1, 104-2, 104-3, 104-4, or 104-5) by second interconnects; a structure (item 104-6) coupled to a second side of the plurality of layers (items 104-1, 104-2, 104-3, 104-4 or 104-5) by third interconnects (item 130, 150 or 155), the second side being opposite to the first side; and capacitors (paragraph 46) in at least the plurality of layers (item 140) or the structure. Examiner notes that “a structure” (very broad) could be anything such as another layer of die which is still considered “a structure”.
In regards to claim 2, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein any of the capacitors (paragraph 46) is at least in: one of the plurality of layers (item 140), proximate to an adjacent layer in the plurality of layers, the structure, proximate to the plurality of layers, on the first side of the plurality of layers, or on the second side of the plurality of layers.
In regards to claim 3, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein any one of the capacitors (paragraph 46) comprises: a first conductive structure conductively coupled to a first conductive trace, a second conductive structure conductively coupled to a second conductive trace, and another dielectric material between the first conductive structure and the second conductive structure.
In regards to claim 4, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein: the first conductive trace is in one layer of the plurality of layers, the second conductive trace is in another layer of the plurality of layers or the support structure, and the one layer is adjacent to the another layer or the structure.
In regards to claim 5, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein the first conductive trace and the second conductive trace are in at least one of: one layer of the plurality of layers (item 140), or the structure.
In regards to claim 6, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein the another dielectric material is selected from: a compound comprising oxygen and at least one of hafnium and titanium (paragraph 85).
In regards to claim 7, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein any of the capacitors (paragraph 46) is in at least one of: the dielectric material around the IC dies, one or more IC dies, or the structure.
In regards to claim 22, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses a microelectronic assembly, comprising: a plurality of layers (item 104, multi-layer die assembly) comprising a first layer (items 104-1, 104-2, 104-3, 104-4, 104-5) and a second layer (items 104-2, 104-3, 104-4, 104-5 or 104-6), wherein the first layer (items 104-1, 104-2, 104-3, 104-4 or 104-5) includes a first integrated circuit (IC) die (items 114-1, 114-2, 114-3, 114-4, 114-5, 114-10, 114-14, 114-15, 114-16, 114-17, 114-18, 114-19, 114-20, 114-21, 114-22), the second layer (items 104-2, 104-3, 104-4, 104-5 or 104-6) includes a second IC die (items 114-2, 114-3, 114-5, 114-10, 114-14, 114-15, 114-16, 114-17, 114-18, 114-19, 114-20, 114-21, 114-22, 114-23, 114-24, 114-25), and the first die (items 114-1, 114-2, 114-3, 114-4, 114-5, 114-10, 114-14, 114-15, 114-16, 114-17, 114-18, 114-19, 114-20, 114-21, 114-22) is coupled with the second die (items 114-2, 114-3, 114-5, 114-10, 114-14, 114-15, 114-16, 114-17, 114-18, 114-19, 114-20, 114-21, 114-22, 114-23, 114-24, 114-25) by first interconnects (items 130-1, 150-1 or 155-1); a first IC component (item 114-7, 114-8, 114-9, 114-11, 114-12, 114-13, 114-21, 114-22, 114-23, 114-24, 114-25) coupled with a first side of the plurality of layers (item 104, multi-layer die assembly) by second interconnects (items 130-1, 150-1 or 155-1); a second IC component (item 114-7, 114-8, 114-9, 114-11, 114-12, 114-13, 114-21, 114-22, 114-23, 114-24, 114-25) coupled with a second side of the plurality of layers (item 104, multi-layer die assembly) by third interconnects (items 130-1, 150-1 or 155-1); and a capacitor (paragraph 46) in at least one of the plurality of layers (item 104) or in the second IC component (item 114-7, 114-8, 114-9, 114-11, 114-12, 114-13, 114-21, 114-22, 114-23, 114-24, 114-25).
In regards to claim 23, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein the first interconnects have a pitch of less than 10 micrometers between adjacent first interconnects (paragraph 180).
In regards to claim 24, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein the second interconnects have a pitch greater than 10 micrometers between adjacent second interconnects (paragraph 142).
In regards to claim 25, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein the third interconnects have a pitch of less than 10 micrometers between adjacent third interconnects (paragraph 143).
In regards to claim 26, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein: the first interconnects have a pitch of less than 10 micrometers between adjacent first interconnects (paragraph 180), the second interconnects have a pitch greater than 10 micrometers between adjacent second interconnects (paragraph 142), and the third interconnects have a pitch of less than 10 micrometers between adjacent third interconnects (paragraph 143).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini et al. (Elsherbini’977) (US 2019/0385977 A1) in view of NAH (KR 20180112394 A).
In regards to claim 1, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses a microelectronic assembly (item 100), comprising: a plurality of layers (items 104-1, 104-2, 104-3, 104-4, 104-5 or 104-6) of IC dies (items 114-1, 114-2, 114-3, 114-4, 114-5, 114-7, 114-8, 114-9) in a dielectric material (item 104), adjacent layers in the plurality of layers (items 104-1, 104-2, 104-3, 104-4, 104-5, 104-6) being coupled together by first interconnects (item 130, 150 or 155) having a pitch of less than 10 micrometers between adjacent first interconnects (paragraph 180); a package substrate (item 102) coupled to a first side of the plurality of layers (items 104-1, 104-2, 104-3, 104-4, or 104-5) by second interconnects; a structure (item 104-6) coupled to a second side of the plurality of layers (items 104-1, 104-2, 104-3, 104-4 or 104-5) by third interconnects (item 130, 150 or 155), the second side being opposite to the first side; and capacitors (paragraph 46) in at least the plurality of layers (item 140) or the structure. Examiner notes that “a structure” (very broad) could be anything such as another layer of die which is still considered “a structure”.
Elbershini does not specifically disclose a structure coupled to the second side of the plurality of layers by third interconnects.
Nah discloses a structure (item 100D, 100G) coupled to the second side of the plurality of layers (layers of item 200) by third interconnects (item 230).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Nah for the purpose of protection and device/package height.
In regards to claim 2, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein any of the capacitors (paragraph 46) is at least in: one of the plurality of layers (item 140), proximate to an adjacent layer in the plurality of layers, the structure, proximate to the plurality of layers, on the first side of the plurality of layers, or on the second side of the plurality of layers.
In regards to claim 3, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein any one of the capacitors (paragraph 46) comprises: a first conductive structure conductively coupled to a first conductive trace, a second conductive structure conductively coupled to a second conductive trace, and another dielectric material between the first conductive structure and the second conductive structure.
In regards to claim 4, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein: the first conductive trace is in one layer of the plurality of layers, the second conductive trace is in another layer of the plurality of layers or the support structure, and the one layer is adjacent to the another layer or the structure.
In regards to claim 5, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein the first conductive trace and the second conductive trace are in at least one of: one layer of the plurality of layers (item 140), or the structure.
In regards to claim 6, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein the another dielectric material is selected from: a compound comprising oxygen and at least one of hafnium and titanium (paragraph 85).
In regards to claim 7, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein any of the capacitors (paragraph 46) is in at least one of: the dielectric material around the IC dies, one or more IC dies, or the structure.
In regards to claim 8, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) as modified by Nah does not specifically discloses wherein: the first interconnects comprise hybrid bonds having metal-metal bonds and dielectric-dielectric bonds, and the third interconnects comprise at least one of: hybrid bonds having metal-metal bonds and dielectric-dielectric bonds, or dielectric-dielectric bonds. Examiner notes that hybrid bonding/hybrid bonds are well known in the art and would have been obvious to one or ordinary skill in the art before the effective filing date for the purpose of the a reliable electrical and/or mechanical bond.
In regards to claim 9, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses an IC package (item 100), comprising: a first layer of IC dies (items 104-1, 104-2, 104-3, 104-4 or 104-5 plus 114) in a dielectric material (item 104); a second layer of IC dies (items 104-2, 104-3, 104-4, 104-5 or 104-6 plus 114) in the dielectric material (item 104, paragraph 42); a package substrate (item 102) coupled to the first layer dies (items 104-1, 104-2, 104-3, 104-4 or 104-5); and capacitors (paragraph 46) in at least the first layer (items 104-1, 104-2, 104-3, 104-4 or 104-5), the second layer (items 104-2, 104-3, 104-4, 104-5 or 104-6), or the support, wherein: the first layer (items 104-1, 104-2, 104-3, 104-4 or 104-5) and the second layer (items 104-2, 104-3, 104-4, 104-5 or 104-6) are coupled by first-level interconnects (FLIs) having a first pitch (items 130, 150 or 155), the package substrate (item 102) is coupled to the first layer (items 104-1, 104-2, 104-3, 104-4 or 104-5) by second-level interconnects (SLI) pitch (items 130, 150 or 155) having a second pitch greater than the first pitch (paragraphs 180, 142, 143), but does not specifically disclose a support coupled to the second layer, and the support is coupled to the second layer by other FLIs having a third pitch smaller than the second pitch.
Nah discloses a support (item 100D, 100G) coupled to the second layer (layers of item 200) by third interconnects (item 230).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Nah for the purpose of protection and device/package height.
Elbershini as modified by Nah does not specifically disclose the support is coupled to the second layer by other FLIs having a third pitch smaller than the second pitch.
However Elbershini already discloses that interconnects can have various ranges of pitch (paragraphs 180, 142, 143).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include FLIs having a third pitch smaller than the second pitch, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
It would have been obvious to modify the invention to include FLIs having a third pitch smaller than the second pitch, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 10, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein the capacitors (paragraph 46) are proximate to at least one of: the package substrate (item 102) in the first layer, the support structure in the second layer, or an interface between the first layer and the second layer.
In regards to claim 11, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein: the capacitors comprise a first conductive structure, a second conductive structure, and a capacitor-dielectric material between the first conductive structure and the second conductive structure, the first conductive structure is to be coupled to a power source, and the second conductive structure is to be coupled to a ground connection.
In regards to claim 12, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein the first conductive structure and the second conductive structure comprise respective pluralities of fingers separated by the capacitor- dielectric material.
In regards to claim 13, Elsherbini’977 (Figs. 3, 5, 7 and associated text and items) discloses wherein the first conductive structure and the second conductive structure comprise at least one of planar plates or corrugated plates.
In regards to claim 14, Elsherbini’977 (paragraphs 38, 42, Figs. 3, 5, 6A-6F, 7 and associated text and items) discloses wherein: the first conductive structure and the second conductive structure comprise concentric cylindrical vias, and an individual concentric cylindrical via of the concentric cylindrical vias around a through via in at least one IC die of the IC dies of at least the first layer or the second layer, or a through via in the dielectric material of at least the first layer or the second layer.
In regards to claim 15, Elsherbini’977 (paragraphs 38, 42, Figs. 3, 5, 6, 7 and associated text and items) discloses wherein: the first conductive structure and the second conductive structure comprise deep trench vias, and the deep trench vias are in at least one of: respective substrates of the IC dies in at least the first layer or the second layer, the dielectric material of at least the first layer or the second layer, or the support structure.
In regards to claim 21, Elsherbini’977 (paragraphs 38, 42, Figs. 3, 5, 6, 7 and associated text and items) discloses wherein the first pitch or the third pitch is less than 10 micrometers (paragraphs 142, 143, 180).
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 May 9, 2026
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