Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 3-8, 14, 17 and 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species. Applicant timely traversed the election requirement in the reply filed on 12/16/2025. The traversal is on the grounds that Applicant disagrees with Examiner’s characterization of the species of Group A, stating that Examiner’s characterization is unduly narrow and does not reflect the species as disclosed in the application. Examiner finds Applicant’s arguments persuasive and the requirement that group A1 contains only three layers is with withdrawn, as is the election of group B. Examiner understands the elected species to be the embodiment shown in Applicant’s Fig. 1B but without a requirement that the device comprise only three layers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini (US 20200227401 A1) in view of Lin (US 20230326889 A1).
Regarding claim 1, Elsherbini discloses a microelectronic assembly (Fig. 7), comprising: a plurality of layers of monolithic wafers and disaggregated integrated circuit dies (Fig. 7, first layer comprising 114-1 and the surrounding mold material 127, a second layer comprising 114-3 and 114-6 and the surrounding mold material 127, and a third layer comprising 114-4 and 114-7 and 114-8 and the surrounding mold material 127; para. 27 "FIG. 1 illustrates a number of elements that are omitted from subsequent drawings for ease of illustration, but may be included in any of the microelectronic assemblies 100 disclosed herein. Examples of such elements include... the mold material 127, the second-level interconnects 137, and/or the circuit board 133"), adjacent layers being coupled together by first interconnects (130-1, 130-2, 130-3, 130-4) having a pitch less than 10 micrometers between adjacent first interconnects (Para. 50 "interconnects 130 disclosed herein may have a pitch between 7 microns and 100 microns"), the disaggregated IC dies arranged with portions of the monolithic wafers into modular sub-assemblies (114-1 in combination with the surrounding layers; 114-3 and 114-6 in combination with the surrounding layers; and 114-4, 114-7, 114-8 in combination with the surrounding layers); and a package substrate (102) coupled to the modular sub-assemblies by second interconnects (150-1, 150-2, 150-3) having a pitch greater than 10 micrometers between adjacent second interconnects (Para. 50 "interconnects 150 disclosed herein may have a pitch between 80 microns and 300 microns"), wherein: each layer comprises either the monolithic wafer or the disaggregated IC dies (Fig. 7 shows first layer comprising at least 114-1, second layer comprising at least 114-3 and 114-6, and third layer comprising at least 114-4, 114-7, and 114-8), the disaggregated IC dies are surrounded laterally by a dielectric material (127; para. 43 "the mold material 127 may be an insulating material"; para. 27 "FIG. 1 illustrates a number of elements that are omitted from subsequent drawings for ease of illustration, but may be included in any of the microelectronic assemblies 100 disclosed herein. Examples of such elements include... the mold material 127, the second-level interconnects 137, and/or the circuit board 133"). However, Elsherbini does not explicitly disclose and the disaggregated IC dies are arranged with portions of the monolithic wafers such that a voltage regulator circuit in a first layer of the plurality of layers, a compute circuit in a second layer of the plurality of layers, and a memory circuit in a third layer of the plurality of layers are conductively coupled together at least in an intra-modular power delivery circuitry.
On the other hand, Lin discloses and the disaggregated IC dies are arranged with portions of the monolithic wafers such that a voltage regulator circuit (Fig. 1A, para. 22 "the carrier 10 includes an integrated component including a power regulating component…. The power regulating component may include a voltage regulating element") in a first layer (10) of the plurality of layers, a compute circuit (para. 27 "the processing component 20 may include, for example, a central processing unit") in a second layer (20) of the plurality of layers, and a memory circuit in a third layer (memory unit 30) of the plurality of layers are conductively coupled together at least in an intra-modular power delivery circuitry. It would have been obvious to one of ordinary skill in the art before the time of the effective filing of the invention to modify Elsherbini according to the teachings of Lin such that the device would include a voltage regulator circuit in the first layer, a compute circuit in the second layer, and a memory circuit in the third layer, and that the plurality of layers would be conductively coupled together at least in an intra-modular power delivery circuitry, in order to provide a system consisting of power, computation and memory units capable of sharing power with one another, as is common in the art.[RefA][RefA]
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini (US 20200227401 A1) in view of Lin (US 20230326889 A1) as applied to claim 1 above, and further in view of Yu (US 20180158749 A1).
Regarding claim 9, Elsherbini discloses a microelectronic structure (Fig. 7), comprising: a disaggregated IC die (114-6) having a first side (upper surface) and an opposing second side (second surface); a portion (upper portion of the monolithic wafer formed by 114-1 and the surrounding mold material 127; para. 27 "FIG. 1 illustrates a number of elements that are omitted from subsequent drawings for ease of illustration, but may be included in any of the microelectronic assemblies 100 disclosed herein. Examples of such elements include... the mold material 127, the second-level interconnects 137, and/or the circuit board 133") of a first monolithic wafer (114-1 and surrounding molding layer) coupled to the first side of the disaggregated IC die by interconnects (130-1) having a pitch of less than 10 micrometers between adjacent interconnects (Para. 50 "interconnects 130 disclosed herein may have a pitch between 7 microns and 100 microns"); and a portion (lower portion of the monolithic wafer formed by 114-6 and the surrounding mold material 127; para. 27 "FIG. 1 illustrates a number of elements that are omitted from subsequent drawings for ease of illustration, but may be included in any of the microelectronic assemblies 100 disclosed herein. Examples of such elements include... the mold material 127, the second-level interconnects 137, and/or the circuit board 133") of a second monolithic wafer (114-7 and surrounding molding layer) coupled to the second side of the disaggregated IC die by interconnects (130-3) having another pitch of less than 10 micrometers between adjacent interconnects (Para. 50 "interconnects 130 disclosed herein may have a pitch between 7 microns and 100 microns"), wherein: the disaggregated IC die is surrounded by a dielectric material (Para. 43 "The mold material 127 may be an insulating material, such as an appropriate epoxy material"), and the microelectronic structure is part of a larger microelectronic device comprising the first monolithic wafer and the second monolithic wafer (Shown in fig. 7 and further in figs. 12-16). However, Elsherbini does not explicitly disclose wherein the dielectric material is specifically an inorganic dielectric material.
On the other hand, Yu discloses wherein the dielectric material is specifically an inorganic dielectric material (Fig. 5, 216; para. 44 "216 may comprise a molding compound such as an epoxy…. In some embodiments, the gap-fill material 216 may comprise... Silicon dioxide, silicon nitride, or the like"; silicon oxide and silicon nitride are both known to be inorganic dielectric materials). It would have been obvious to one of ordinary skill in the art before the time of the effective filing of the invention to modify Elsherbini according to the teachings of Yu such that the epoxy dielectric of Elsherbini would be interchanged for SiO or SiN, in order to take advantage of the high temperature tolerance of SiO or SiN in order to protect components during operation or manufacturing.[RefA][RefA]
Elsherbini in view of Yu still does not disclose the disaggregated IC die comprising a compute circuit, the portion of the first monolithic wafer comprising a voltage regulator circuit, and the portion of the second monolithic wafer comprising a memory circuit. However, Lin discloses the disaggregated IC die comprising a compute circuit (Fig. 1A, layer 20; para. 27 "the processing component 20 may include, for example, a central processing unit"), the portion of the first monolithic wafer comprising a voltage regulator circuit (Layer 10; para. 22 "the carrier 10 includes an integrated component including a power regulating component…. The power regulating component may include a voltage regulating element"), the portion of the second monolithic wafer comprising a memory circuit (memory unit 30). It would have been obvious to one of ordinary skill in the art before the time of the effective filing of the invention to modify Elsherbini in view of Yu according to the teachings of Lin such that the device would include a voltage regulator circuit in the first layer, a compute circuit in the second layer, and a memory circuit in the third layer, and that the plurality of layers would be conductively coupled together at least in an intra-modular power delivery circuitry, in order to provide a system consisting of power, computation and memory units capable of sharing power with one another, as is common in the art.
Regarding claim 10, Elsherbini discloses wherein a power delivery circuit in the microelectronic structure comprises the voltage regulator circuit, the compute circuit and the memory circuit (Fig. 7 shows the different layers providing each other power).
Regarding claim 11, Elsherbini discloses wherein: the disaggregated IC die is coupled back-to back with the portion of the first monolithic wafer (Fig. 7 shows a back side of 114-6 connecting to a back side of 114-1), and the disaggregated IC die is coupled front-to-front with the portion of the second monolithic wafer.
Allowable Subject Matter
Claims 2, 12, 13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art of record does not disclose wherein a conductive pathway between laterally adjacent modular sub-assemblies comprises conductive traces in one layer farthest from the package substrate.
Regarding claim 12, the prior art of record does not disclose wherein TDVs are present in the inorganic dielectric material around the disaggregated IC die, the first monolithic wafer comprises TSVs, and the memory circuit in the portion of the second monolithic wafer is conductively coupled to the voltage regulator circuit in the portion of the first monolithic wafer through at least one of the TDVs in the inorganic dielectric material around the disaggregated IC die and at least one of the TSVs in the first monolithic wafer.
For this reason, claim 13 is also objected to as a dependent of a rejected base claim.
Regarding claim 15, the prior art of record does not disclose wherein: the voltage regulator circuit comprises: a first voltage rail configured to provide current at a first voltage; and a second voltage rail configured to provide current at a second voltage, the memory circuit is conductively coupled to the first voltage rail, and the compute circuit is conductively coupled to the second voltage rail.
Claims 16, 19 and 20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 16, the prior art of record does not disclose A method for fabricating a microelectronic assembly, the method comprising: providing a first wafer comprising IC dies; coupling a second wafer to the first wafer by forming metal-metal bonds and dielectric-dielectric bonds having a pitch of less than 10 micrometers between adjacent metal-metal bonds, the first wafer comprising IC dies; and coupling a third wafer to the second wafer on a side of the second wafer opposite to the first wafer, the coupling comprising forming metal-metal bonds and dielectric-dielectric bonds having a pitch of less than 10 micrometers between adjacent metal-metal bonds, the third wafer comprising IC dies, wherein: at least one of the first wafer, the second wafer or the third wafer is a reconstituted wafer having disaggregated IC dies surrounded by a dielectric material, at least another of the first wafer, the second wafer or the third wafer is a monolithic wafer, and the first wafer comprises voltage regulator circuits, the second wafer comprises at least one of compute circuits and memory circuits and the third wafer comprises at least the other of compute circuits and memory circuits.
For this reason, claims 19 and 20 are also allowable as dependents of claim 16.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST.
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/S.J.S./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817