DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 02/27/2026 has been entered.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 02/27/2026, have been fully considered, the Applicant’s amendment in relation to “…the second and third dies are electrically coupled to the first die face-to-face by interconnects…”, are considered but it does not overcome the new ground of rejections with a reference of the record, US 20200118973 A1 to Wang.
Chen does not expressly disclose “wherein the second and third dies are electrically coupled to the first die face-to-face by interconnects…”. However, Wang discloses the second (126, Figs. 1-7, 1-14) and third (127, Figs. 1-7, 1-14) dies electrically coupled to the first die (103, Figs. 1-7, 1-14) face-to-face (Figs. 1-7, 1-14) by interconnects (116, Figs. 1-3, 1-14), being used in the current rejection, see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8-9 and 13 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210082855 A1, of the record) in view of Wang et al. (US 20200118973 A1, hereinafter Wang, of the record) and further in view of Khanna et al. (US 20070086168 A1, hereinafter Khanna, of the record).
Re: Independent Claim 1, Chen discloses a microelectronic assembly (500 chip package structure in [0075], Fig. 3), comprising:
PNG
media_image1.png
572
922
media_image1.png
Greyscale
a dielectric layer (512 dielectric layer in [0077], Fig. 3) having one or more metal traces (514 wiring layers in [0077], Fig. 3), the dielectric layer (512) having a surface (512-surface2, Fig. 3-Annotated);
Chen’s Figure 3-Annotated.
a microelectronic subassembly (170,130,160,180 chip structure 170, chip structures 130, conductive via structures 160 and insulating material 180 in [0033,0052], Fig. 3) on the surface (512-surface2) of the dielectric layer (512), the microelectronic subassembly including:
a first die (170 in [0052], Fig. 3) and a through-dielectric via (TDV) (160 in [0052], Fig. 3) surrounded by a dielectric material (180 suitable insulating material in [0033], Fig. 2), wherein the first die (170) is at the surface of the dielectric layer (512);
a second die (130-L in [0052], Fig. 3-Annotated) and a third die (130-R in [0052], Fig. 3-Annotated) on the first die (170), wherein the second (130-L) and third (130-R) dies are electrically coupled to the first die (170) by interconnects (410 redistribution layers in [0079], Fig. 3), and wherein the TDV (160) is electrically coupled at a first end to the dielectric layer (512) and electrically coupled at an opposing second end to the second die (130-L); and
an insulating material (240 molding layer in [0063], Fig. 3) on the surface of the dielectric layer (512) and around the microelectronic subassembly (170,130,160,180).
Chen does not expressly disclose wherein the second (130-L) and third (130-R) dies are electrically coupled to the first die face-to-face by interconnects having a pitch of less than 10 microns between adjacent interconnects and a substrate on and coupled to the second and third dies.
PNG
media_image2.png
208
260
media_image2.png
Greyscale
Wang’s Figure 1-14-Annotated.
However, in the same semiconductor device field of endeavor, Wang discloses the second (126, [0035], Figs. 1-7, 1-14) and third (127, [0035], Figs. 1-7, 1-14) dies are electrically coupled to the first die (103, [0035], Figs. 1-7, 1-14) face-to-face (Figs. 1-7, 1-14) by interconnects (116 fine pitch contacts are Direct Bond Interconnect (“DBI”) contacts in [0030], Figs. 1-3, 1-14) having a pitch of less than 10 microns between adjacent interconnects (DBI contacts have a pitch in a range of approximately 1 to 100 microns in [0030]) .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Wang’s feature of the second and third dies are electrically coupled to the first die face-to-face by interconnects having a pitch of less than 10 microns between adjacent interconnects to Chen’s device to have to provide a multi-chip module formed with less cost and/or less difficulty ([0003], Wang).
Chen modified by Wang stills does not expressly disclose a substrate on and coupled to the second and third dies.
However, in the same semiconductor device field of endeavor, Khanna discloses a substrate (250 module substrate connected to a printed circuit board 268 in [0018,0020], Fig. 2) on and coupled to the second and third dies (254a-n one or more bare-die semiconductor chips 254a, 254n in [0019], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Khanna’s feature of a substrate on and coupled to the second and third dies to the combination of Chen and Wang device to include a printed circuit board that carries an electronic component assembly ([0020], Khanna).
Re: Claim 2, Chen modified by Wang and Khanna discloses the microelectronic assembly of claim 1, wherein the insulating material (240, Chen) includes an inorganic material, an organic material, an organic polymer with inorganic particles, a resin material, or an epoxy material (molding layer 240 includes a polymer material in [0058], Chen).
Re: Claim 3, Chen modified by Wang and Khanna discloses the microelectronic assembly of claim 1, microelectronic assembly of claim 1, wherein the substrate of the microelectronic subassembly is a first substrate (250’s Khanna applied to Chen, 250 connected to a printed circuit board 268 in [0018,0020], Fig. 2. Khanna), and the microelectronic assembly further comprising: a second substrate (268’s Khanna applied to Chen) coupled to a top surface of the insulating material (240, Chen) and the first substrate (250’s Khanna applied to Chen) of the microelectronic subassembly (170,130,160,180, Chen).
Re: Claim 8, Chen modified by Wang and Khanna discloses the microelectronic assembly of claim 1, wherein the surface (512-surface2, Chen) of the dielectric layer (512, Chen) is a second surface (Fig. 3-Annotated) and the dielectric layer (512, Chen) further includes an opposing first surface (512-surface1 Fig. 3-Annotated, Chen), wherein the interconnects (410, Chen) are first interconnects, and the microelectronic assembly further comprising: a package substrate (230 a redistribution structure in [0047], Fig. 3, Chen) electrically coupled to the first surface (512-surface1, Chen) of the dielectric layer (512, Chen) by second interconnects (190,210 conductive pillars 190 and solder bump 210 in [0049,0051], Fig. 3, Chen).
Regarding claim 9, Chen modified by Wang and Khanna discloses the microelectronic assembly of claim 8,
Chen modified by Wang and Khanna does not expressly disclose wherein a pitch of the second interconnects is between 40 microns and 400 microns.
However, in the same semiconductor device field of endeavor, Wang discloses a pitch of interconnects (116 fine pitch contacts are Direct Bond Interconnect (“DBI”) contacts in [0030], Fig. 1-3) is between 40 microns and 400 microns (DBI contacts have a pitch in a range of approximately 1 to 100 microns in [0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Wang’s feature of a pitch of the second interconnects is between 40 microns and 400 microns to the combination of Chen, Wang and Khanna device to provide a multi-chip module formed with less cost and/or less difficulty ([0003], Wang).
Regarding claim 13, Chen modified by Wang and Khanna discloses the microelectronic assembly of claim 3, wherein the second substrate (268’s Khanna applied to Chen) is coupled to the insulating material (240, Chen) and the first substrate (250’s Khanna applied to Chen) of the microelectronic subassembly by interconnects (410, Chen) having a pitch of less than 10 microns between adjacent interconnects (116’s Wang applied to Chen in [0030], Wang).
Claim(s) 4 and 7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chen in view of Wang in view of Khanna and further in view of Velez et al. (US 20180061775 A1, hereinafter Velez, of the record).
Regarding claim 4, Chen modified by Wang and Khanna discloses the microelectronic assembly of claim 3,
Chen modified by Wang and Khanna does not expressly disclose wherein a material of the second substrate includes silicon.
However, in the same semiconductor device field of endeavor, Velez discloses wherein a material of the second substrate (202 substrate in [0025] Fig. 7A) includes silicon (202 made of silicon with a thickness of about 50-75 microns in [0025], Fig. 7A)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Velez’s feature wherein a material of the second substrate includes silicon to the combination of Chen, Wang and Khanna device to helps reduces warpage in the device ([0025], Velez).
Regarding claim 7, Chen modified by Wang and Khanna discloses the microelectronic assembly of claim 3, wherein a thickness of the second substrate (202, Velez) is between 50 microns and 800 microns (202 having a thickness of about 50-75 microns in [0025], Fig. 7A, Velez)
Claim(s) 12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chen in view of Wang in view of Khanna and further in view of Chen-H et al. (US 20210134704 A1, hereinafter Chen-H, of the record).
Regarding claim 12, Chen modified by Wang and Khanna discloses the microelectronic assembly of claim 3,
Chen modified by Wang and Khanna does not expressly disclose wherein the second substrate is coupled to the insulating material and the first substrate of the microelectronic subassembly by an adhesive or by fusion bonding.
However, in the same semiconductor device field of endeavor, Chen-H discloses wherein the second substrate (S support substrate in [0015], Fig. 9) is coupled to the insulating material (122 in [0017], Fig. 9) by an adhesive or by fusion bonding (B3-B4 bond layer to bond the support substrate by fusion bonding process in [0015], Fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chen-H’s feature of wherein the second substrate is coupled to the insulating material by an adhesive or by fusion bonding to the combination of Chen, Wang and Khanna device to obtain wherein the second substrate is coupled to the insulating material and the first substrate of the microelectronic subassembly by an adhesive or by fusion bonding to cover back surfaces area for bonding to the support substrate ([0014,0015], Chen-H).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
Prosecution Insights