DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed January 7, 2026 have been entered and considered.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 13, 2026 has been entered.
Election/Restrictions
Applicant’s election without traverse of Species 1, Species 1A, Figs. 11-12, Claims 1-13 in the reply filed on March 14, 2025 is acknowledged.
Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 14, 2025.
[MPEP 37 CFR 1.142(b) Requirement for Restriction] states: “(b) Claims to the invention or inventions not elected, if not canceled, are nevertheless withdrawn from further consideration by the examiner by the election, subject however to reinstatement in the event the requirement for restriction is withdrawn or overruled.” Due to 37 CFR 1.142(b), claims 7 and 10 are withdrawn from consideration as being drawn to non-elected species.
Claim 7 states: “the second semiconductor layer and the third semiconductor layer are omitted from the peripheral area around the cell part”, this limitation is only talked on in non-elected species Fig. 15 and 17. Claim 10 states: “the display substrate further comprises a third substrate on the third semiconductor layer”, this limitation is only talked on in non-elected species Fig. 18. Claim 8 is dependent on claim 7, therefore, Examiner will assume claim 8 is dependent on claims which claim 7 is dependent on.
The Restriction/Election requirement is still deemed proper and is therefore made FINAL.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Bower et al. (US 10181507 B2), in view of Sakariya et al. (US 20160013170 A1) and Sekine et al. (US 7842958 B1).
Regarding claim 1, Bower et al. teaches:
a circuit substrate [10] comprising pixel circuit units [80, 80R, Fig. 5], and pads [22A, 22B] electrically connected to the pixel circuit units [80, 80R, Col. 10, Lines 60-67 to Col. 11, Lines 1-5, Fig. 5];
a display substrate [30] above the circuit substrate [10], comprising light-emitting elements [20, Col. 8, Lines 6-8, Fig. 1] electrically connected to the pixel circuit units [80, 80R] and comprising a first semiconductor layer [21P, Fig. 2], an active layer [28 “light-emitting area”, Col. 9, Lines 26-31, Fig. 2] on the first semiconductor layer [21P, Fig. 2], and a second semiconductor layer [21N, Fig. 2] on the active layer [28, Fig. 2],
a circuit board [50] above the display substrate [30], and comprising circuit board pads [52A, 52B] electrically connected to the pads [22A, 22B];
pad connecting electrodes [40, 12, 60] in the via holes [stack comprising 52, 60, 12, 40, 22, Fig. 4, 7], and connected between the pads [22A, 22B] of the circuit substrate [10] and the circuit board pads [52A, 52B] of the circuit board [50].
Bower et al. does not teach:
defining via holes in a peripheral area around a cell part where the light-emitting elements are located.
a heat dissipation substrate below the circuit substrate.
Sakariya et al. teaches:
defining via holes [130 “openings”, paragraph [0040], Fig. 3C] in a peripheral area [Y-Y, paragraph [0006], Fig. 3C] around a cell part [X-X, paragraph [0006], Fig. 3C] where the light-emitting elements [400, paragraph [0041-0043], Fig. 3C-3D, 4A-4D] are located.
a heat dissipation substrate [202, paragraph [0042], Fig. 4A-4H] below the circuit substrate [200, paragraph [0042], Fig. 4A-4H].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Sakariya et al. into the teachings of Bower et al. to include defining via holes in a peripheral area around a cell part where the light-emitting elements are located, and a heat dissipation substrate below the circuit substrate, for the purpose of increasing electrical connection within device, increasing performance, leaving space for subsequent features, and enhancing dissipation of heat from device. See also, MPEP 2144.04 (VI)(C) Rearrangement of Parts.
Bower et al. and Sakariya et al. do not teach:
defining via holes penetrating the active laver and the first semiconductor layer, such that the active layer and the first semiconductor layer encircle the via holes in plan view;
Sekine et al. teaches:
defining via holes [513, Col. 7, Lines 5-18; Col. 5, Lines 2-42, Fig. 4] penetrating the active laver [22, Fig. 4] and the first semiconductor layer [21, Fig. 4], such that the active layer [22, Fig. 4] and the first semiconductor layer [21, Fig. 4] encircle the via holes [513, Fig. 4, 6] in plan view;
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Sekine et al. into the teachings of Bower et al. and Sakariya et al. to include defining via holes penetrating the active laver and the first semiconductor layer, such that the active layer and the first semiconductor layer encircle the via holes in plan view, for the purpose of serving as an alternative electrode to the conventional transparent electrode layer, facilitating the surface diffusion of current for the semiconductive light-emitting layer to achieve uniform surface light emission, improving the light emission amount and the light emission efficiency. See also, MPEP 2144.04 (VI)(C) Rearrangement of Parts.
Regarding claim 2, Bower et al., Sakariya et al. and Sekine et al. teach the display device of claim 1.
Bower et al. further teaches:
wherein the pad connecting electrodes [40, 12, 60] comprise first electrode parts [40] connected to the pads [22], second electrode parts [60] connected to the circuit board pads [52], and connecting parts [12] in the via holes [stack comprising 52, 60, 12, 40, 22, Fig. 4, 7] and connected to the first electrode parts [40] and to the second electrode parts [60].
Regarding claim 3, Bower et al., Sakariya et al. and Sekine et al. teach the display device of claim 2.
Bower et al. further teaches:
wherein the via holes [stack comprising 52, 60, 12, 40, 22, Fig. 4, 7] and the circuit board pads [52] correspond to the pads [22], and
wherein a number of the via holes [stack comprising 52, 60, 12, 40, 22, Fig. 4, 7] and a number of the circuit board pads [52] are the same as a number of the pads [22].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Bower et al. (US 10181507 B2), in view of Sakariya et al. (US 20160013170 A1) and Sekine et al. (US 7842958 B1) as applied to claim 2 above, and further in view of Nishida et al. (US 20060023762 A1).
Regarding claim 4, Bower et al., Sakariya et al. and Sekine et al. teach the display device of claim 2.
Bower et al., Sakariya et al. and Sekine et al. do not teach:
wherein the first semiconductor layer, the active layer, and the second semiconductor layer are further in the peripheral area around the cell part, and
wherein the display substrate further comprises a third semiconductor layer in both the cell part, and in the peripheral area around the cell part.
Nishida et al. teaches:
wherein the first semiconductor layer [22/80, paragraph [0059]/[0069], Fig. 18], the active layer [24/82, paragraph [0059]/[0069], Fig. 18], and the second semiconductor layer [26/246 “third semiconductor section”, paragraph [0059]/[0134], Fig. 18] are further in the peripheral area around the cell part [20 “light emitting element section”, paragraph [0059], Fig. 18], and
wherein the display substrate further comprises a third semiconductor layer [28/248 “third semiconductor section”, paragraph [0059]/[0134], Fig. 18] in both the cell part, and in the peripheral area around the cell part.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Nishida et al. into the teachings of Bower et al., Sakariya et al. and Sekine et al. to include wherein the first semiconductor layer, the active layer, and the second semiconductor layer are further in the peripheral area around the cell part, and wherein the display substrate further comprises a third semiconductor layer in both the cell part, and in the peripheral area around the cell part, for the purpose of forming features in the non-display area as to not interfere with the display features, increasing electrical connection within the device and therefore increasing performance.
Claims 5-6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Bower et al. (US 10181507 B2), in view of Sakariya et al. (US 20160013170 A1), Sekine et al. (US 7842958 B1) and Nishida et al. (US 20060023762 A1) as applied to claim 4 above, and further in view of Lee et al. (US 8054002 B2).
Regarding claim 5, Bower et al., Sakariya et al., Sekine et al. and Nishida et al. teach the display device of claim 4.
Bower et al. further teaches:
wherein the pads [22A, 22B] and the circuit board pads [52A, 52B] overlap with a part of the first semiconductor layer [21N], the active layer [28], or the second semiconductor layer [21P].
Bower et al., Sakariya et al., Sekine et al. and Nishida et al. do not teach:
wherein the pads and the circuit board pads overlap with a part of the first semiconductor layer, the active layer, or the second semiconductor layer in the peripheral area around the cell part.
Lee et al. teaches:
wherein the pads [not shown, Col. 5, Lines 15-25, Fig. 3] and the circuit board pads overlap with a part of the first semiconductor layer [240, Fig. 5-7], the active layer [220, Fig. 5-7], or the second semiconductor layer [200, Fig. 5-7] in the peripheral area [120, Fig. 3] around the cell part [140, Fig. 3].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Lee et al. into the teachings of Bower et al., Sakariya et al., Sekine et al. and Nishida et al. to include wherein the pads and the circuit board pads overlap with a part of the first semiconductor layer, the active layer, or the second semiconductor layer in the peripheral area around the cell part, for the purpose of providing necessary features in the non-display area, leaving space for subsequent processing, and increasing electrical connections within the device. One of ordinary skill in the art would find the location of features to be obvious over the prior art if changing the location of the feature would not modify the operation of the device. See also, MPEP 2144.04 (VI)(C) Rearrangement of Parts.
Regarding claim 6, Bower et al., Sakariya et al., Sekine et al. and Nishida et al. teach the display device of claim 4.
Bower et al. further teaches:
wherein the second electrode parts [60, Fig. 2, 4] are on the third semiconductor layer [21C, Fig. 2].
Bower et al., Sakariya et al., Sekine et al. and Nishida et al. disclose the above claimed subject matter.
However, Bower et al., Sakariya et al., and Nishida et al. do not teach:
wherein the via holes further penetrate the second semiconductor layer and the third semiconductor layer such that the second semiconductor layer and the third semiconductor layer encircle the via holes in plan view.
Sekine et al. teaches:
wherein the via holes [513, Col. 7, Lines 5-18; Col. 5, Lines 2-42, Fig. 4] further penetrate the second semiconductor layer [23, Fig. 4] and the third semiconductor layer [21, Fig. 4] such that the second semiconductor layer [23, Fig. 4] and the third semiconductor layer [21, Fig. 4] encircle the via holes [513, Fig. 4, 6] in plan view.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Sekine et al. into the teachings of Bower et al., Sakariya et al., Sekine et al. and Nishida et al. to include wherein the via holes further penetrate the second semiconductor layer and the third semiconductor layer such that the second semiconductor layer and the third semiconductor layer encircle the via holes in plan view, for the purpose of serving as an alternative electrode to the conventional transparent electrode layer, facilitating the surface diffusion of current for the semiconductive light-emitting layer to achieve uniform surface light emission, improving the light emission amount and the light emission efficiency.
Regarding the third semiconductor layer, MPEP 2144.04 (VI)(B) Duplication of Parts states: In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
Regarding the location of the features, MPEP 2144.04 (VI)(C) Rearrangement of Parts states: In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
Therefore, one of ordinary skill in the art would find an additional semiconductor layer and the location of features to be obvious.
Bower et al., Sakariya et al., Sekine et al. and Nishida et al. do not teach:
wherein the via holes in the peripheral area around the cell part.
Lee et al. teaches:
wherein the via holes [between 240/220/200 stack, Col. 4, Lines 43-49, Fig. 6] in the peripheral area [120, Col. 2, Lines 64-67, Fig. 3, 6-7] around the cell part [140, Fig. 3, 6-7].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Lee et al. into the teachings of Bower et al., Sakariya et al., Sekine et al. and Nishida et al. to include wherein the via holes in the peripheral area around the cell part, for the purpose of increasing efficiency and storage capacity, increasing electrical connections within the device and therefore increasing performance and yield, and enhancing power management and heat dissipation.
Regarding claim 11, Bower et al., Sakariya et al., Sekine et al. and Nishida et al. teach the display device of claim 4.
Bower et al., Sakariya et al., Sekine et al. and Nishida et al. do not teach:
wherein parts of the second semiconductor layer in the light-emitting elements are connected to part of the second semiconductor layer in the peripheral area around the cell part.
Lee et al. teaches:
wherein parts of the second semiconductor layer [240] in the light-emitting elements [120a-d, Fig. 3, 5] are connected to part of the second semiconductor layer [200, Fig. 5] in the peripheral area [120, Fig. 3, 6-7] around the cell part [140, Fig. 3, 6-7].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Lee et al. into the teachings of Bower et al., Sakariya et al., Sekine et al. and Nishida et al. to include wherein parts of the second semiconductor layer in the light-emitting elements are connected to part of the second semiconductor layer in the peripheral area around the cell part, for the purpose of ensuring proper connections between features, increasing density and performance.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Bower et al. (US 10181507 B2), in view of Sakariya et al. (US 20160013170 A1), Sekine et al. (US 7842958 B1) and Nishida et al. (US 20060023762 A1) as applied to claim 4 above, and further in view of Kang et al. (US 9397261 B2), and Lee et al. (US 8054002 B2).
Regarding claim 8, Bower et al., Sakariya et al., Sekine et al. and Nishida et al. teach the display device of claim 4.
Bower et al., Sakariya et al., Sekine et al. and Nishida et al. do not teach:
wherein a top surface of the display substrate is lower in regions where the via holes are located.
Kang et al. teaches:
wherein a top surface of the display substrate [151 “support member”, Col. 12, Lines 4-19, Fig. 10] is lower in regions where the via holes [143, Col. 17, Lines 29-36, Fig. 10] are located
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kang et al. into the teachings of Bower et al., Sakariya et al., Sekine et al. and Nishida et al. to include the wherein a top surface of the display substrate is lower in regions where the via holes are located, for the purpose of ensuring proper connections of features, increasing performance and yield and increasing density.
Bower et al., Sakariya et al., Sekine et al., Nishida et al. and Kang et al. do not teach:
wherein a top surface of the display substrate is lower in regions where the via holes are located than in other regions of the peripheral area around the cell part.
Lee et al. teaches:
wherein a top surface of the display substrate is lower in regions where the via holes are located than in other regions of the peripheral area [120, Col. 2, Lines 64-67; Col. 4, Lines 43-49, Fig. 3, 6-7] around the cell part [140, Fig. 3, 6-7].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Lee et al. into the teachings of Bower et al., Sakariya et al., Sekine et al., Nishida et al., and Kang et al. to include the wherein a top surface of the display substrate is lower in regions where the via holes are located than in other regions of the peripheral area around the cell part, for the purpose of ensuring proper connections of features, increasing performance and yield and increasing density. One of ordinary skill in the art would find the location of features to be obvious over the prior art if changing the location of the feature would not modify the operation of the device. See also, MPEP 2144.04 (VI)(C) Rearrangement of Parts.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Bower et al. (US 10181507 B2), in view of Sakariya et al. (US 20160013170 A1), Sekine et al. (US 7842958 B1) and Nishida et al. (US 20060023762 A1) as applied to claim 4 above, and further in view of Bibl et al. (US 9111464 B2).
Regarding claim 9, Bower et al., Sakariya et al., Sekine et al. and Nishida et al. teach the display device of claim 4.
Bower et al., Sakariya et al., Sekine et al. and Nishida et al. do not teach:
wherein the display substrate further comprises color control structures on the third semiconductor layer in the cell part, color filters on the color control structures, and a second substrate on the color filters.
Bibl et al. teaches:
wherein the display substrate [102, Col. 27, Lines 31-33, Fig. 12A-12F] further comprises color control structures [310 “wavelength conversion layer”, Col. 29, Lines 39-43, Fig. 12A-12E] on the third semiconductor layer [405/409 of 400, Col. 12, Lines 25-50, Fig. 1C, 12A-12E] in the cell part [104 “pixel area”/X-X, Col. 8, Lines 11-22, Fig. 1A, 1C], color filters [328, Col. 29, Lines 39-52, Fig. 12A-12E] on the color control structures [310], and a second substrate [500, Col. 30, Lines 43-61, Fig. 14A-14B] on the color filters [328].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Bibl et al. into the teachings of Bower et al., Sakariya et al., Sekine et al. and Nishida et al. to include wherein the display substrate further comprises color control structures on the third semiconductor layer in the cell part, color filters on the color control structures, and a second substrate on the color filters, for the purpose of controlling wavelength of light emitted from color conversion and color filter, improving display and performance.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Bower et al. (US 10181507 B2), in view of Sakariya et al. (US 20160013170 A1) and Sekine et al. (US 7842958 B1) as applied to claim 1 above, and further in view of Jintyou et al. (US 20200161340 A1).
Regarding claim 12, Bower et al., Sakariya et al., and Sekine et al. teach the display device of claim 1
Bower et al., Sakariya et al., and Sekine et al. do not teach:
wherein the circuit board defines a first opening corresponding to the cell part of the display substrate, and
wherein the circuit board does not overlap with the cell part of the display substrate, and is in the peripheral area around the cell part.
Jintyou et al. teaches:
wherein the circuit board [716, paragraph [0316], Fig. 13] defines a first opening corresponding to the cell part [711/702/711/704, Fig. 13] of the display substrate [701, paragraph [0342], Fig. 13], and
wherein the circuit board [716, Fig. 13] does not overlap with the cell part [711/702/711/704, Fig. 13] of the display substrate [701, Fig. 13], and is in the peripheral area around the cell part [711/702/711/704, Fig. 13].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Jintyou et al. into the teachings of Bower et al., Sakariya et al. and Sekine et al. to include wherein the circuit board defines a first opening corresponding to the cell part of the display substrate, and wherein the circuit board does not overlap with the cell part of the display substrate, and is in the peripheral area around the cell part, for the purpose of ensuring proper connections between features within the device, increasing density, leaving space for subsequent connections and improving performance.
Regarding claim 13, Bower et al., Sakariya et al., Sekine et al. and Jintyou et al. teach the display device of claim 12.
Bower et al., Sakariya et al., Sekine et al. and Jintyou et al. disclose the above claimed subject matter.
However, Bower et al., Sakariya et al., and Sekine et al. do not teach:
wherein a top surface of the cell part of the display substrate protrudes from a top surface of the circuit board.
Jintyou et al. teaches:
wherein a top surface of the cell part [711/702/711/704, Fig. 13] of the display substrate [701, Fig. 13] protrudes from a top surface of the circuit board [716, Fig. 13].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Jintyou et al. into the teachings of Bower et al., Sakariya et al., Sekine et al. and Jintyou et al. to include the wherein a top surface of the cell part of the display substrate protrudes from a top surface of the circuit board, for the purpose of improving performance through thickness of features, leaving space for subsequent connections, improving heat tolerance and improving power handling capabilities.
Response to Arguments
Applicant’s arguments with respect to independent claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues on pages 1-4, Section: 1. Claim Rejections Under 35 U.S.C. §103, in remarks filed January 7, 2026 that the current prior art of record does not teach the amendments to independent claim 1. Examiner agrees with Applicant; However, after a new line of search and consideration of the prior art, the amendments to independent claim 1 can be overcome by newly cited source Sekine et al. (US 7842958 B1).
Applicant argues on page 4, Section: 1. Claim Rejections Under 35 U.S.C. §103, in remarks filed January 7, 2026 that dependent claims 2-14 depend from claim 1 and should be in condition for allowance. Examiner disagrees with Applicant due to at least the reasons mentioned above.
In summary, the amendments to independent claim 1 can be overcome by newly cited source Sekine et al. (US 7842958 B1). All claims directly or indirectly dependent on independent claim 1 are also rejected for at least the reasons mentioned above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID MICHAEL HELBERG whose telephone number is (571)270-1422. The examiner can normally be reached Mon.-Fri. 8am-5pm EST.
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/D.M.H./Examiner, Art Unit 2815 03/04/2026
/MONICA D HARRISON/Primary Examiner, Art Unit 2815