DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see remarks, filed 05/14/2026, with respect to the rejection(s) of claim(s) 1-2, 4-5 and 7-10 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an updated prior art search.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-2, 4-5 and 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US-20210020574-A1 – hereinafter Yu) in view of Chakrabarty et al. (US-20170343603-A1 – hereinafter Chakrabarty), and further in view of Sharan et al. (US-20200381350-A1 – hereinafter Sharan).
Regarding claim 1, Yu teaches a fan-out package structure (Fig.6 66’; ¶0040), comprising:
an upper redistribution layer (Fig.6 40; ¶0035) comprising a first surface (top surface of 40) and a second surface (bottom surface of 40) opposite to the first surface (top surface of 40);
a die disposed (Fig.6 46; ¶0035) on the first surface (top surface of 40) of the upper redistribution layer (40) and electrically connected to the upper redistribution layer (40);
a passive element (Fig.6 26; ¶0034) disposed on the second surface (bottom surface of 40) of the upper redistribution layer (40) and electrically connected to the upper redistribution layer (40); and
an active element (Fig.6 32; ¶0028) disposed on the second surface (bottom surface of 40) of the upper redistribution layer (40) and electrically connected to the upper redistribution layer (40), wherein the active element (32) is laterally adjacent to the passive element (26), and the die (46) is electrically connected to the active element (32) and the passive element (26) through the upper redistribution layer (40);
a lower redistribution layer (Fig.6 58; ¶0044); and
a first conductive pillar (Fig.6 24; ¶0040) configured to connect the upper redistribution layer (40) and the lower redistribution layer (58);
a second conductive pillar (Fig.6 28; ¶0034) configured to connect the passive element (26) and the upper redistribution layer (40); and
a third conductive pillar (Fig.6 36; ¶0032) configured to connect the active element (32) and the upper redistribution layer (40), and wherein a pitch of the first conductive pillar (24) is greater than or equal to a pitch of the third conductive pillar (36);
wherein the upper redistribution layer (40) comprises:
a first connection pad (Fig.6 40 has bond pads on the top surface; ¶0033) formed on the first surface (top surface of 40) and configured to connect with the die (46);
a plurality of second connection pads (Fig.6 28; ¶0032) formed on the second surface (bottom surface of 40) and configured to connect with the passive element (26);
a third connection pad (Fig.6 36; ¶0032) formed on the second surface (bottom surface of 40) and configured to connect with the active element (32);
a first wire (Fig.6 RDL 42; ¶0031) formed in the upper redistribution layer (40) and configured to vertically connect the first connection pad (bond pads on the top surface; ¶0033) and one of the plurality of second connection pads (28).
Yu does not teach a second wire formed in the upper redistribution layer and configured to laterally connect one of the second connection pads and the third connection pad, and
wherein the pitch of the third conductive pillar is greater than or equal to a pitch of the second conductive pillar.
Chakrabarty teaches an interposer (Fig.14; ¶0095 of Chakrabarty) comprising horizontal interconnects (Fig.14; ¶0095 and ¶0096 of Chakrabarty) for die-to-die interconnections (¶0096 of Chakrabarty).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a horizontal die-to-die interconnection in the upper redistribution layer (40 of Yu) between a second pad (28 of Yu) and a third pad (36 of Yu) as taught by Chakrabarty (Fig.14 of Chakrabarty). A practitioner of ordinary skill would have been motivated to make this modification for the benefit of higher interconnect density and lower parasitic electrical effects.
Yu in view of Chakrabarty does not teach wherein the pitch of the third conductive pillar is greater than or equal to a pitch of the second conductive pillar.
Sharan teaches a semiconductor device (Fig.2 200; ¶0026 of Sharan) with package components that can have a high density pillar pitch (Fig.2 205; ¶0028 of Sharan) or a low density pillar pitch (Fig.2 208; ¶0028 of Sharan).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the third pitch (pitch of 36 of Yu) to be greater than the second pitch (pitch of 28 of Yu) as taught by Sharan (Fig.2 of Sharan) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of bump density translation and flexible bump/via pattern design (¶0019 of Sharan).
Regarding claim 2, the aforementioned combination of Yu in view of Chakrabarty from claim 1 teaches the fan-out package structure according to claim 1, wherein an orthographic projection of the active element (32 of Yu) on the upper redistribution layer (40 of Yu) partially overlaps with an orthographic projection of the die (46 of Yu) on the upper redistribution layer (40 of Yu), and an orthographic projection of the passive element (26 of Yu) on the upper redistribution layer (40 of Yu) overlaps with the orthographic projection of the die (46 of Yu) on the upper redistribution layer (40 of Yu).
Regarding claim 4, the aforementioned combination of Yu in view of Chakrabarty from claim 1 teaches the fan-out package structure according to claim 1, further comprising:
a first insulating layer (Fig.6 38; ¶0030 of Yu) disposed on the second surface (bottom surface of 40 of Yu) of the upper redistribution layer (40 of Yu) and configured to encapsulate the passive element (26 of Yu) and the active element (32 of Yu); and
a second insulating layer (Fig.6 52; ¶0035 of Yu) disposed on the die (46 of Yu) and the upper redistribution layer (40 of Yu) and configured to encapsulate the die (46 of Yu), wherein the second insulating layer (52 of Yu) comprises an opening (where 46 is exposed), and a surface (top surface of 46 of Yu) of the die (46 of Yu) is exposed to an outside through the opening (where 46 is exposed).
Regarding claim 5, the aforementioned combination of Yu in view of Chakrabarty from claim 1 teaches the fan-out package structure according to claim 1, further comprising:
a patterned adhesive layer (Fig.3 30 and 34; ¶0018 and ¶0028 of Yu) disposed on the lower redistribution layer (58 of Yu), wherein one surface (bottom surface of 26 of Yu) of the passive element (26 of Yu) and one surface (bottom surface of 32 of Yu) of the active element (32 of Yu) are adhered to the lower redistribution layer (58 of Yu) through the patterned adhesive layer (30 and 34 of Yu), and one other surface (top surface of 26 of Yu) of the passive element (26 of Yu) and one other surface (top surface of 32 of Yu) of the active element (32 of Yu) are electrically connected to the upper redistribution layer (40 of Yu).
Regarding claim 7, the aforementioned combination of Yu in view of Chakrabarty from claim 1 teaches the fan-out package structure according to claim 1, further comprising a underfill layer (Fig.6 50; ¶0035 of Yu) disposed between the upper redistribution layer (40 of Yu) and the die (46 of Yu).
Regarding claim 8, the aforementioned combination of Yu in view of Chakrabarty from claim 1 teaches the fan-out package structure according to claim 1, further comprising a protective ring or a protective cover (Fig.6 52; ¶0035 of Yu) disposed on the first surface (top surface of 40 of Yu) of the upper redistribution layer (40 of Yu) and surrounding the die (46 of Yu).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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