Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
1. Applicants’ communication filed 12/30/2026 has been carefully considered by the examiner. The arguments advanced therein are persuasive with respect to the rejections of record, and those rejections are accordingly withdrawn. In view of a further search and consideration, however, a new rejection is set forth further below. This action is not made final.
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9, 11-14, 17-19, and 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US 2021/0296314).
Regarding claim 9, Kang et al. discloses, as shown in Figures 1 and 12, a semiconductor structure comprising:
a first vertical transport field-effect transistor (102a) in a lower semiconductor layer; and
a second vertical transport field-effect transistor (102c) in an upper semiconductor layer, wherein the first vertical transport field-effect transistor is offset from the second vertical transport field-effect transistors by one-half of a contacted gate pitch of the second vertical transport field-effect transistor.
Regarding claim 11, Kang et al. discloses the first vertical transport field-effect transistor is a first type field-effect transistor and the second vertical transport field-effect transistor is a second type field-effect transistor [0041]-[0042].
Regarding claim 12, Kang et al. discloses the offset is one-half of a contacted gate pitch of the second vertical transport field-effect transistor (Figures).
Regarding claim 13, Kang et al. discloses the second plurality of vertical transport field-effect transistors in the upper semiconductor layer are each horizontally offset from the first plurality of vertical transport field-effect transistors in the lower semiconductor layer by a range between 0.3 to 0.7 contacted gate pitch (half pitch) (Figure 12).
Regarding claim 14, Kang et al. discloses, as shown in Figures 1 and 12, a semiconductor structure, the semiconductor structure comprising:
one or more vertical transport field-effect transistors (102a) in an upper semiconductor layer, wherein the one or more vertical transport field-effect transistors in the first semiconductor layer are separated by one contacted gate pitch;
one or more vertical transport field-effect transistors (102c) in a lower semiconductor layer, wherein the one or more vertical transport field-effect transistors in the lower semiconductor layer are separated by one contacted gate pitch; and
wherein the one or more vertical transport field-effect transistors in the upper semiconductor layer are offset from the one or more vertical transport field-effect transistors in the lower semiconductor layer.
Regarding claim 17, Kang et al. discloses the one or more vertical transport field-effect transistors in the lower semiconductor layer is a first type field-effect transistor and wherein the one or more vertical transport field-effect transistors in the upper semiconductor layer is a second type field-effect transistor [0041]-[0042].
Regarding claim 18, Kang et al. discloses the offset is in a range between 0.3 to 0.7 of the contacted gate pitch (half pitch) (Figure 12).
Regarding claim 19, Kang et al. discloses, as shown in Figures 1 and 12, a semiconductor structure, the semiconductor comprising:
a first pair of vertical transport field-effect transistors (12a) in a lower semiconductor layer;
a second pair of vertical transport field-effect transistors (12c) in an upper semiconductor layer, wherein each of the second pair of vertical transport field-effect transistors in the upper semiconductor layer is horizontally offset by half of a contacted gate pitch from at least one vertical transport field-effect transistors in the lower semiconductor layer; and
wherein the first pair of vertical transport field-effect transistors in the lower semiconductor layer are a first type of vertical transport field-effect transistor connected in parallel and the second pair of vertical field-effect transistors in the upper semiconductor layer are a second type of vertical transport field-effect transistor connected in series.
Regarding claim 23, Kang et al. discloses, as shown in Figures 1 and 12, a semiconductor structure, the semiconductor structure comprising:
a first pair of vertical transport field-effect transistors (12a) in a lower semiconductor layer;
a second pair of vertical transport field-effect transistors (12c) in an upper semiconductor layer, wherein each of the second pair of vertical transport field-effect transistors in the upper semiconductor layer is horizontally offset by half of a contacted gate pitch from at least one vertical transport field-effect transistors in the lower semiconductor layer; and
wherein the first pair of vertical transport field-effect transistors in the lower semiconductor layer are a first type of vertical transport field-effect transistor connected in series and the second pair of vertical field-effect transistors in the upper semiconductor layer are a second type of vertical transport field-effect transistor connected in parallel
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 2021/0296314, of record) in view of Pethe et al. (US 2014/0077305, of record).
Kang et al. discloses the claimed invention including the semiconductor structure, as explained in the above rejection. Kang et al. further discloses the first plurality of vertical transport field-effect transistors in the lower semiconductor layer and the second plurality of vertical transport field-effect transistor have one or more conductive vias (gate contacts) can be in communication with either the gate structure of the first FET device or the gate structure of the second FET device [0042]. Kang et al. does not disclose the one or more vertical transport field-effect transistors in the lower semiconductor layer each has a contact over an active gate (COAG). However, Pethe et al. discloses a first plurality of vertical transport field-effect transistors each have a gate contact over an active gate (COAG) (gate contacts 350, 460,416,550 over active gates 308C, 308D, 450). Note Figures 3F-7 of Pethe et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the one or more vertical transport field-effect transistors in the lower semiconductor layer of Kang et al. each have the COAG, such as taught by Pethe et al. in order to further reduce a standard cell area.
5. Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 2021/0296314, of record).
Kang et al. discloses the claimed invention including the semiconductor structure, as explained in the above rejection. Kang et al. does not disclose the first pair of vertical transport field-effect transistors in the lower semiconductor layer and the second pair of vertical transport field-effect transistors form a two input NAND circuit. However, it is a common practice to connect the transistors with different configuration to perform the desired logic. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to connect the first pair of vertical transport field-effect transistors in the lower semiconductor layer and the second pair of vertical transport field-effect transistors of Kang et al. to form a two input NAND circuit in order to perform the desired logic.
Allowable Subject Matter
6. Claims 1-3 and 6-8 are allowed.
7. Claims 10, 15, 20-22 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
8. The following is a statement of reasons for the indication of allowable subject matter:
Applicant' s claims 1-3, 6-8, 10, 15, 20-22, and 24 are allowable over the references of record because none of these references disclose or can be combined to yield the claimed semiconductor structure comprising the second plurality of VTFETs is offset from the first plurality of VTFETs, a first interconnect is above both the first VTFET and the second VTFET, and each of the first contact and the second contact has a single, direct straight, vertical connection to the first interconnect, in combination with the remaining claimed limitations of claim 1; the first vertical transport field-effect transistor has a straight, vertical contact and the second vertical transport field-effect transistor has a straight, vertical contact, as recited in claim 10; the one or more vertical transport field-effect transistors in the lower semiconductor layer have straight, vertical contacts connecting to interconnect wiring above the one or more vertical transport field-effect transistors in the upper semiconductor layer, as recited in claim 15; each of the first pair of vertical transport field-effect transistors in the lower semiconductor layer and each of the second pair of vertical transport field-effect transistors in the upper semiconductor layer have a straight, vertical contact to an interconnect wire above the second pair of vertical transport field-effect transistors, as recited in claim 20; a bottom conduction plane connecting to at least one of the first pair of the first type vertical transport field-effect transistors in the lower semiconductor layer; and a power rail above and connected to at least one of the second pair of the second type vertical transport field-effect transistors in the upper semiconductor layer, as recited in claim 21; each of the first pair of vertical transport field-effect transistors in the lower semiconductor layer and each of the second pair of vertical transport field-effect transistors in the upper semiconductor layer have a straight, vertical contact to an interconnect wire above the second pair of vertical transport field-effect transistors, as recited in claim 24.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm.
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/HUNG K VU/ Primary Examiner, Art Unit 2897