DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement of RCE Filing and Status of Claims
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114.
Applicant's submission filed on 12/22/25 has been entered.
The amendment filed on 12/22/25 has been entered.
Applicant amended Claim 1.
Applicant earlier cancelled Claims 16-20 and withdraw from examination Claim 13 as belonging to the invention not chosen for examination.
Claims 1-12 and 14-15 are examined on merits herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 2022/0068896) in view of Chang et al. (US 2022/0375852) and Mignot (US 2020/0357692).
In re Claim 1, Kwon teaches an integrated circuit device comprising (Fig. 2A):
a lower metal via 110V (disposed directly on LP) within a first insulating layer 111 (paragraph 0022);
an upper metal via 120V (disposed directly on 110W) in a second insulating layer 112 (paragraph 0022) on the first insulating layer 111;
a lower metal wire 110W (paragraph 0026) in the second insulating layer 112 comprising a lower surface contacting the lower metal via 110V and an upper surface contacting the upper metal via 120V (as shown in Fig. 2A); and
an upper metal wire 120W (paragraph 0033) on the upper metal via 120V, wherein
the upper metal via 120V is between the lower metal wire 110W and the upper metal wire 120W, and wherein
the upper metal via 120V and the lower metal wire 110W are connected to each other, wherein
a width of an upper end of the lower metal wire 110W is greater than a width of an upper surface of the upper metal via 120V.
Kwon does not explicitly teach that the upper metal via and the lower metal wire are connected to each other without an interface therebetween, since Kwon shows that both, the upper metal via 120V and the lower metal wire 110W, are created from a stack of a seed layer and a main layer, such as 114 (seed)/116(main) for 110W and 124(seed)/126(main) for 120V. However, Kwon teaches that a seed layer 114 and a main layer 116 can be made from a same material with no distinct interface (paragraphs 0030-0031) and a seed layer 124 and a main layer 126 are made from a same material as 114 and 116 (paragraph 0038), e.g., all 4 layers can be made from a same material, where, per Kwon, a combination of a seed layer and a main layer can create a single unified body (e.g., of a same material, paragraph 0031), such as a unified body made from copper or from titanium or from their alloys (paragraph 0030). It would have been obvious for one of ordinary skill in the art before filing the application to use for seed layers (114 and 124) and for main layers (116 and 126) a same metal material, where it is desirable to limit a number of metal materials used in the device.
Although Kwon is silent about existence or absence of an interface between layers 120V and 110W, one of ordinary skill in the art before the effective date of filing the application would understand that since these layers are created from a same material, they can be created without an interface, e.g., the upper metal via and the lower metal wire can be created with no interface, when desired.
Kwon does not teach that the lower metal via, the lower metal wire and the upper metal via comprise ruthenium (Ru) or molybdenum (Mo) – he teaches copper (Cu) or titanium (Ti, paragraphs 0030, 0038).
Kwon further does not teach that a side surface of the lower metal wire is aligned with a side surface of the upper metal via.
Chang teaches (Figs. 1 and Fig. 16H) a circuit, in which an upper metal via 80S (or 80) and a lower wire 60 (the number 60 is shown in Figs. 2A/B, 16A, paragraphs 0032, 0065), when made from a same material, are connected to each other with no interface therebetween (paragraphs 0065, 0067). Chang further teaches that a wire layer (such as layer 60) and a via 80S may comprise Cu, Ti, or Ru (paragraphs 0033, 0038).
Mignot teaches that a side surface of a wire 18 (Fig. 6, paragraph 0030, the wire can be created from Cu or Ru, paragraph 0034) is aligned with a side surface of an upper located via (created within a via opening 19 in Fig. 4, paragraph 0044, and also created from Cu or Ru, paragraph 0049).
Kwon, Chang, and Mignot teach analogous arts directed towards structures comprised interconnects created from wires and vias, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Kwan device in view of the Chang and Mignot devices, since they are from the same field of endeavor, and Chang and Mignot created successfully operated devices.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Kwon structure such that a connection between the upper metal via and the lower wire was without an interface therebetween (per Chang), if it is desirable to create interconnects based on the Chang method in order to fabricate advanced semiconductor devices (Chang, paragraph 0002).
It would have been also obvious for one of ordinary skill in the art before the effective date of filing the application to further modify the Kwon device by substituting Cu m for creating upper and lower vias and wires with Ru (per Chang and Mignot), if such material is preferred for the manufacturer. See MPEP 2144.07 Art Recognized Suitability for an Intended Purpose: The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious); and/or Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988).
It would have been further obvious for one of ordinary skill in the art before the effective date of filing the application to choose such shapes of the lower metal wire and the upper metal via that a side surface of the lower metal wire would be aligned with a side surface of the upper metal via, if such shapes of these elements are preferred for the manufacturer. Please, note that in accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
In re Claim 2, Kwon/Chang/Mignot teaches the integrated circuit device of Claim 1 as cited above, wherein vias and wires are created based on the Chang device (and on the Mignot device), where Chang shows (Figs. 16A-16H) that each of the (lower) metal via 80 and the (lower) metal wire 60 is a monolithic layer, wherein in Fig. 1, Chang shows that a combination of three metal wires and two metal vias disposed in a stack can be created as a monolithic layer without interfaces. Kwon also teaches (Fig. 2A) that each of his lower metal via and lower metal wire is a monolithic layer (when they, including their seed layers and main layers, are created from a same material, as shown for Claim 1, or when no seed layers are used, but main layers are made from a same material, paragraph 0030).
In re Claim 3, Kwon/Chang/Mignot teaches the integrated circuit device of Claim 1 as cited above.
Kwon teaches that all upper and lower metal wires and metal vias (including layers 110V, 110W, 120V and 120W) can be created from a same metal (as shown for Claim 1), and would have been obvious for one of ordinary skill in the art before the effective date of filing the application that these elements are created from Ru, since layers 114, 116, 124 and 126 of Kwon were created from Ru (as shown for Claim 1) (per Chang and Mignot)
Kwon further teaches (paragraph 0032) that dielectric 112, in which the lower metal wire and the upper via are located, is made from silicon oxide. It would have been obvious for one of ordinary skill in the art before the effective date of filing the application that the interface between the lower metal wire and the lower metal via would be devoid of nitrogen, since Kwon (modified per Chang and Mignot) does not use nitrogen in the process of creating the cited interface.
In re Claim 4, Kwon/Chang/Mignot teaches the integrated circuit device of Claim 1 as cited above, wherein each of the lower metal via, the lower metal wire and the upper metal via consists of Ru or Mo – it was shown that these elements consist of Ru.
In re Claim 5, Kwon/Chang/Mignot teaches the integrated circuit device of Claim 1 as cited above.
Where a Chang structures of Fig. 1 or Fig. 16H, showing monolithic combinations of wires and vias, are implemented for creation of the Kwon’s upper metal via and lower metal wire (of Fig. 2A), it would have been obvious for one of ordinary skill in the art before filing the application that the lower metal wire is a lower portion of a monolithic layer, and the upper metal via is an upper portion of the monolithic layer.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon/Chang/Mignot in view of Dai et al. (US 2020/0126841).
In re Claim 6, Kwon/Chang/Mignot teaches the integrated circuit device of Claim 5 as cited above, including the monolithic layer.
Kwon/Chang/Mignot does not teach that a width of the monolithic layer decreases with increasing distance from the lower metal via.
Dai teaches (Fig. 2, paragraph 0019) a metal element 108 that can be either a via, a metal wire, or a combination of a via and a wire, and, as it is shown in Fig. 2 (and in a corresponding method of its manufacture) the combination of a wire and a via is a monolithic layer. Dai further teaches that a width of the monolithic layer 108 decreases with increasing distance from a lower metal via 104.
Kwon/Chang/Mignot and Dai teach analogous arts directed to stacks of vias and metal layers, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Kwon/Chang device in view of the Dai device, since the arts are from the same field of endeavor, and Dai created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Kwon/Chang/Mignot device of Claim 5 the monolithic layer comprised the lower meal wire and the upper metal via in such shape that the width of the monolithic layer would decrease with increasing distance from the lower metal via, if such shape is preferred by a manufacturer. However, in accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
Allowable Subject Matter
Claims 9-12 and 14-15 are allowed.
Claims 7-8 are objected to since Claim 7 contains allowable subject matter, but depends on the rejected Claim 1, and Claim 8 depends on Claim 7.
Reason for Identifying Allowable Subject Matter
Re Claim 9: Although such prior arts as Tsai et al. (US 2014/0239501), Kwon (US 2022/0068896), and Chang et al. (US 2022/0375852), teach most limitations of Claim 9, combining these prior arts to meet all limitations of Claim 9 is relatively complicated to render the claim obvious.
Re Claims 10-12 and 14-15: Claims 10-12 and 14-15 are allowed due to dependency on Claim 9.
Re Claim 13: Earlier withdrawn from examination Claim 13 could be rejoined with Claim 9 during a step of examination related to allowance.
Re Claim 7: Although Tsai teaches the limitation of Claim 8: “an upper surface of the lower metal via comprises a recess”, it is not easy to create a structure comprised the limitation of Claim 7 with all limitations of the amended Claim 1, on which Claim 7 depends.
The prior arts of record include all prior arts cited by the current Office Action above, not cited by the current Office Action - prior arts cited by the previous Office Action, such as Lee et al. (US 2022/0013467), Teng et al. (US 2014/0167229), Ota et al. (US 2007/0138638).
Response to Arguments
Applicant’ arguments (REMARKS, filed 12/22/25) have been fully considered.
Regarding arguments first through third on obviousness or non-obviousness of combination of Kwon and Chang (REMARKS, pages 6-9), please, consider the following responses below:
First, Kwon does not “teach away” from absence of an interface between the lower wire and the upper via, since, as the current Office Action points out, all seed and main layers in the Kwon structure may be created from a same metal, allowing creating a stack of a seed layer and a main layer without an interface as a unified body, as Kwon teaches in paragraphs 0030, 0031, 0038. Use of a same metal for all vias and wires (when it is desired to limit a number of metal materials in the device) allows creating the lower wire and the upper via without an interface, when needed. Chang provides a good example for creating a metal via and a metal wire without an interface, explicitly pointing out an absence of an interface. Based on the Chang teaching, and in view of the Kwon’ teaching on creation of seed and main layers as a unified body and allowing to create all seed layers and all wires from a same metal, one would create a no-interface stack of the lower wire and the upper via, if desirable.
Second (REMARKS, page 8), disposition of a stack of a wire and a via in a same insulation layer or in different insulation layers has nothing to do with a possibility of creating the stack of a via and a wire - with or without an interface. Moreover, creation of a stack – with or without an interface – does not need any motivation – it is a designer choice: Please, note that it is easy to create an opening for a stack (of a wire and a via) in one insulating layer, as well as in a stack of two insulating layers. It is further easy to fill this opening with one metal – which allows creating the via and a wire without an interface (in one insulating layer or in a stack of two insulating layers), or filling the opening with two metals – one for the via and one for the metal, which would create the stack with an interface – in one insulating layer or in a stack of more insulating layers. In view of the above, a citation of MPEP 2141 is improper – creation of a wire and a via stack with or without interface – is a designer choice.
The third arguments (REMARKS, page 9) is related to a hindside, since one of ordinary skill in the art could create a stack of a seed layer and a main layer in the Kwon device using different metals, which definitely prevents one of ordinary skill in the art creating a stack of the wire and via without an interface. Please, be reminded that in accordance with MPEP 2145, "any judgment on obviousness is in a sense necessarily a reconstruction based on hindsight reasoning, but so long as it takes into account only knowledge which was within the level of ordinary skill in the art at the time the claimed invention was made and does not include knowledge gleaned only from applicant’s disclosure, such a reconstruction is proper." In re McLaughlin, 443 F.2d 1392, 1395, 170 USPQ 209, 212 (CCPA 1971).
Regarding a new limitation of Claim 1 (REMARKS, page 9), Examiner agrees with Kwon/Chang does not teach this limitation. However, the limitation is known in the art and, as the current Office Action shows, a new combination of prior art teaching all limitations of the amended Claim 1.
The Examiner disagrees with the applicant statement on allowability of all pending claims of the application (REMARKS, pages 9-10), but the application has claims that were already allowed and limitations that can be added into Claim 1 to make the application allowable.
Conclusion
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 01/13/26