DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/16/2025 has been entered.
Response to Amendment/Argument
Applicant's arguments filed 12/16/2025 with respect to the specification have been fully considered but they are not persuasive. The previous office action stated that the specification and drawings were replete with issues with some examples stated. While the specific examples previously stated were addressed, others still persist that impact the consistency between the claims, the drawings and the written description. The specific issue affecting claim 1 is stated below in detail, but please review the drawings and written description for other inconsistencies.
Applicant’s arguments, see remarks, filed 12/16/2025, with respect to the rejection(s) of claim(s) 1-4, 6-9, 11-14, 16-17, 19 and 21-23 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an updated prior art search.
Specification
35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, requires the specification to be written in “full, clear, concise, and exact terms.” The specification is replete with terms which are not clear, concise and exact. The specification should be revised carefully in order to comply with 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112. Examples of some unclear, inexact or verbose terms used in the specification are: Paragraph [0054] states that thickness H8 is less than thickness H7, while Figure 3 and claim 1 depict the opposite. Additionally, H8 does not correspond to the thickness of either the first (353(3)) or second (353(2)) metal trace in Figure 3; the dotted line instead goes to the second metal surface (353(2)). H7 + D1 is the thickness that is drawn to first metal trace (353(3)) in Figure 3. Corrections are required.
Claim Objections
Claim 43 is objected to because of the following informalities: The claim ends with a semicolon instead of a period. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4, 6-7, 9, 11-13, 16-17, 19, 21 and 43-44 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US-20220084993-A1 – hereinafter Kim) in view of Yim et al. (US-20210257305-A1 – hereinafter Yim).
Regarding claim 1, Kim teaches an integrated circuit (IC) package (Fig.3 2; ¶0063), comprising:
a substrate (Fig.3 2000; ¶0064) comprising a first metallization layer (Fig.3 500; ¶0039), comprising:
an insulating layer (Fig.3 850; ¶0042) comprising a first outer surface (top surface) extending in a horizontal direction and one or more openings that extend to the first outer surface (top surface); and
a metal layer (Fig.3 621-623; ¶0041) comprising a plurality of metal traces (621-623), the plurality of metal traces (621-623) comprising one or more first metal traces (623) embedded in the insulating layer (850) and one or more second metal traces (621) embedded in the insulating layer; (850) and one or more interconnects (Fig.3 808 and 930; ¶0044 and ¶0022);
wherein:
the one or more first metal traces (623) each have a first thickness in a vertical direction;
the one or more second metal traces (621) each have a second thickness in the vertical direction less than the first thickness;
the one or more second metal traces (621) are each disposed in an opening of the one or more openings in the insulating later (850) and each comprise a second metal surface (top surface of 621) recessed in the opening a second distance from the first outer surface (top surface) of the insulating layer (850); and
each interconnect (808) of the one or more interconnects (808 and 930) is disposed in an opening of the one or more openings in the insulating later (850) and coupled to a second metal trace (621) of the one or more second metal traces (621) in the opening.
Kim does not teach wherein the one or more interconnects each comprise a first portion and a second portion;
wherein the first portion of each interconnect of the one or more interconnects is disposed in an opening of the one or more openings in the insulating later; and
wherein the second portion of each interconnect of the one or more interconnects is disposed outside of the opening of the one or more openings.
Yim teaches an IC package (Fig.1A 10; ¶0020 of Yim) with interconnects (Fig.1A 162; ¶0035 of Yim) that protrude into a wiring layer (Fig.1A 200; ¶0020 of Yim) located above the interconnects (162 of Yim).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the interconnects of Kim (808 of Kim) to protrude into upper package substrate (Fig.3 810; ¶0042 of Kim) as taught by Yim (Fig.1A of Yim) to arrive at the claimed invention. This modification is obvious because it is a matter of design choice. The resulting prior art combination teaches interconnects (808 of Kim) that are partially in and partially out of the insulating layer (850 of Kim).
Regarding claim 2, the aforementioned combination of Kim in view of Yim from claim 1 teaches the IC package of claim 1, wherein:
the one or more first metal traces (623) each comprise a first metal surface (top surface of 623) recessed a first distance from the first outer surface (623) of the insulating layer (623).
Regarding claim 3, the aforementioned combination of Kim in view of Yim from claim 2 teaches the IC package of claim 2, wherein:
the first distance is less than the second distance (Fig.3 621 is recessed more than 623).
Regarding claim 4, the aforementioned combination of Kim in view of Yim from claim 2 teaches the IC package of claim 2, wherein:
the first metal surface (top surface) of each of the one or more first metal traces (623) extends to the first outer surface (top surface) of the insulating layer (850).
Regarding claim 6, the aforementioned combination of Kim in view of Yim from claim 1 teaches the IC package of claim 1, wherein the substrate (2000) does not comprise a solder resist layer (Kim makes no mention of a solder resist layer) adjacent to the first metallization layer (500).
Regarding claim 7, the aforementioned combination of Kim in view of Yim from claim 1 teaches the IC package of claim 1, wherein the one or more interconnects (808) are each direct metal bonded (¶0056) to a second metal trace (621) of the one or more second metal traces (621).
Regarding claim 9, the aforementioned combination of Kim in view of Yim from claim 1 teaches the IC package of claim 1, wherein the substrate (2000) comprises a second metallization layer (Fig.3 400; ¶0039), and further comprising:
a die (Fig.3 700; ¶0022) coupled to the second metallization layer (400); and
wherein:
the one or more interconnects (808) comprise one or more external interconnects (808) each coupled to the second metal trace (621) of the one or more second metal traces (621).
Regarding claim 11, the aforementioned combination of Kim in view of Yim from claim 9 teaches the IC package of claim 9, wherein:
the substrate (2000) comprises a package substrate;
the die (700) comprises a first side (top side) and a second side (bottom side) opposite the first side (top side); and
the first side (top side) of the die is coupled to the second metallization layer (400) of the package substrate (2000); and
further comprising an interposer substrate (Fig.3 1000; ¶0022) adjacent to the second side (bottom side) of the die (700), such that the die (700) is disposed between the package substrate (2000) and the interposer substrate (1000).
Regarding claim 12, the aforementioned combination of Kim in view of Yim from claim 11 teaches the IC package of claim 11, further comprising a plurality of vertical interconnects (Fig.3 930; ¶0022) disposed outside the die (700) in the horizontal direction, wherein:
the interposer substrate (1000) comprises a third metallization layer (Fig.3 300; ¶0023) comprising a plurality of third metal interconnects; and
each vertical interconnect (930) of the plurality of vertical interconnects (930) couples a third metal interconnect (300) of the plurality of third metal interconnects (300), to a second metal interconnect (400) of a plurality of second metal interconnects (400).
Regarding claim 13, the aforementioned combination of Kim in view of Yim from claim 1 teaches the IC package of claim 1, wherein:
the substrate (2000) comprises a package substrate; and
further comprising:
a die (Fig.3 700; ¶0022) comprising a first side (top side) and a second side (bottom side) opposite the first side (top side), the first side (top side) of the die (700) is coupled to the first metallization layer (500) of the package substrate (2000); and
an interposer substrate (Fig.3 1000; ¶0022) adjacent to the second side (top side) of the die (700), such that the die (700) is disposed between the package substrate (2000) and the interposer substrate (1000);
wherein:
the one or more interconnects (808 and 930) comprise a plurality of vertical interconnects (930) disposed outside the die (700) in the horizontal direction;
the interposer substrate (1000) comprises a third metallization layer (Fig.3 300; ¶0023) comprising a plurality of third metal interconnects (300); and
each vertical interconnect (930) of the plurality of vertical interconnects (930) couples a third metal interconnect of the plurality of third metal interconnects (300) in the third metallization layer (300) of the interposer substrate (1000), to the second metal trace (621) of the one or more second metal traces (621).
Regarding claim 16, the aforementioned combination of Kim in view of Yim from claim 1 teaches the IC package of claim 1, further comprising:
a package substrate (Fig.3 1000; ¶0022); and
a die comprising (Fig.3 700; ¶0022) a first side (bottom side) and a second side (top side) opposite the first side (bottom side), wherein the first side (bottom side) of the die (700) is coupled to the package substrate (1000);
wherein the substrate (2000) comprises an interposer substrate adjacent to the second side (top side) of the die (700), such that the die (700) is disposed between the package substrate (1000) and the interposer substrate (2000).
Regarding claim 17, the aforementioned combination of Kim in view of Yim from claim 16 teaches the IC package of claim 16, wherein the one or more interconnects (808 and 930) comprise a plurality of vertical interconnects (930) disposed outside the die (700) in the horizontal direction,
wherein each vertical interconnect (930) of the plurality of vertical interconnects further couples the second metal trace (621) of the one or more second metal traces (621), to the package substrate (1000).
Regarding claim 19, the aforementioned combination of Kim in view of Yim from claim 16 teaches the IC package of claim 16, wherein the one or more interconnects (808 and 930) comprise one or more external interconnects (808) each coupled to the second metal trace (621) of the one or more second metal traces (621).
Regarding claim 21, the aforementioned combination of Kim in view of Yim from claim 19 teaches the IC package of claim 19, wherein the one or more interconnects (808 and 930) comprise a plurality of vertical interconnects (930) disposed outside the die (700) in the horizontal direction,
wherein each vertical interconnect (930) of the plurality of vertical interconnects further couples the second metal trace (621) of the one or more second metal traces (621), to the package substrate (1000).
Regarding claim 43, the aforementioned combination of Kim in view of Yim from claim 1 teaches the IC package of claim 1, further comprising a layer (Fig.3 PK2; ¶0042 of Kim) adjacent to the substrate (2000 of Kim);
wherein the second portion of each interconnect (808 of Kim) of the one or more interconnects is disposed in the layer (PK2 of Kim).
Regarding claim 44, the aforementioned combination of Kim in view of Yim from claim 43 teaches the IC package of claim 43, wherein the layer comprises a package mold (Fig.3 850 top; ¶0042 of Kim).
Claim(s) 22-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yim.
Regarding claim 22, the aforementioned combination of Kim in view of Yim from claim 1 teaches the IC package of claim 1, wherein:
the substrate (2000) comprises a package substrate; and
further comprising:
a first die (Fig.3 700; ¶0022) comprising a first side (top side) and a second side (bottom side) opposite the first side (top side), wherein the first side (top side) of the first die (700) is coupled to the package substrate (2000);
an interposer substrate (Fig.3 1000; ¶0022) adjacent to the second side (bottom side) of the first die (700), such that the first die (700) is disposed between the package substrate (2000) and the interposer substrate (1000); and
a second die (Fig.4L 800; ¶0042) coupled to the interposer substrate (1000).
Kim does not teach wherein the interposer substrate is coupled such that the interposer substrate is disposed between the first die and the second die.
Where the prior art discloses all claimed components and the only difference between the prior art and the claimed invention is how those claimed components are arranged relative to each other, the difference needs to be non-obvious. A different vertical arrangement of the package substrate, the interposer substrate and the second die does not patentably distinguish claim 22 over Kim, because the terms “package substrate” and “interposer substrate” can be broadly interpreted in the art as analogous components.
Regarding claim 23, the aforementioned combination of Kim in view of Yim from claim 1 teaches the IC package of claim 1.
Kim does not explicitly teach wherein the IC package is integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multi copter.
Claim 23 is unpatentable over claim 1 because it is well-known in the art that embodiments similar to the device taught by Kim and including Kim are integrated into the devices listed in claim 23.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yim, and further in view of Kang et al. (US-12021020-B2 – hereinafter Kang).
Regarding claim 8, the aforementioned combination of Kim in view of Yim from claim 1 teaches the IC package of claim 1.
Kim does not teach the IC package further not comprising a solder joint coupling any of the one or more interconnects to the second metal trace of the one or more second metal traces.
Kang teaches a device having interconnects (Fig.1 113; col 4 lines 53-57 of Kang) that are conductive pillars (col 4 line 53-57 of Kang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the conductive pillars of Kang (113 of Kang) as the interconnect of Kim (808 of Kim) to arrive at the claimed invention. A practitioner of ordinary skill would be motivated to make this modification because conductive pillars are one of many viable options for an interconnect structure that is not a solder ball.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yim, and further in view of Yu et al. (US-20220392881-A1 – hereinafter Yu).
Regarding claim 14, the aforementioned combination of Kim in view of Yim from claim 1 teaches the IC package of claim 13, further comprising a plurality of die interconnects (Fig.3 708; ¶0032).
Kim does not teach wherein the die interconnects are coupled to the first side of the die and each coupled to a first metal trace of the one or more first metal traces. To arrive at the claimed invention, the die 700 only needs to be rotated 180 degrees.
Yu teaches an example of a die (Fig.24 50; ¶0017 of Yu) where the die has interconnects on a top side of the die (50 of Yu) instead of a bottom side of the die (50 of Yu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to orient the die of Kim (700 of Kim) in the same manner as the die of Yu (50 of Yu) to arrive at the claimed invention. A practitioner would have been motivated to make this modification as a matter of design choice or in applications such as for bridge dies.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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