DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Continued Examination Under 37 CFR 1.114
5. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/06/2025 has been entered.
Response to Arguments
6. Applicant's arguments filed 10/08/2025 have been fully considered but they are not persuasive. Regarding claims 1 and 9, applicant argues the prior art does not teach the amended limitations, i.e. “wherein the array of interconnect pillars includes conductive pillars separate from solder that are electrically coupled together by solder, wherein the conductive pillars includes more than one pillar height between different lateral regions.”
Referring to Figures 3 and 7 of Huang, Kuan-Yu et al. (Pub No. US 20220013492 A1) (hereinafter, Huang) in the broadest reasonable interpretation of the prior art, the conductive pillars (122/124/126 and 222/224/226; Figs 3 and 7) separated by solder (JC/JA) have varying thicknesses/heights (Thickness; 122T/124T/126T and 222T/224T/226T; Figs 3/7; ¶¶[0026,0031]) according to some embodiments (¶¶[0026, 0031]), thus the conductive pillars may include more than one pillar height between different lateral regions (Lateral distances; LS1/LS2; Fig 7).
The Examiner notes that although the same prior art reference is used in the rejection, the rejection is based on a different embodiment that is not the subject of Applicant's arguments.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1-12 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang, Kuan-Yu et al. (Pub No. US 20220013492 A1) (hereinafter, Huang).
Huang, Fig 5: Embodiment of semiconductor package with stack of die
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Re Claim 1, (Currently Amended) Huang teaches a semiconductor device, comprising:
a first semiconductor die (First package component; 10; Fig 5; ¶[0023]); and
a second semiconductor die (Second package component; 20; Fig 5; ¶[0028]) stacked with the first semiconductor die and electrically connected to the first semiconductor die by an array of interconnect pillars (Conductive bumps; 120/220/120A/220A; Figs 3/5/7; ¶[0041]) coupled to solder joints (Joint structure; JA; Fig 5; ¶[0037]);
wherein the array of interconnect pillars includes conductive pillars (Conductive layers; 222/224/226 and 122/124/126; Figs 3 and 7; ¶¶[0026, 0031]) separate from solder (Joint structure; JA/JC; Figs 5/7; ¶[0037]) that are electrically coupled together by solder, wherein the conductive pillars includes more than one height (Thickness; 122T/124T/126T and 222T/224T/226T; Figs 3/7; ¶¶[0026,0031]) between different lateral regions (Lateral distances; LS1/LS2; Fig 7).
Huang, Fig 3: Joint structure with lower pillars with varying thicknesses
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Huang, Fig 7: Joint structure with upper pillars with varying thicknesses
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Re Claim 2, (Original) Huang teaches the semiconductor device of claim 1, wherein the array of interconnect pillars (Conductive bumps; 120/220/120A/220A; Figs 3/5; ¶[0041]) includes pillars (Corner bump; 1202; Fig 5; ¶[0041]) that are taller (See Standoff SF2; Fig 5; ¶[0040]) adjacent to a periphery (Closer to edges; Fig 5) of the die (First/Second package component; 10/20; Fig 5; ¶[0028]), and shorter (See Standoff SF1; Fig 5; ¶[0040]) at an interior (Around the middle; Fig 5) of the die.
Re Claim 3, (Original) Huang teaches the semiconductor device of claim 1, wherein a pillar height distribution (Conductive bump thickness distribution; Figs 3-4; ¶[0036]; Per ¶[0036] the thickness 128T of conductive bump 120A of first package component 10 of Fig 3 is determined by warpage distribution of Fig 4) is mapped to a known warpage profile (Warpage distribution; Fig 4; ¶¶[0035-0036]) of either the first die (First package component; 10; Figs 3/5; ¶[0023]); or the second die (Second package component; 20; Figs 3/5; ¶[0028]).
Re Claim 4, (Original) Huang teaches the semiconductor device of claim 1, wherein a pillar height distribution (Standoff; SF1/SF2; Fig 5; ¶[0040]; Per ¶[0040] The standoff may vary across the semiconductor package SP1 depending on the warpage distribution) is mapped to a known warpage profile that combines warpage (Per ¶[0040] the vertical distance between the two package components (10 and 20) may vary in different zones due to the warpage) of the first die (First package component; 10; Figs 3/5; ¶[0023]) and warpage of the second die (Second package component; 20; Figs 3/5; ¶[0028]).
Re Claim 5, (Original) Huang teaches the semiconductor device of claim 1, wherein the array of interconnect pillars (Conductive bumps; 120/220/120A/220A; Figs 3/5; ¶[0041]) includes pillars extending down from the first die (First package component; 10; Fig 5; ¶[0023]) and up from the second die (Second package component; 20; Fig 5; ¶[0028]),
and wherein heights (Thickness; 128T; Fig 3; ¶[0047]) of pillars (Conductive bumps; 120; Figs 5/6; ¶[0041]) extending down and heights (Thickness; 228T; Fig 3; ¶[0047]) of pillars (Conductive bumps; 220; Figs 5/6; ¶[0041]) extending up complement each other (Match the warpage distribution; Figs 5/6; ¶[0040]; Per ¶¶[0040, 0047] the standoff SF1/SF2 may vary across the semiconductor package SP1 depending on the warpage distribution. The extent to which the joint structure JB covers the first and second conductive bumps (120 and 220) may be determined by the thicknesses (128T and 228T) of the fourth conductive layers (128A and 228A) shown in FIG. 3).
Re Claim 6, (Original) Huang teaches the semiconductor device of claim 1, wherein the array of interconnect pillars (Conductive bumps; 120/220/120A/220A; Figs 3/5; ¶[0041]) includes copper (Copper included in first/third conductive layers 122/126, which are components of 120; ¶0021]; Per ¶[0030] The materials of the first conductive layer 222, the second conductive layer 224, the third conductive layer 226, and the fourth conductive layer 228A may be respectively the same as or similar to those of the first conductive layer 122, the second conductive layer 124, the third conductive layer 126, and the fourth conductive layer 128A).
Re Claim 7, (Original) Huang teaches the semiconductor device of claim 1, wherein the array of interconnect pillars (Conductive bumps; 120/220/120A/220A; Figs 3/5; ¶[0041]) includes nickel (Nickel included in second conductive layer 124; ¶[0021]) on copper (Copper included in first and third conductive layer 122/126; ¶[0021]).
Re Claim 8, (Original) Huang teaches the semiconductor device of claim 1, wherein the array of interconnect pillars (Conductive bumps; 120/220/120A/220A; Figs 3/5; ¶[0041]) includes solder (Lead-free solder, such as tin, SnAg, tin bismuth (SnBi) solder, copper (SAC) solder included in fourth conductive layer 128A; ¶[0021]).
Re Claim 9, (Currently Amended) Huang teaches a semiconductor device, comprising:
a stack of semiconductor dies (First/Second package component; 10/20; Fig 5; ¶[0028]); and
an array of interconnect pillars (Conductive bumps; 120/220/120A/220A; Figs 3/5; ¶[0041]) coupled to solder joints (Joint structure; JA; Fig 5; ¶[0037]) at interfaces between dies in the stack;
wherein one or more array of interconnect pillars (Conductive bumps; 120/220/120A/220A; Figs 3/5; ¶[0041]) include conductive pillars (Conductive layers; 222/224/226 and 122/124/126; Figs 3 and 7; ¶¶[0026, 0031]) separate from solder (Joint structure; JA/JC; Figs 5/7; ¶[0037]) that are electrically coupled together by solder wherein the conductive pillars include more than one height (Thickness; 122T/124T/126T and 222T/224T/226T; Figs 3/7; ¶¶[0026,0031]) between different lateral regions (Lateral distances; LS1/LS2; Fig 7).
Re Claim 10, (Original) Huang teaches the semiconductor device of claim 9, wherein pillar height (Standoffs; SF1/SF2; Fig 5; ¶[0040]) arrangements are different between at least two different interfaces (Peripheral region and central region; Fig 5; ¶[0039]) between dies (First/Second package component; 10/20; Fig 5; ¶[0028]) in the stack.
Re Claim 11, (Original) Huang teaches the semiconductor device of claim 9, wherein one of the dies (First package component; 10; Fig 5; ¶[0023]) in the stack of semiconductor dies (First/Second package component; 10/20; Fig 5; ¶[0028]) includes a logic die (First package component 10 contains logic circuitry; ¶[0023]).
Re Claim 12, (Original) Huang teaches the semiconductor device of claim 9, wherein one of the dies (Second package component; 25; Figs 21-23; ¶[0095]) in the stack of semiconductor dies (First/second package component; 15/25; Figs 21-23; ¶[0095]) includes a DRAM die (DRAM memory device; ¶[0095]).
Re Claim 14, (Original) Huang teaches the semiconductor device of claim 9, wherein pillars in a single given array of interconnect pillars (Conductive bumps; 120/220/120A/220A; Figs 3/5; ¶[0041]) at a given interface include different diameters (Lateral dimensions; LD1/LD2; Fig 3; ¶[0024]).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Huang, Kuan-Yu et al. (Pub No. US 20220013492 A1) (hereinafter, Huang) as applied to claim 9, and further in view of Hong, Ji-Seok et al. (Pub No. US 20200135698 A1) (hereinafter, Hong).
Re Claim 13, (Original) Huang does not teach the semiconductor device of claim 9, wherein a top die in the stack of semiconductor dies is thicker than middle dies in the stack.
In the same field of endeavor, Hong teaches the semiconductor device of claim 9, wherein a top die (Third component die; 40; Fig 3; ¶[0040]) in the stack of semiconductor dies (Die stack; 50; Fig 3; ¶[0040]) is thicker (Die 40 is thicker than die 20 and 30; ¶[0040]; Per ¶[0040] all component dies of the die stack 50 except for the third component die 40 have a structure identical to base die 10) than middle dies (First/second component dies; 20/30; Fig 3; ¶[0040]) in the stack.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor device as disclosed by Huang by making a top die in the stack of semiconductor dies thicker than middle dies in the stack, as disclosed by Hong. One of ordinary skill in the art would have been motivated to make this modification in order to have a small gap distance between middle die such that there is a greater production yield of die stack structures (Hong, ¶[0005]). Furthermore, the die 40 must be higher such that it is closer to the top of the package mold 300, in order to dissipate heat more efficiently from the top of the die stack structure 90 to a heat sink provided on the upper surface of sealing member 310, as suggested by Hong (¶[0084]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY EDWARD DUREN whose telephone number is (703)756-1426. The examiner can normally be reached 07:30 - 17:00 PST.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817