DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 23, 2026 has been entered.
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on December 17, 2025 was considered by the Examiner.
Response to Arguments
Regarding the rejection under 35 USC 103, Applicant’s amendments and arguments were considered but are largely moot in view of the new grounds of rejection presented herein.
Applicant argues Applicant respectfully submits that Zhao's bottom two layers 201 of 102 are fundamentally different from a laminate substrate comprising a plurality of nonconductive layers with embedded conductive traces.
However, as discussed below, Zhao’s bottom three layers of 201 (i.e., bottom three die assemblies 201) correspond to the claimed laminate substrate, and these three layers comprise a plurality of nonconductive layers of 108 with embedded traces of the redistribution layer 202 in these layers, as further discussed below.
Applicant further argues that Zhao does not teach or disclose at least "an interposer mounted on the laminate substrate by a nonconductive adhesive layer" much less "a plurality of conductive vias extending through both the interposer and the nonconductive adhesive layer and connecting to the laminate substrate" as recited in Claim 1. Rather, as shown in FIGS. 1 and 2 of Zhao, a fifth layer from the bottom of a die assembly 201 (alleged to correspond to an interposer of Claim 1) mounted on the bottom two layers of a die assembly 201 of a dice 102 (alleged to correspond to a laminate substrate of Claim 1) are merely semiconductor dices stacked or adhered on top of each other.
However, FIG. 1 of Zhao shows stacked layers of 201, and each layer 201 is a die assembly; Zhao teaches each of the dice 102 is part of a die assembly 201 including the respective die 102, a rim 108 and a redistribution layer 202 as described herein (and optionally a molding compound 200), [0022]. Accordingly, the stack of die assemblies 201 is not merely a stack of semiconductor dies as alleged by Applicant as each die assembly 201 incudes a respective die 102, a rim 108 and a redistribution layer 202 (and optionally a molding compound 200). FIG. 2 shows a labeled die assembly 201.
Applicant argues Moreover, the vias 112 (alleged to correspond to the conductive vias of Claim 1) merely extend through one or more of the dice 102 (see FIG. 1 and at least paragraph [0020] of Zhao) adjacent to the first and second dies 104, 106 and does not extend through the first and second dies 104, 106. As such, the vias 112 do not extend through both an interposer and a nonconductive adhesive layer much less connect to a laminate substrate comprising a plurality of nonconductive layers with embedded conductive traces.
However, a die assembly 201 (not die 104 or die 106 as alleged by Applicant) is considered to correspond to the claimed interposer. In FIG. 1, the adhesive layer 204 is between adjacent die assemblies 201, [0026]. The vias 112 are shown extending through each of the die assemblies 201 in FIG. 1 (they are shown extending through the rims 108 of each die assembly 201). FIG. 2 shows the righthand via 112 extending through the adhesive layer 204 between rims 108. Likewise, FIG. 1 shows the lefthand via 112 extending through the adhesive layer 204 between rims 108, though the adhesive layer 204 is not labeled in FIG. 1. The bottom three layers 201 (i.e., bottom three die assemblies 201) in FIG. 1 correspond to the claimed laminate substrate. The sixth layer 201 (i.e., sixth die assembly 201) from the bottom in FIG. 1 corresponds to the claimed interposer. The vias 112 are shown extending through each 201.
Applicant argues Thus, Applicant respectfully submits that the non-conducting organic adhesive of Delgado fails to teach or disclose at least "an interposer mounted on the laminate substrate by a nonconductive adhesive layer" as recited in Claim 1.
However, Applicant is arguing references individually and not the combination. Zhao teaches an interposer mounted on the laminate substrate by an adhesive layer as recited in Claim 1; Delgado teaches the nonconductive adhesive layer. In combination, Zhao and Delgado teach "an interposer mounted on the laminate substrate by a nonconductive adhesive layer" as recited in Claim 1.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, from claim 4 the feature “an additional RDL between the interposer and the nonconductive adhesive layer” must be shown or the feature(s) canceled from the claim(s).
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, 9-10, 18, 20-21, is/are rejected under 35 U.S.C. 103 as being unpatentable over US20150325550A1 to Zhao (hereinafter “Zhao”) in view of US 20070235810 A1 to Delgado et al. (hereinafter “Delgado”).
RE: Claim 1, Zhao discloses A stacked structure (100 in FIGs. 1-2), comprising:
a laminate substrate (bottom three layers 201 of 102; “laminate” is not defined in the instant specification; “laminate” is defined by Merriam-Webster’s dictionary as “consisting of laminae,” see definition 1 for the adjective “laminate” provided by Merriam-Webster available at <https://www.merriam-webster.com/dictionary/laminate> and “lamina” is defined as “a thin plate or scale : layer”, see <https://www.merriam-webster.com/dictionary/laminae>; the term laminae is the plural form of lamina; accordingly, a laminate substrate is a substrate consisting of multiple lamina and the bottom three layers 201 in FIG. 1 therefore correspond to the claimed laminate substrate) comprising a plurality of nonconductive layers (plurality of layers 108 in the bottom three layers 201 in FIG. 1; 108 is constructed of dielectric molding compound, [0019]) with embedded conductive traces (traces of redistribution layer 202 in the bottom three layers 201, [0024], [0032], [0044]; 202 is housed within the rims 108, [0024], accordingly, the traces of 202 are embedded within the rims 108; each of the die assemblies 201 includes a die 102 as well as a redistribution layer 202 formed adjacent to the die 102, [0024]; each of the dice 102 is part of a die assembly 201 including the respective die 102, a rim 108 and a redistribution layer 202 as described herein (and optionally a molding compound 200), [0022]; redistribution layer 202 thereby provides a “fan-out” configuration that allows for the distributed interconnection of each of the dice 102 with other dice within the semiconductor device 100 as well as the ball grid array 114 (e.g., by way of the vias 112), [0024]);
an interposer (sixth 201 from the bottom in FIG. 1) mounted on the laminate substrate by an adhesive layer (third 204 from the bottom in FIG. 1; Each of the dice 102 is coupled with one another with a layer of an adhesive 204 or other bonding substance provided between each of the die assemblies 201, [0026]),
a plurality of conductive vias (112, [0020]) extending through both the interposer and the adhesive layer and connecting to the laminate substrate (FIG. 1 shows 112 extending through and connecting to each 201 and each 204); and
a redistribution layer (RDL) (fifth 201 or seventh 201 from the bottom in FIG. 1) adjacent to the interposer.
Zhao does not explicitly disclose that adhesive 204 is nonconductive.
In the same field of endeavor, Delgado discloses a semiconductor power device 20 and a semiconductor control device 32 coupled to dielectric layer 14. In one embodiment power device 20 and semiconductor control device 32 are coupled with a non-conducting organic adhesive 11, such as a polymer adhesive for example, and without solder or conductive polymers, [0019].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use non-conducting adhesive material as taught by Delgado for the adhesive 204 in Zhao to prevent short-circuiting.
RE: Claim 2, modified Zhao discloses The stacked structure of claim 1, wherein the RDL is on the interposer (the seventh 201 from the bottom is on the sixth 201 from the bottom in FIG. 1).
RE: Claim 3, modified Zhao discloses The stacked structure of claim 1, wherein the RDL is between the interposer and the nonconductive adhesive layer (the fifth 201 from the bottom in FIG. 1 is between the sixth 201 and third 204 from the bottom).
RE: Claim 4, modified Zhao discloses The stacked structure of claim 2, further comprising an additional RDL (fourth 201 from the bottom in FIG. 1) between the interposer and the nonconductive adhesive layer (the fourth 201 from the bottom in FIG. 1 is between the sixth 201 and third 204 from the bottom).
RE: Claim 5, modified Zhao discloses The stacked structure of claim 1, wherein the plurality of conductive vias extend through the redistribution layer (vias in at least some examples are provided through the silicon of the dice 102, [0029]; the redistribution layer 202 extends beyond the footprint (e.g., the lateral footprint of the die 102) and extends into the rim 108, [0024]; plurality of vias 112 are formed through the rims 108, [0020]; FIG. 1 shows vias 112 extending through each 201).
RE: Claim 6, modified Zhao discloses The stacked structure of claim 1, wherein the interposer comprises a nonconductive material formed of glass, semiconductor and/or ceramic (a plurality of dice 302 are shown in a monolithic semiconductor wafer 300. For instance, the plurality of dice 302 are formed in a silicon wafer as is previously known (by way of masking and etching of the wafer), [0030]; see FIG. 3 which shows 302 are used to form the dice 102 in FIG. 1; accordingly, each 201 includes silicon which is a semiconductor; the instant application states The interposer 101 can include a nonconductive material formed of glass, a semiconductor material (e.g., silicon, GaAs, InP, etc.), [0014]; accordingly, under a broad reasonable interpretation in light of the specification, silicon is considered a nonconductive material).
RE: Claim 7, modified Zhao discloses The stacked structure of claim 1, wherein the redistribution layer is integrated with the interposer by an intervening adhesive (204 between the sixth 201 and the seventh 201 from the bottom in FIG. 1).
RE: Claim 20, modified Zhao discloses The stacked structure of claim 1, wherein the laminate substrate comprises a plurality of contact pads (114 which includes 116, [0021]) connected to the plurality of conductive vias (each of the dice 102 as well as external circuitry including, but not limited to, a ball grid array 114, a land grid array, a pin grid array or the like positioned along a surface of the semiconductor device 100, [0020]; the first die 104 (e.g., the redistribution layer of the first die 104 described herein) is directly coupled with the solder balls 116, [0021]; The conductive traces formed along the redistribution layer are configured for coupling with the vias 112, [0021]).
RE: Claim 21, modified Zhao discloses The stacked structure of claim 1, wherein the interposer has a smaller footprint than that of the laminate substrate (FIG. 1 shows a first vertical footprint of the sixth 201 from the bottom is smaller than a second vertical footprint of the bottom three layers in FIG. 1; the word “footprint” is not defined in the instant specification; the word “footprint” is defined as “the shape and size of the area something occupies,” see definition 2 by Dictionary.com; Accordingly, under a broad reasonable interpretation, the first vertical footprint would correspond to the vertical area occupied by the sixth layer 201 which is perpendicular to the horizontal direction in FIG. 1; the second vertical footprint would correspond to the vertical area occupied by the bottom three layers 201 which is perpendicular to the horizontal direction in FIG. 1).
RE: Claim 9, Zhao discloses A stacked structure (100 in FIGs. 1-2) comprising:
a laminate substrate (bottom three layers 201 of 102; “laminate” is not defined in the instant specification; “laminate” is defined by Merriam-Webster’s dictionary as “consisting of laminae,” see definition 1 for the adjective “laminate” provided by Merriam-Webster available at <https://www.merriam-webster.com/dictionary/laminate> and “lamina” is defined as “a thin plate or scale : layer”, see <https://www.merriam-webster.com/dictionary/laminae>; the term laminae is the plural form of lamina; accordingly, a laminate substrate is a substrate consisting of multiple lamina and the bottom three layers 201 in FIG. 1 therefore correspond to the claimed laminate substrate) comprising a plurality of nonconductive layers (plurality of layers 108 in the bottom three layers 201 in FIG. 1; 108 is constructed of dielectric molding compound, [0019]) with embedded conductive traces (traces of redistribution layer 202 in the bottom three layers 201, [0024], [0032], [0044]; 202 is housed within the rims 108, [0024], accordingly, the traces of 202 are embedded within the rims 108; each of the die assemblies 201 includes a die 102 as well as a redistribution layer 202 formed adjacent to the die 102, [0024]; each of the dice 102 is part of a die assembly 201 including the respective die 102, a rim 108 and a redistribution layer 202 as described herein (and optionally a molding compound 200), [0022]; redistribution layer 202 thereby provides a “fan-out” configuration that allows for the distributed interconnection of each of the dice 102 with other dice within the semiconductor device 100 as well as the ball grid array 114 (e.g., by way of the vias 112), [0024]); and
at least two interposers (fourth and fifth 201 from the bottom in FIG. 1) arranged on a side of the laminate substrate (fourth and fifth 201 are on a top side of the bottom three layers 201 in FIG. 1),
wherein each of the at least two interposers are integrated with the laminate substrate by one or more adhesive layers (204 between the bottom three layers 201 and the fourth 201 from the bottom in FIG. 1, and/or 204 between the fourth and fifth 201 from the bottom in FIG. 1; Each of the dice 102 is coupled with one another with a layer of an adhesive 204 or other bonding substance provided between each of the die assemblies 201, [0026]).
Zhao does not explicitly disclose that adhesive 204 is nonconductive.
In the same field of endeavor, Delgado discloses a semiconductor power device 20 and a semiconductor control device 32 coupled to dielectric layer 14. In one embodiment power device 20 and semiconductor control device 32 are coupled with a non-conducting organic adhesive 11, such as a polymer adhesive for example, and without solder or conductive polymers, [0019].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use non-conducting adhesive material as taught by Delgado for the adhesive 204 in Zhao to prevent short-circuiting.
RE: Claim 10, modified Zhao The stacked structure of claim 9, wherein each of the at least two interposers comprises a respective plurality of through interposer conductive vias formed in a nonconductive material (the vias 112 are formed separately in each of the die assemblies 201 prior to stacking of the die assemblies in the configuration shown in FIG. 2. Accordingly, the vias 112 are aligned during the stacking procedure to accordingly ensure communication between each of the die assemblies 201 (and the ball grid array 114), [0027]; FIG. 1 shows vias 112 extending through 108 which is dielectric, [0019]).
RE: Claim 18, Zhao discloses A stacked structure (100 in FIGs. 1-2), comprising:
a laminate substrate (bottom three layers 201 of 102; “laminate” is not defined in the instant specification; “laminate” is defined by Merriam-Webster’s dictionary as “consisting of laminae,” see definition 1 for the adjective “laminate” provided by Merriam-Webster available at <https://www.merriam-webster.com/dictionary/laminate> and “lamina” is defined as “a thin plate or scale : layer”, see <https://www.merriam-webster.com/dictionary/laminae>; the term laminae is the plural form of lamina; accordingly, a laminate substrate is a substrate consisting of multiple lamina and the bottom three layers 201 in FIG. 1 therefore correspond to the claimed laminate substrate) comprising a plurality of nonconductive layers (plurality of layers 108 in the bottom three layers 201 in FIG. 1; 108 is constructed of dielectric molding compound, [0019]) with embedded conductive traces (traces of redistribution layer 202 in the bottom three layers 201, [0024], [0032], [0044]; 202 is housed within the rims 108, [0024], accordingly, the traces of 202 are embedded within the rims 108; each of the die assemblies 201 includes a die 102 as well as a redistribution layer 202 formed adjacent to the die 102, [0024]; each of the dice 102 is part of a die assembly 201 including the respective die 102, a rim 108 and a redistribution layer 202 as described herein (and optionally a molding compound 200), [0022]; redistribution layer 202 thereby provides a “fan-out” configuration that allows for the distributed interconnection of each of the dice 102 with other dice within the semiconductor device 100 as well as the ball grid array 114 (e.g., by way of the vias 112), [0024]);
a substrate (fourth 201 from the bottom in FIG. 1) mounted on the laminate substrate (Each of the dice 102 is coupled with one another with a layer of an adhesive 204 between each of the die assemblies 201, [0026]); and
a redistribution layer (RDL) (fifth 201 from the bottom in FIG. 1) on a side of the substrate opposite the laminate substrate (the fifth 201 from the bottom in FIG. 1 is on a top side of the fourth 201 opposite the bottom three layers 201 which are on the bottom side of the fourth 201),
a plurality of conductive vias (112, [0020]) extending through both the substrate and the RDL and connecting to the laminate substrate (FIG. 1 shows 112 extending through each layer 201 and connecting to each layer 201; the redistribution layer 202 extends beyond the footprint (e.g., the lateral footprint of the die 102) and extends into the rim 108, [0024]; plurality of vias 112 are formed through the rims 108, [0020]).
Zhao does not explicitly disclose that adhesive 204 is without solder.
In the same field of endeavor, Delgado discloses a semiconductor power device 20 and a semiconductor control device 32 coupled to dielectric layer 14. In one embodiment power device 20 and semiconductor control device 32 are coupled with a non-conducting organic adhesive 11, such as a polymer adhesive for example, and without solder or conductive polymers, [0019].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use non-conducting adhesive material without solder as taught by Delgado for the adhesive 204 in Zhao to prevent short-circuiting.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao in view of Delgado as applied to claim 1 above, and further in view of
U.S. 2019/0181107A1 to Delacruz et al. (hereinafter “Delacruz”).
RE: Claim 8, modified Zhao does not explicitly disclose The stacked structure of claim 1, wherein the redistribution layer is directly bonded to the interposer without an intervening adhesive.
However, Zhao discloses an adhesive 204 or other bonding substance is provided between each of the die assemblies 201, [0026].
In the same field of endeavor, Delacruz discloses the substrate 102 can represent the top insulating layer of a microelectronic component comprised of a base layer (of active semiconductor, e.g., silicon, or the like), [0020].
Delacruz further discloses the bonding surface 204 of the second substrate 206 is insulating material, [0027].
Delacruz further discloses the substrates 102 and 206 may be direct bonded, including using a hybrid bonding technique, without using intervening materials such as adhesives. The surfaces 106 and 204 of the substrates 102 and 206, respectively, are bonded via direct bonding (e.g., via Zibond™), dielectric to dielectric at room temperature without the use of the adhesive, [0023].
Delacruz further discloses the process includes reducing a capacitive coupling between the first and second microelectronic elements with the first recessed portion and between the third and fourth microelectronic elements with the second recessed portion, [0058] and that insulating material 902 between interconnect 904 locations of the first substrate 102 and/or the second substrate 206 can be removed or recessed to reduce capacitive coupling between the interconnects 904, [0045] and that the process includes forming a first recessed portion (such as recess 202, for example) in the first surface of the second substrate, [0050], see FIG. 2.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide insulating material in the sixth and seventh layers 201 in Zhao and directly bond them together without adhesives as taught by Delacruz in order to avoid using adhesive material which would save in material costs while still providing insulation between the sixth and seventh layers 201 in Zhao and/or to reduce the capacitive coupling between the sixth and seventh layers 201.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao in view of Delgado as applied to claim 1 above, and further in view of US 20190131256 A1 to Liao et al. (hereinafter “Liao”).
RE: Claim 19, modified Zhao does not explicitly disclose The stacked structure of claim 1, wherein the interposer is formed of a base material different from that of the laminate substrate.
However, Zhao discloses the molding compound 200 (e.g., a dielectric resin that forms a corresponding polymer) is provided laterally and over top of the plurality of dice 102, [0025].
In the same field of endeavor, Liao discloses A dielectric material 152 is formed over the RDL 120 of the wafer 131 and surrounds the dies 130, 133, [0051] and that The dielectric material 152 may be a molding compound resin such as polyimide, polyphenylene sulphide (PPS), polyether ether ketone (PEEK), polyethersulfone (PES), a heat resistant crystal resin, or combinations thereof, [0052].
Accordingly, before the effective filing date of the claimed invention, there was a need to select a molding material for each of the bottom three layers 201 and for the sixth 201 from the bottom in FIG. 1 in Zhao.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use polyphenylene sulphide (PPS) for the molding compound in the bottom three layers 201 as this would have been obvious to try since polyphenylene sulphide (PPS) is one solution for dielectric molding compound material identified by Liao and this would have had a reasonable expectation of success, see MPEP 2143.
It would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use polyether ether ketone (PEEK) for the molding compound in the sixth 201 from the bottom in FIG. 1 as this would have been obvious to try since polyether ether ketone (PEEK) is one solution for dielectric molding compound material identified by Liao and this would have had a reasonable expectation of success, see MPEP 2143.
As a result, the molding compound 200 of the bottom three layers 201 and the molding compound 200 of the sixth 201 from the bottom in FIG. 1 of Zhao would be made of different materials. As “base material” is not defined in the instant specification, each molding compound 200 is considered a base material as each molding compound 200 in Zhao is located at a bottommost edge of each die assembly 201 and therefore functions as a base.
Conclusion
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights