Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/11/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uenaka (Pub. No.: US 2011/0169071) in view of WANG (Pub. No.: US 2023/0068091) and further in view of ZHANG (Pub. No.: US 2023/0282280).
Re claim 1, Uenaka teaches a microelectronic device comprising:
a stack structure comprising blocks separated from one another by dielectric slot structures and each including a vertically alternating sequence of conductive structures (71a to 71d, FIG. 4, ¶ [0069]) and insulative structures (72a to 72d) arranged in tiers, at least one of the blocks comprising a stadium structure comprising opposing staircase structures each having steps comprising edges of the tiers; and
a filled trench vertically overlying and within horizontal boundaries of the stadium structure of the at least one of the blocks, the filled trench comprising:
a dielectric liner material (82a) on the opposing staircase structures of the stadium structure and on inner sidewalls of two bridge regions;
at least one dielectric structure (82b) on the dielectric liner material (82a), the at least one dielectric structure horizontally overlapping the steps of the stadium structure; and
a dielectric fill material (56) vertically overlying the dielectric structure, the dielectric fill material positioned within the vertical and horizontal boundaries of the stadium structure.
Uenaka fails to teach at least one dielectric structure doped with one or more of carbon and boron; and having a thickness within a range of from about 10 nm to about 100 nm.
WANG teaches at least one dielectric structure doped with one or more of carbon and boron (506, FIG. 5, [0055]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of increasing the bit density and reduce the bit cost of the flash memory devices as taught by WANG, [0002].
Moreover, Uenaka/WANG fails to teach one dielectric structure having a thickness within a range of from about 10 nm to about 100 nm.
ZHANG teaches one dielectric structure having a thickness within a range of from about 10 nm to about 100 nm (866, FIG. 8A, note that “In some embodiments, the thickness of the staircase step 866 is a thickness of one pair of the first dielectric layer 452 and the second dielectric layer 454”, [0153] and “first dielectric layers 452 can have the same thickness or different thicknesses, which can be in a range between 10 nm to 500 nm”, [0092]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of precise alignment between the channel holes, gate line slits, word line (staircase) contacts, bit line contacts, dummy channel holes as taught by ZHANG, [0004].
Re claim 2, WANG differs from the claim invention by not disclosing wherein the at least one dielectric structure has a concentration of the one or more of carbon and boron within a range of from about 0.5 atomic% to about 20 atomic%.
However, Applicant has not disclosed that the ranges are for particular unobvious purpose, produce an unexpected result, or are otherwise critical. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to include the above said teaching, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997).
Re claim 3, in the combination, WANG teaches the microelectronic device of claim 1, wherein the at least one dielectric structure has a substantially uniform distribution of the one or more of carbon and boron throughout the thickness thereof (506, FIG. 5, [0055]).
Re claim 4, in the combination, Uenaka, FIG. 4 teaches the microelectronic device of claim 1, wherein the at least one dielectric structure (56/82b) has a greater concentration of the one or more of carbon and boron proximate an upper surface (56) thereof than proximate a lower surface thereof (none exist in 82a).
Re claim 5, in the combination, Uenaka, FIG. 19 teaches the microelectronic device of claim 1, wherein the at least one dielectric structure comprises only one dielectric structure (56) substantially continuously extending over horizontal areas of all of the steps of the stadium structure (94a/94b).
Re claim 6, in the combination, Uenaka, FIG. 19 teaches the microelectronic device of claim 1, wherein the dielectric structure comprises multiple dielectric structures (56/94b) that are discrete from one another over the dielectric liner material (94a).
Re claim 7, in the combination, Uenaka, FIG. 19 teaches the microelectronic device of claim 6, wherein the each of the multiple dielectric structures (56/94b) is individually substantially confined within a horizontal area of one of the steps of the stadium structure.
Re claim 8, in the combination, WANG teaches the microelectronic device of claim 1, wherein the at least one dielectric structure comprises carbon-doped silicon nitride (406, FIG. 4, ¶ [0054]).
Re claim 9, in the combination, Uenaka, FIG. 4 teaches the microelectronic device of claim 1, wherein the at least one of the blocks further comprises:
two crest regions, the stadium structure interposed between the two crest regions (left via right) in a first horizontal direction; and
two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with upper surfaces of the two crest regions.
Claim(s) 18-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uenaka in view of WANG
Re claim 18, Uenaka, FIGS 4 and 19 teaches a memory device, comprising:
a stack structure comprising tiers each comprising conductive material (71a to 71d) and insulative material (72a to 72d) vertically neighboring the conductive material:
a stadium structure comprising staircase structures individually having steps comprising horizontal ends of at least some the tiers of the stack structure;
a dielectric liner material (82a) on surfaces of the stadium structure;
dielectric structures (82b) on the dielectric liner material and substantially confined within horizontal boundaries of the steps of the stadium structure, the dielectric structures each comprising a dielectric nitride material [0091] and having a horizontal area (the area form right at the center of the bottom-most surface) less than that of the steps of the stadium structure (occupied by the steps);
a dielectric fill material (56) over the dielectric structures and the dielectric liner material, the dielectric fill material positioned within the vertical and horizontal boundaries of the stadium structure; and
strings of memory cells (AR1/30, [0029]/[0038]) vertically extending through a portion of the stack structure horizontally neighboring the stadium structure.
Uenaka fails to teach the dielectric structures each comprising a dielectric nitride material doped with one or more of carbon and boron.
Uenaka fails to teach at least one dielectric structure doped with one or more of carbon and boron.
WANG teaches at least one dielectric structure doped with one or more of carbon and boron (506, FIG. 5, [0055]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of increasing the bit density and reduce the bit cost of the flash memory devices as taught by WANG, [0002].
Re claim 19, in the combination, WANG teaches the microelectronic device of claim 18, wherein the at least one dielectric structure comprises carbon-doped silicon nitride (406, FIG. 4, ¶ [0054]).
Re claim 20, WANG differs from the claim invention by not disclosing wherein the at least one dielectric structure has a concentration of the one or more of carbon and boron within a range of from about 0.5 atomic% to about 20 atomic%.
However, Applicant has not disclosed that the ranges are for particular unobvious purpose, produce an unexpected result, or are otherwise critical. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to include the above said teaching, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997).
Re claim 21, in the combination, Uenaka, FIG. 4 teaches the memory device of claim 18, wherein each of the dielectric structures (56/82b) has a relatively greater atomic concentration of the one or more of carbon and boron proximate an upper boundary (56) thereof than proximate a lower boundary thereof (none exists in 82b).
Re claim 22, in the combination, WANG teaches the memory device of claim 18, wherein each of the dielectric structures (406/408) has a relatively greater atomic concentration of the one or more of carbon and boron proximate a lower boundary (406, FIG. 4) thereof than proximate an upper boundary thereof (408).
Re claim 23, Uenaka, FIG. 19/4 teaches an electronic system, comprising:
an input device (peripheral circuit);
an output device (display etc.);
a processor device (of FIG. 4) operably coupled to the input device and the output device; and a memory device [0005] operably coupled to the processor device and comprising at least one microelectronic device structure comprising:
a stack structure having a vertically alternating sequence of conductive material (71a to 71d) and insulative material (72a to 72d) arranged in tiers, the stack structure comprising at least two blocks separated from one another by at least one dielectric structure, each of the at least two blocks comprising:
a stadium structure (of FIG. 19) comprising opposing staircase structures individually having steps comprising horizontal ends of at least some of the tiers of the stack structure; a dielectric liner material (82a) on surfaces of the stadium structure;
at least one dielectric landing structure (82b) on the dielectric liner material (82a), the at least one dielectric landing structure having a first thickness (82b) and horizontally overlapping the steps of the opposing staircase structures of the stadium structure; and
a dielectric fill material (56) over the dielectric structure and the dielectric liner material the dielectric fill material exhibiting a substantially planar upper vertical boundary, and a substantially non-planar lower vertical boundary complementary to a topography thereunder, the dielectric fill material (56) having minimum thickness greater than the first thickness of the at least one dielectric landing structure (82b).
Uenaka fails to teach at least one dielectric structure doped with one or more of carbon and boron.
WANG teaches at least one dielectric structure doped with one or more of carbon and boron (506, FIG. 5, [0055]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of increasing the bit density and reduce the bit cost of the flash memory devices as taught by WANG, [0002].
Re claim 24, in the combination, Uenaka, FIG. 19 teaches the electronic system of claim 23, wherein the at least one dielectric landing structure comprises a single dielectric landing structure (56) substantially continuously extending across all of the steps of the opposing staircase structures of the stadium structure.
Re claim 25, in the combination, Uenaka, FIG. 4 teaches the electronic system of claim 23, wherein the at least one dielectric landing structure (56) comprises multiple dielectric landing structures discrete from one another (by contact plugs 53a to 53d & 54a to 54b), each of the multiple dielectric landing structures individually substantially confined within a horizontal area of one of the steps of the opposing staircase structures of the stadium structure.
Re claim 26, in the combination, WANG teaches the electronic system of claim 23, wherein the at least one dielectric landing structure (506) has a non-uniform concentration (cut by 510a-c of FIG. 5) of the one or more of carbon and boron across the first thickness of the at least one dielectric landing structure.
Response to Arguments
Applicant's arguments with respect to claims 1, 18 and 23 on the remarks filed on 02/11/2026 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TONY TRAN/Primary Examiner, Art Unit 2893