DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claims 1 and 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2023/0095134), Lee (US 2021/0225708), and How (US 2015/0243639).
With regard to claim 1, fig. 23 of Chen discloses a microelectronic assembly 50, comprising: a first layer (layer between bottom of 18 and bottom of 28) comprising a plurality of first IC dies (105a, 105b) in an organic dielectric material (“epoxy”, par[0061]), the first layer (layer between bottom of 18 and bottom of 28) having a first side (bottom of 18) and a second side opposite (bottom of 28) to the first side (bottom of 18); a second layer (layer between bottom of 24 and top of 18) on the first side (bottom of 18) of the first layer (layer between bottom of 18 and bottom of 28), the second layer (layer between bottom of 24 and top of 18) comprising a second IC die 405 in the organic dielectric material 22, the second IC die 405 conductively coupling a pair of first IC dies (105a, 105b) in the plurality of first IC dies (105a, 105b) of the first layer (layer between bottom of 18 and bottom of 28); and a package substrate (“substrate package”, par [0080]) coupled to the second side (bottom of 14) of the first layer (layer between bottom of 18 and bottom of 28), wherein: the second IC die 405 is coupled to the pair of first IC dies (105a, 105b) by interconnects 454b and the pair of first IC dies (105a, 105b) comprises through-substrate vias (TSVs) 116 conductively coupling active circuit elements 122 in the first IC dies (105a, 105b) with the interconnects 454b.
Chen does not disclose Interconnects having a pitch less than 60 micrometers between adjacent interconnects, wherein portions of the TSVs are between the active circuit elements in the first IC dies.
However, Lee discloses Interconnects (“micro metal bonds”, par [0024]) having a pitch less than 60 micrometers (“between 1 and 10 micrometers”, par [0024]) between adjacent interconnects (“micro metal bonds”, par [0024]).
Lee does not disclose wherein portions of the TSVs are between the active circuit elements in the first IC dies.
However, fig. 2 of How discloses wherein portions of the TSVs 103 are between the active circuit elements (“active circuits”, par [0009]) in the first IC dies 100.
Therefore, it would have been obvious to one of ordinary skill in the art to form the bond pads on the bridge die of Chen with the pitch of 10 micrometers as taught in Lee in order to provide pitch reduction and facilitate high packaging density. See par [0024] of Lee.
It would have been obvious to one of ordinary skill in the art to form the TSV of Chen surround by active devices as taught in How in order to provide a high density of active circuits within the semiconductor substrate of the die. See par [0009] of How.
With regard to claim 2, fig. 23 of Chen discloses that the organic dielectric material is an epoxy material (“epoxy”, par [0061]).
With regard to claim 3, fig. 23 of Chen discloses that the organic dielectric material (“epoxy”, par [0061]) is a first organic dielectric material (“epoxy”, par[0061]), the first layer (layer between bottom of 18 and bottom of 28) further comprises a redistribution layer (RDL) 28 between the plurality of first IC dies (105a, 105b) and the second side (bottom of 28), and the RDL 28 comprises a plurality of layers of conductive traces 30 and a second organic dielectric material (“passivation layer 28 may also be formed of polyimide”, par [0078]).
With regard to claim 4, fig. 23 and 30 of Chen discloses that the second layer (layer between bottom of 24 and top of 18) comprises a plurality of second IC dies 405, a subset of the plurality of second IC dies (top SB in fig. 30) couples the pair of first IC dies (top 105 in fig. 30), and other subsets of the plurality of second IC dies (bottom SB in fig. 30) couple other pairs of first IC dies (bottom 105 in fig. 30) in the first layer (layer between bottom of 18 and bottom of 28).
With regard to claim 5, Chen does not disclose that the interconnects comprise micro-bumps including solder caps conductively and mechanically coupled to copper pads.
However, fig. 5A of Lee discloses that the interconnects 34 comprise micro-bumps (“micro-bumps or micro-pads 34a”, par [0174]) including solder caps 33 conductively and mechanically coupled to copper pads (“copper layer 32”, par [0191]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the bond pads on the bridge die of Chen with the micro-bumps as taught in Lee in order to provide a fine-line interconnection bridge. See par [0173] of Lee.
With regard to claim 6, Chen does not disclose that the micro-bumps have approximately 25 micrometers to 60 micrometers pitch, between adjacent micro-bumps.
However, fig. 5A of Lee discloses that the micro-bumps 34a have approximately 25 micrometers to 60 micrometers pitch (“micro-pads 34a in the section or region may be smaller than 50, 40 or 30 micrometers“, par [0174]), between adjacent micro-bumps 34a.
Therefore, it would have been obvious to one of ordinary skill in the art to form the bond pads on the bridge die of Chen with the micro-bumps as taught in Lee in order to provide a fine-line interconnection bridge. See par [0173] of Lee.
With regard to claim 7, figs. 14 and 23 of Chen discloses that the interconnects 454d comprise hybrid bonds (“hybrid bonding”, par [0070]) including metal-to-metal bonds (“direct metal bonding”, par [0070]) and inorganic dielectric to inorganic dielectric bonds (“dielectric bonding”, par [0070]).
With regard to claim 8, Chen does not disclose that the metal-to-metal bonds have less than approximately 10 micrometers pitch between adjacent metal to metal bonds.
However, Lee discloses that the metal-to-metal bonds have less than approximately 10 micrometers pitch (“between 1 and 10 micrometers”, par [0024]) between adjacent metal to metal bonds (“copper-pad-to-copper-pad direct bonding”, par [0024]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the bond pads on the bridge die of Chen with the pitch of 10 micrometers as taught in Lee in order to provide pitch reduction and facilitate high packaging density. See par [0024] of Lee.
With regard to claim 9, fig. 23 of Chen discloses a panel 26 comprising glass (“undoped silicon glass”, par [0076]) coupled to the second layer (layer between bottom of 24 and top of 18) on a side (bottom of 24) of the second layer (layer between bottom of 24 and top of 18) opposite to the first layer (layer between bottom of 18 and bottom of 28).
With regard to claim 10, figs. 23 and 30 of Chen disclose a microelectronic assembly, comprising: a pair of first IC dies (105a, 105b) mutually parallel and separated by a gap (gap between 105); a plurality of second IC dies 405 coupled to the pair of first IC dies 105 by first interconnects 454b, the second IC dies 405 extending across the gap (gap between 105a and 105b), the second IC dies 405 comprising conductive pathways between the first IC dies (105a, 105b); and a package substrate (“substrate package”, par [0080]) coupled to the pair of first IC dies (105a, 105b) by second interconnects 32, wherein: the first IC dies (105a, 105b) are between the second IC die 405 and the package substrate (“substrate package”, par [0080]), the first IC dies (105a, 105b) and the second IC dies 405 are surrounded by a first organic dielectric material (e.g., 106) (22, 13) (“epoxy”, par[0061]), a RDL 28 comprising a second organic dielectric material 28 (“polyimide”, par [0078]) is between the first IC dies 105 and the second interconnects 32, and the first IC dies (105a, 105b) comprise through-substrate vias (TSVs) 116 conductively coupling active circuit elements 122 in the first IC dies (105a, 105b) with the first interconnects 454d.
Chen does not disclose that the first interconnects have a pitch of less than 10 micrometers between adjacent interconnects, wherein portions of the TSVs are between the active circuit elements in the first IC dies.
However, Lee discloses that the first interconnects (“copper-pad-to-copper-pad direct bonding”, par [0024]) have a pitch of less than 10 micrometers (“between 1 and 10 micrometers”, par [0024]) between adjacent interconnects (“copper-pad”, par [0024]).
Lee does not disclose wherein portions of the TSVs are between the active circuit elements in the first IC dies.
However, fig. 2 of How discloses wherein portions of the TSVs 103 are between the active circuit elements (“active circuits”, par [0009]) in the first IC dies 100.
Therefore, it would have been obvious to one of ordinary skill in the art to form the bond pads on the bridge die of Chen with the pitch of 10 micrometers as taught in Lee in order to provide pitch reduction and facilitate high packaging density. See par [0024] of Lee.
It would have been obvious to one of ordinary skill in the art to form the TSV of Chen surround by active devices as taught in How in order to provide a high density of active circuits within the semiconductor substrate of the die. See par [0009] of How.
With regard to claim 11, fig. 23 of Chen discloses that the first organic dielectric material (22, 14) comprises epoxy (“epoxy”, par [0061]), and the second organic 28 dielectric material comprises polyimide (“polyimide”, par [0078]).
With regard to claim 12, figs. 23 and 30 of Chen discloses a glass panel 26 coupled to the plurality of second IC dies 405, wherein the second IC dies 405 are between the glass panel 26 and the first IC dies 105.
With regard to claim 13, fig. 23 of Chen disclose that the first interconnects 454d comprise hybrid bonds (“hybrid bonding”, par [0069]) including metal-to-metal bonds (“metal-to metal direct bonding”, par [0069]) and inorganic dielectric to inorganic dielectric bonds (“dielectric bonding”, par [0069]).
With regard to claim 14, Chen does not discloses that the metal-to-metal bonds have less than approximately 10 micrometers pitch between adjacent metal to meta bonds.
However, Lee discloses that metal-to-metal bonds (“copper-pad-to-copper-pad direct bonding”, par [0024]) have less than approximately 10 micrometers pitch (“between 1 and 10 micrometers”, par [0024]) between adjacent metal to meta bonds (“copper-pad”, par [0024]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the bond pads on the bridge die of Chen with the pitch of 10 micrometers as taught in Lee in order to provide pitch reduction and facilitate high packaging density. See par [0024] of Lee.
With regard to claim 16, figs. 3 and 23 of Chen discloses that each of the first IC dies 105 comprises: an interface layer 18 comprising an inorganic dielectric material 18 and conductive bond pads 20b; a substrate 120 having at least one TSV 116; and a metallization stack 130 in contact with the substrate 120, the metallization stack 130 comprising a plurality of layers of another inorganic dielectric material 132, conductive traces 134, and conductive vias 136, wherein: the at least one TSV 116 conductively couples the conductive traces 134 in the metallization stack 130 with one of the conductive bond pads 20b of the interface layer 18, the metallization stack 130 is between the RDL 28 and the substrate 120, the substrate 120 is between the metallization stack 130 and the interface layer 18, and the first interconnects 20b comprise the conductive bond pads 20b of the interface layer 18.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2023/0095134), Lee (US 2021/0225708), How (US 2015/0243639), and Raghunathan (US 2019/0333905).
With regard to claim 15, Chen, Lee, and How do not disclose that the RDL comprises a plurality of layers of the second organic dielectric material, conductive traces and conductive vias.
However, fig. 1a of Raghunathan discloses that the RDL 115 comprises a plurality of layers (“four single-layer RDLs”, par [0043]) of the second organic dielectric material (“polyimide”, par [0043]), conductive traces (“conductive traces”, par [0043]) and conductive vias (“conductive vias”, par [0043]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the passivation layer of Chen with the RDL as taught in Raghunathan in order to provide a fan-out redistribution layer. See par [0040] of Raghunathan.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/Primary Examiner, Art Unit 2893
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