DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Applicant’s response, filed on 08/21/2025, with respect to the rejection(s) of claims 1 under 35 USC § 103 have been fully considered and are persuasive in that the combination of Huang and Dong alone do not read on the amended claim language. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Dong et al. (US20190304986A1) and in further view of C.-H. Huang et al. / Solid-State Electronics 53 (2009) 279–284, (hereinafter, Huang).
The Applicant argues that the Examiner cannot combine the teachings in Dong and Nishikawa because Nishikawa teaches the dipole moments going in opposite directions while the claim and teaching Dong require the dipole moments going in the same direction. The Examiner disagrees. Dong teaches that the blocking layer can be more or fewer than five blocking layers, where layers 1281, 1283 and 1285 can be silicon oxide while layers 1282, 1284 and 1286 are metal oxide (hafnium oxide), (para.44 and 45). Huang’s experimental results disclose, in page 280, column 2, wherein high-k dielectrics, such as Al2O3 or HfO2 are promising candidates to replace conventional nitride charge trapping layers. As such, the structure of the combination of Dong and Nishikawa and Huang are similar to the Applicant’s claimed structure.
Nishikawa requires the dipole moments to be opposite on different sides of the same silicon oxide layer. However, the Examiner continues to aver that Nishikawa and Dong can combined as the resulting structure has dipole moments in the same direction at different locations and at different interfaces and layers within the alternating layered structure. Therefore, as the combination of Nishikawa and Dong and Huang allows for a structure where the dipole moments are in opposite directions on different sides of the same layer (as required by Nishikawa) while being in the same direction at different layers/interfaces within the alternating layer structure(as taught by Dong), Nishikawa, Dong and Huang can be properly combined. As such, the Examiner does not find the Applicant arguments persuasive with respect to the combination of Nishikawa and Dong and continues to rely on them along with the new Huang reference to reject claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 8-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over NISHIKAWA et al. (US20200279866A1) in view of Dong et al. (US20190304986A1) and in further view of C.-H. Huang et al. / Solid-State Electronics 53 (2009) 279–284, (hereinafter, Huang).
Regarding claim 1, Fig.6A of NISHIKAWA memory device, comprising:
an alternating stack of insulating layers 32 (para.0081) and electrically conductive layers 46 (para.0123) arranged along a vertical direction;
a memory opening 149 (para.0083) vertically extending through the alternating stack; and a memory opening fill structure 47L (para.0096) located in the memory opening 149 and comprising a vertical semiconductor channel 60L (para.0095) and a memory film 50L (para.0095),
wherein: the memory film 50L comprises a blocking dielectric film 52L (para.0082), a tunneling dielectric layer 56L (para.0082) and a vertical stack of memory elements 54L (para.0092) located between the blocking dielectric film 52L and the tunneling dielectric layer 56L; and
NISHIKAWA does not disclose wherein the blocking dielectric film comprises component layers which comprise, from a side that is proximal to the vertical stack of memory elements 54L toward a side that is distal from the vertical stack of memory elements 54L, an inner dielectric metal oxide blocking dielectric layer, an inner silicon oxide blocking dielectric layer, a middle dielectric metal oxide blocking dielectric layer, an outer silicon oxide blocking dielectric layer, and an outer dielectric metal oxide blocking dielectric layer,
wherein: a first electric dipole interface is located between the outer silicon oxide blocking dielectric layer and the middle dielectric metal oxide blocking dielectric layer, and has a first dipole moment pointing inward from the outer silicon oxide blocking dielectric layer toward the middle dielectric metal oxide blocking dielectric layer; and
a second electric dipole interface is located between the inner silicon oxide blocking dielectric layer and the inner dielectric metal oxide blocking dielectric layer, and has a second dipole moment pointing inward from the inner silicon oxide blocking toward the inner dielectric metal oxide blocking dielectric layer.
Fig. 4H of Dong teaches 3 layers, that is 1281, 1282, and 1283.
However, in Para 46 after the discussion of a 5 layered blocking layer of Fig. 1H, Dong teaches that the blocking layer can be more or fewer than five blocking layers, where layers 1281, 1283 and 1285 can be silicon oxide while layers 1282 and 1284 are metal oxide (hafnium oxide), (para.44 and 45). So, if the blocking layer were to be increased to 7 layers, it would be expected to have a blocking layer structure 1281,1283, 1285, and 1287, where 1281 1283,1285 and 1287 will be silicon oxide and 1282 1284 and 1286 will be metal oxide.
Thus, a person having ordinary skills in the art will find it obvious to increase the number of blocking layers in Fig. 4H to more than 3 layer and definitely more than 5 layers.
The combination of NISHIKAWA and Dong does teach a first electric dipole interface is located between the outer silicon oxide blocking dielectric layer and the middle dielectric metal oxide blocking dielectric layer, and has a first dipole moment pointing inward from the outer silicon oxide blocking dielectric layer toward the middle dielectric metal oxide blocking dielectric layer; and a second electric dipole interface is located between the inner silicon oxide blocking dielectric layer and the inner dielectric metal oxide blocking dielectric layer, and has a second dipole moment pointing inward from the inner silicon oxide blocking toward the inner dielectric metal oxide blocking dielectric layer.
However, Huang’s experimental results disclose, in page 280, column 2, high-k dielectrics, such as Al2O3 or HfO2 are promising candidates to replace conventional nitride charge trapping layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace Dong’s HfO2 with Huang’s Al2O3 because Al2O3 has better retention characteristics with a low charge loss than Si3N4 and HfO2 films as a storage layer in the oxide-storage dielectrics-oxide structure.
When the aluminum oxide, as taught by Huang, is used instead of hafnium oxide, taught by Dong, the resulting combination of NISHIKAWA, Dong and Huang teaches a blocking layer structure including 7 layers of alternating silicon oxide and aluminum oxide layers. As the combination yields the alternating layers in the same manner as the applicant, the structure yielded by the combination would also results in a first electric dipole interface is located between the outer silicon oxide blocking dielectric layer and the middle dielectric metal oxide blocking dielectric layer, and has a first dipole moment pointing inward from the outer silicon oxide blocking dielectric layer toward the middle dielectric metal oxide blocking dielectric layer; and a second electric dipole interface is located between the inner silicon oxide blocking dielectric layer and the inner dielectric metal oxide blocking dielectric layer, and has a second dipole moment pointing inward from the inner silicon oxide blocking toward the inner dielectric metal oxide blocking dielectric layer. (MPEP2112.01) Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)).
Regarding claim 6, Dong teaches the memory device of Claim 1, wherein the middle dielectric metal oxide blocking dielectric layer 1284 (para.0045) consists essentially of aluminum oxide.
Regarding claim 8, NISHIKAWA further teaches the memory device of Claim 1, wherein the outer dielectric metal oxide blocking dielectric layer 524 (para.0131) consists essentially of aluminum oxide.
Regarding claim 9, Fig. 6A of NISHIKAWA teaches the memory device of Claim 1, wherein the vertical stack of memory elements 54L (para.0092) comprises portions of a charge storage layer that vertically extends continuously through the alternating stack (para.0081).
Regarding claim 10, NISHIKAWA further teaches the memory device of Claim 9, wherein the inner silicon oxide blocking dielectric layer 523 (para.0083) is in contact with an outer sidewall of the charge storage layer.
Regarding claim 11, NISHIKAWA further teaches the memory device of Claim 9, wherein the blocking dielectric film further comprises an inner dielectric metal oxide blocking dielectric layer 522 (para.0087) that contacts an inner sidewall of the inner silicon oxide blocking dielectric layer 523 (para.0083) and an outer sidewall of the charge storage layer 54L (para.0092).
Regarding claim 13, NISHIKAWA teaches the memory device of Claim 11, wherein the inner dielectric metal oxide blocking dielectric layer 522 (para.0087) consists essentially of aluminum oxide.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over NISHIKAWA et al. (US20200279866A1) in view of Dong et al. (US20190304986A1) and and in view of C.-H. Huang et al. / Solid-State Electronics 53 (2009) 279–284, (hereinafter, Huang) and in further view of Kanakamedala et al. (US20180040627A1).
Regarding claim 4, the combination of NISHIKAWA, Dong and Huang teaches all of the elements of the claimed invention as stated above except wherein the middle dielectric metal oxide blocking dielectric layer has a higher atomic density of oxygen atoms than the outer silicon oxide blocking dielectric layer.
Kanakamedala teaches, in para.0052, wherein the composition of the first blocking dielectric portions 522 is modified to include a higher atomic concentration of oxygen atoms during the oxidation process.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first blocking dielectric portions 522 to have a higher atomic concentration of oxygen atoms, as taught by Kanakamedala, because oxidation process can be performed to change the composition of the first blocking dielectric material portions 522 and to form second blocking dielectric material portions 524. (Kanakamedala, [para.0051]).
Regarding claim 5, the combination of Nishikawa, Dong and Huang teaches all of the elements of the claimed invention as stated above except, wherein a surface portion of the middle dielectric metal oxide blocking dielectric layer 1284 (para.0045) that is proximal to the outer silicon oxide blocking dielectric layer 1285 (para.0045) comprises oxygen vacancies at a higher vacancy concentration than a surface portion of the outer silicon oxide blocking dielectric layer 1285 that is proximal to the middle dielectric metal oxide blocking dielectric layer 1284.
Kanakamedala teaches, in para.0052, wherein the composition of the first blocking dielectric portions 522 is modified to include a higher atomic concentration of oxygen atoms during the oxidation process.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first blocking dielectric portions 522 to have a higher atomic concentration of oxygen atoms, as taught by Kanakamedala, because oxidation process can be performed to change the composition of the first blocking dielectric material portions 522 and to form second blocking dielectric material portions 524 (Kanakamedala, [para.0051]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over NISHIKAWA et al. (US20200279866A1) in view of Dong et al. (US20190304986A1) and and in view of C.-H. Huang et al. / Solid-State Electronics 53 (2009) 279–284, (hereinafter, Huang) and in further view of SATO et al. (US20200227439A1).
Regarding claim 7, The combination of Nishikawa, Dong and Huang teaches except wherein the middle dielectric metal oxide blocking dielectric layer has a thickness that is less than one half of a thickness of the inner silicon oxide blocking dielectric layer, and is less than one half of a thickness of the outer silicon oxide blocking dielectric layer.
Fig.6A of SATO teaches, in para.0103, wherein front-side gate dielectric layer 152L can include a single dielectric material layer or a stack of a plurality of dielectric material layers; wherein the continuous front-side gate dielectric layer 152L can include a silicon oxide layer and wherein the continuous front-side gate dielectric layer 152L can additionally include a dielectric metal oxide layer such as an aluminum oxide layer. The thickness of the continuous front-side gate dielectric layer 152L can be in a range from 1 nm to 10 nm, such as from 2 nm to 6 nm. The thickness of the silicon oxide layer can be in the range from 1 nm to 10 nm or greater while the thickness of dielectric metal oxide layer can be in the range from 2 nm to 6 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the front-side gate dielectric layer 152L of SATO in the teachings of Nishikawa, as modified by Dong and Huang, because the continuous front-side gate dielectric layer 152L can be formed by a conformal deposition process such as low pressure chemical vapor deposition or atomic layer deposition.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./ Examiner, Art Unit 2891
/ERIC K ASHBAHIAN/ Primary Examiner, Art Unit 2891