DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending for examination.
Examiner’s Note
The prior art rejection below cites particular paragraphs, columns, and/or line numbers in the references for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/31/2022, 11/25/2023, 11/26/2023, 02/29/2024, 06/20/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1 - 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As to claim 1, the claim recites1. A method, comprising:
generating a tensor-level intermediate representation from a machine learning model using kernel expressions;
partitioning statements of the tensor-level intermediate representation into a first set of statements and a second set of statements;
generating, from the first set of statements, kernel instructions based on a reconfigurable neural engine model, wherein the kernel instructions are executable by a compute tile of a data processing array to implement compute functions of the machine learning model; and
generating, from the second set of statements, microcontroller instructions based on a super-graph model, wherein the microcontroller instructions are executable by a microcontroller of the data processing array to move data into and out from the data processing array.
Step 1: the claim is directed to a process which is one of the statutory categories of invention.
Step 2A:
Prong 1:
The limitations “generating a tensor-level intermediate representation from a machine learning model using kernel expressions;
partitioning statements of the tensor-level intermediate representation into a first set of statements and a second set of statements;
generating, from the first set of statements, kernel instructions based on a reconfigurable neural engine model” and “generating, from the second set of statements, microcontroller instructions based on a super-graph model” are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
Prong 2:
The additional element of “to move data into and out from the data processing array” is mere data gathering which the courts have held to be insignificant extra-solution activity (see MPEP 2106.05(g)).
The additional element of “wherein the kernel instructions are executable by a compute tile of a data processing array to implement compute functions of the machine learning model”; “wherein the microcontroller instructions are executable by a microcontroller of the data processing array” merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
Thus, these additional elements do not integrate the judicial exception into a practical application.
Step 2B:
The additional element of “to move data into and out from the data processing array” merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
The additional element of “wherein the kernel instructions are executable by a compute tile of a data processing array to implement compute functions of the machine learning model”; “wherein the microcontroller instructions are executable by a microcontroller of the data processing array” merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
Accordingly, the additional elements do not amount to significantly more than the abstract idea.
As to claim 2. The method of claim 1, wherein the compute tile is configured to execute a virtual machine, and wherein the virtual machine is configured to execute the kernel instructions to invoke one or more kernels of the compute tile. merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
As to claim 3. The method of claim 1, wherein the microcontroller is configured to execute a virtual machine, and wherein the virtual machine is configured to execute the microcontroller instructions. merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
As to claim 4. The method of claim 1, wherein the reconfigurable neural engine model specifies an instruction format for invoking a plurality of kernels executing in the compute tile. merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
As to claim 5. The method of claim 1, wherein the super-graph model specifies data movement in the data processing array. merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
As to claim 6. The method of claim 1, wherein the partitioning statements of the tensor-level intermediate representation comprises: detecting compute intrinsic calls in the statements of the tensor-level intermediate representation; and including the compute intrinsic calls in the first set of statements are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
As to claim 7. The method of claim 6, wherein the partitioning statements of the tensor-level intermediate representation comprises: detecting, in the tensor-level intermediate representation, loop constructs including a copy operation of data from one memory to another memory; and including the loop constructs in the second set of statements are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
As to claim 8. This is a system claim of claim 1. See rejection for claim 1 above.
Further. The additional element one or more processors merely recites a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
As to claims 9 – 14, see rejection for claims 2 – 7 above.
As to claim 15, this is a computer program product claim of claim 1. See rejection for claim 1 above. Further, additional elements one or more computer-readable storage media, and program instructions collectively stored on the one or more computer-readable storage media, wherein the program instructions are executable by computer hardware to initiate operations merely recites a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
As to claims 15 - 20, see rejection for claims 2 – 7 above.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 – 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 8, limitation “processor configured to initiate” makes it unclear if the system only requires a processor that can initiate the operations recited therewith or if the system also executes these operations. Instead of “configured to initiate”, the claim should be “configured to perform” or something similar.
Conclusion
The prior art made of record but not relied upon request is considered to be pertinent to applicant’s disclosure.
Surendran et al., (US PUB 2022/0343137 hereinafter Surendran), discloses a method for automatically generate a reduced number of compute kernels for performing operations of one or more neural networks (title, abstract and figures 1 – 39).
Hanebutte (US PUB 2023/0004365), discloses a compiler including blocks to identify resources in a hardware to execute low-level instructions generated from high-level code (title, abstract and figures 1 – 5).
Lin et al., (US PUB 2022/0391702 hereinafter Lin), discloses a method of convolution expanding kernel with data tensor in a neural network (title, abstract and figures 1 – 8).
Ansor: Generating High-Performance Tensor Programs for Deep Learning”, 11-2020, pages 1 – 18, discloses a method for obtaining Tensor Programs for Deep Learning in different operators on various hardware platforms (title and abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUONG N HOANG whose telephone number is (571)272-3763. The examiner can normally be reached 9:5-30.
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/PHUONG N HOANG/ Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194