DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 8, 21-22, 24-25, 27-30 and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2020/0135600 A1, hereafter referred to as Chen1) in view of Chen et al. (US 2019/0164925 A1, hereafter referred to as Chen2).
Regarding claim 1, Chen1 teaches a semiconductor package (10), comprising: a routing structure (158; Fig. 8, [0028]); a first die (126A; Fig. 8, [0022]) and a second die (126B; Fig. 8, [0022]) disposed over the routing structure (158; see Fig. 8 upside down); a first array of contact features (the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B) disposed along a first direction (the horizontal direction in Fig. 9B) and electrically coupling the first die (126A) to the routing structure (158; Fig. 9B, [0030]); and a second array of contact features (the second and the fourth rightmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B) disposed along the first direction (the horizontal direction in Fig. 9B) and electrically coupling the second die (126B) to the routing structure (158; Fig. 9B, [0030]), wherein the routing structure (158) comprises a plurality of metal lines (the topmost and the second topmost 162As in Figs. 9A-9B; [0030]) and each of the plurality of metal lines (the topmost and the second topmost 162As in Figs. 9A-9B; [0030]) electrically connects one of the first array of contact features (the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B) and one of the second array of contact features (the second and the fourth rightmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B), wherein the routing structure (158) comprises an interposer (158 can be considered as an interposer, because it is between dies 126 and conductive connectors 176; Fig. 13; [0057]).
Chen1 does not teach wherein each of the plurality of metal lines comprises at least two 90-degree turns on a horizontal plane.
In the same field of endeavor of semiconductor manufacturing, Chen2 teaches wherein each of the plurality of metal lines (312a; Fig. 2A, [0019]) comprises at least two 90-degree turns (right angle turn; [0020]) on a horizontal plane (X-Y plane; Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1 and Chen2, and to further introduce the turning segment of right angel turns into the metal lines of Chen1 as taught by Chen2, because the turning section can improve the tolerance capability of the metal line to the tensile stress resulting from CTS mismatched as taught by Chen2 ([0018]).
Regarding claim 2, Chen1 teaches the semiconductor package of claim 1, wherein each of the plurality of metal lines (the topmost and the second topmost 162As in Figs. 9A-9B; [0030]) comprises a portion (the portion of the metal lines in the gap regions 148; Figs. 9A-9B, [0025]) that is not disposed below the first die (126A) or the second die (126B; see Fig. 8 upside down, [0025]).
Chen1 does not teach wherein the portion forms an acute angle with the first direction.
In the same field of endeavor of semiconductor manufacturing, Chen2 teaches wherein the portion (the portion of the metal lines 312a between dies 110 and 120; Fig. 2A, [0019]) forms an acute angle (the angle θ can be an acute angle; [0020]) with the first direction (the horizontal direction in Fig. 2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1 and Chen2, and to further introduce the turning segment of acute angel turns into the metal lines of Chen1 between the first die and the second die as taught by Chen2, because the turning section can improve the tolerance capability of the metal line to the tensile stress resulting from CTS mismatched as taught by Chen2 ([0018]).
Regarding claim 3, Chen1 teaches the semiconductor package of claim 1, wherein the first array of contact features (the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B) is aligned with the second array of contact features (the second and the fourth rightmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B) along the first direction (the horizontal direction in Fig. 9B).
Regarding claim 8, Chen1 teaches in Fig. 9B, the semiconductor package of claim 1, wherein the first array of contact features (the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B) and the second array of contact features (the second and the fourth rightmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B) directly interface (directly electrically connected to) the plurality of metal lines (the topmost and the second topmost 162As in Figs. 9A-9B; [0030]), wherein the first array of contact features (the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B), wherein the second array of contact features (the second and the fourth rightmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B).
Chen1 does not explicitly teach in Fig. 9B, wherein the first array of contact features comprise first microbumps, wherein the second array of contact features comprise second microbumps.
In the same reference of Chen1, Chen1 teaches in Fig. 13, the contact features (162B, i.e. the via portion of 162 shown in Fig. 8) electrical connected to microbumps (176; Fig. 13, [0057]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Fig. 9A and 13 of Chen1, and to have a microbumps connected to the first array of contact features and the second array of contact features, because the microbumps (176) can provide external connections to the first array of contact features and the second array of contact features as taught by Chen1 (Fig. 17, [0074]).
The combination of Fig. 9B and Fig. 13 of Chen1 teach “wherein the first array of contact features comprise first microbumps, wherein the second array of contact features comprise second microbumps”, because the first microbumps (176s electrically connected to the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B) can be a part of the first array of contact features that the first microbumps is similar to the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B and are conduct features electrically connected to the first die, and the second microbumps (176s electrically connected to the second and the fourth leftmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B) can be a part of the second array of contact features that the second microbumps is similar to the second and the fourth leftmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B and are conduct features electrically connected to the second die.
Regarding claim 21, Chen1 teaches a semiconductor package (10), comprising: a routing structure (158; Fig. 8, [0028]); a first die (126A; Fig. 8, [0022]) and a second die (126B; Fig. 8, [0022]) disposed over the routing structure (158; see Fig. 8 upside down); a first array of contact features (the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B) disposed along a first direction (the horizontal direction in Fig. 9B) and electrically coupling the first die (126A) to the routing structure (158; Fig. 9B, [0030]); and a second array of contact features (the second and the fourth rightmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B) disposed along the first direction (the horizontal direction in Fig. 9B) and electrically coupling the second die (126B) to the routing structure (158; Fig. 9B, [0030]), wherein the routing structure (158) comprises a plurality of metal lines (the topmost and the second topmost 162As in Figs. 9A-9B; [0030]) and each of the plurality of metal lines (the topmost and the second topmost 162As in Figs. 9A-9B; [0030]) electrically connects one of the first array of contact features (the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B) and one of the second array of contact features (the second and the fourth rightmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B), wherein each of the plurality of metal lines (the topmost and the second topmost 162As in Figs. 9A-9B; [0030]) comprises a portion (the portion of the metal lines in the gap regions 148; Figs. 9A-9B, [0025]) that is not disposed below the first die (126A) or the second die (126B; see Fig. 8 upside down, [0025]), wherein the routing structure (158) comprises an interposer (158 can be considered as an interposer, because it is between dies 126 and conductive connectors 176; Fig. 13; [0057]).
Chen1 does not teach wherein the portion forms an acute angle with the first direction.
In the same field of endeavor of semiconductor manufacturing, Chen2 teaches wherein the portion (the portion of the metal lines 312a between dies 110 and 120; Fig. 2A, [0019]) forms an acute angle (the angle θ can be an acute angle; [0020]) with the first direction (the horizontal direction in Fig. 2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1 and Chen2, and to further introduce the turning segment of acute angel turns into the metal lines of Chen1 between the first die and the second die as taught by Chen2, because the turning section can improve the tolerance capability of the metal line to the tensile stress resulting from CTS mismatched as taught by Chen2 ([0018]).
Regarding claim 22, Chen1 teaches the semiconductor package of claim 21, wherein each of the plurality of metal lines (the topmost and the second topmost 162As in Figs. 9A-9B).
Chen1 does not teach wherein each of the plurality of metal lines comprises at least two 90-degree turns on a horizontal plane.
In the same field of endeavor of semiconductor manufacturing, Chen2 teaches wherein each of the plurality of metal lines (312a; Fig. 2A, [0019]) comprises at least two 90-degree turns (right angle turn; [0020]) on a horizontal plane (X-Y plane; Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1 and Chen2, and to further introduce the turning segment of right angel turns into the metal lines of Chen1 as taught by Chen2, because the turning section can improve the tolerance capability of the metal line to the tensile stress resulting from CTS mismatched as taught by Chen2 ([0018]).
Regarding claim 24, Chen1 teaches the semiconductor package of claim 21, wherein the routing structure (158) is disposed on a package substrate (300; Fig. 17, [0074]).
Regarding claim 25, Chen1 teaches the semiconductor package of claim 24, wherein the package substrate (300) comprises a printed circuit board (PCB) (PCB; [0074]).
Regarding claim 27, Chen1 teaches in Fig. 9B, the semiconductor package of claim 21, wherein the first array of contact features (the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B) and the second array of contact features (the second and the fourth rightmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B) directly interface (directly electrically connected to) the plurality of metal lines (the topmost and the second topmost 162As in Figs. 9A-9B; [0030]), wherein the first array of contact features (the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B), wherein the second array of contact features (the second and the fourth rightmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B).
Chen1 does not explicitly teach in Fig. 9B, wherein the first array of contact features comprise first microbumps, wherein the second array of contact features comprise second microbumps.
In the same reference of Chen1, Chen1 teaches in Fig. 13, the contact features (162B, i.e. the via portion of 162 shown in Fig. 8) electrical connected to microbumps (176; Fig. 13, [0057]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Fig. 9A and 13 of Chen1, and to have a microbumps connected to the first array of contact features and the second array of contact features, because the microbumps (176) can provide external connections to the first array of contact features and the second array of contact features as taught by Chen1 (Fig. 17, [0074]).
The combination of Fig. 9B and Fig. 13 of Chen1 teach “wherein the first array of contact features comprise first microbumps, wherein the second array of contact features comprise second microbumps”, because the first microbumps (176s electrically connected to the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B) can be a part of the first array of contact features that the first microbumps is similar to the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B and are conduct features electrically connected to the first die, and the second microbumps (176s electrically connected to the second and the fourth leftmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B) can be a part of the second array of contact features that the second microbumps is similar to the second and the fourth leftmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B and are conduct features electrically connected to the second die.9999
Regarding claim 28, Chen1 teaches a semiconductor package (10), comprising: a routing structure (158; Fig. 12, [0028]); a first die (126A; Fig. 12, [0022]) and a second die (126B; Fig. 12, [0022]) disposed over the routing structure (158; see Fig. 12 upside down); a first array of contact features (the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B) disposed along a first direction (the horizontal direction in Fig. 9B) and electrically coupling the first die (126A) to the routing structure (158; Fig. 9B, [0030]); and a second array of contact features (the second and the fourth rightmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B) disposed along the first direction (the horizontal direction in Fig. 9B) and electrically coupling the second die (126B) to the routing structure (158; Fig. 9B, [0030]), wherein the routing structure (158) comprises a plurality of metal layers (162 and 166; Fig. 12, [0049-0050]), wherein a topmost one of the plurality of metal layers (162; see Fig. 12 upside down) comprises a plurality of metal lines (the topmost and the second topmost 162As in Figs. 9A-9B; [0030]) and each of the plurality of metal lines (the topmost and the second topmost 162As in Figs. 9A-9B; [0030]) electrically connects one of the first array of contact features (the second and the fourth leftmost 162Bs of 126A in the topmost line of 162Bs of Fig. 9B) and one of the second array of contact features (the second and the fourth rightmost 162Bs of 126B in the topmost line of 162Bs of Fig. 9B), wherein the routing structure (158) comprises an interposer (158 can be considered as an interposer, because it is between dies 126 and conductive connectors 176; Fig. 13; [0057]).
Chen1 does not teach wherein each of the plurality of metal lines comprises at least two 90-degree turns on a horizontal plane.
In the same field of endeavor of semiconductor manufacturing, Chen2 teaches wherein each of the plurality of metal lines (312a; Fig. 2A, [0019]) comprises at least two 90-degree turns (right angle turn; [0020]) on a horizontal plane (X-Y plane; Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1 and Chen2, and to further introduce the turning segment of right angel turns into the metal lines of Chen1 as taught by Chen2, because the turning section can improve the tolerance capability of the metal line to the tensile stress resulting from CTS mismatched as taught by Chen2 ([0018]).
Regarding claim 29, Chen1 teaches the semiconductor package of Claim 28, wherein each of the plurality of metal lines (the topmost and the second topmost 162As in Figs. 9A-9B; [0030]) comprises a portion (the portion of the metal lines in the gap regions 148; Figs. 9A-9B, [0025]) that is not disposed below the first die (126A) or the second die (126B; see Fig. 8 upside down, [0025]).
Chen1 does not teach wherein the portion forms an acute angle with the first direction.
In the same field of endeavor of semiconductor manufacturing, Chen2 teaches wherein the portion (the portion of the metal lines 312a between dies 110 and 120; Fig. 2A, [0019]) forms an acute angle (the angle θ can be an acute angle; [0020]) with the first direction (the horizontal direction in Fig. 2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1 and Chen2, and to further introduce the turning segment of acute angel turns into the metal lines of Chen1 between the first die and the second die as taught by Chen2, because the turning section can improve the tolerance capability of the metal line to the tensile stress resulting from CTS mismatched as taught by Chen2 ([0018]).
Regarding claim 30, Chen1 teaches the semiconductor package of claim 28, wherein the routing structure (158) is mounted on a package substrate (300; Fig. 17, [0074]).
Regarding claim 32, Chen1 teaches the semiconductor package of claim 2, wherein the portion (the portion of the metal lines in the gap regions 148; Figs. 9A-9B, [0025]) is straight (see Figs. 9A-9B).
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen1 and Chen2 as applied to claim 1 above, and further in view of Shih et al. (US 2016/0307852 A1).
Regarding claim 5, Chen1 teaches the semiconductor package of claim 1, wherein the routing structure (158) comprises a plurality of metal layers (162, 166, 170; Fig. 12, [0028]).
Chen1 does not teach wherein the routing structure comprises signal lines spread out in the plurality of metal layers.
In the same field of endeavor of semiconductor manufacturing, Shih et al. teach wherein the routing structure (104, 106; Figs. 1A-1B, [0013]) comprises signal lines (106; Figs. 1A-1B, [0013]) spread out in a metal layer (104, 106).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1, Chen2 and Shih et al., and to have the routing structure of Chen1 comprises signal lines spread out in the plurality of metal layers of Chen1 with the power/ground lines between them as taught by Shih et al., because the signal lines can be used to send out signals with reduced crosstalk and enhanced signal integrity as taught by Shih et al. ([0013]).
Regarding claim 6, Chen1 teaches the semiconductor package of claim 5.
Chen1 does not teach wherein a subset of the signal lines is disposed in one of the plurality of metal layers, wherein the subset of signal lines are laterally spaced apart by a plurality of ground lines.
In the same field of endeavor of semiconductor manufacturing, Shih et al. teach wherein a subset of the signal lines (106 in Figs. 1A-1B) is disposed in one of the plurality of metal layers (the metal layer of 104, 106 in Figs. 1A-1B), wherein the subset of signal lines (106) are laterally spaced apart by a plurality of ground lines (104; Figs. 1A-1B, [0013]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1, Chen2 and Shih et al., and to have the routing structure of Chen1 comprises signal lines spread out in the plurality of metal layers of Chen1 with the power/ground lines between them as taught by Shih et al., because the signal lines can be used to send out signals with reduced crosstalk and enhanced signal integrity as taught by Shih et al. ([0013]).
Claim(s) 7, 26 and 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen1 and Chen2 as applied to claims 1, 21 and 28 above, and further in view of Yamaguchi et al. (US 2007/0189672 A1).
Regarding claim 7, Chen1 teaches the semiconductor package of claim 1, wherein the interposer (158).
Chen1 does not teach the interposer (158) is a silicon interposer.
In the same field of endeavor of semiconductor manufacturing, Yamaguchi et al. teaches a photo-sensitive polyimide composition having a silicon atom-containing compound having a reactive unsaturated functional group and an alkoxy group or an acyloxy group ([0059]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1, Chen2 and Yamaguchi et al., and to use the photo-sensitive polyimide composition of Yamaguchi et al. as the dielectric layers of 158 of Chen1, because Chen1 teaches that the interposer (158) has dielectric layers (160, 164, 168, 172; Fig. 12, [0028]) of photo-sensitive polyimide ([0028]) and Yamaguchi et al. teaches that the photo-sensitive polyimide composition having a silicon atom-containing compound having a reactive unsaturated functional group and an alkoxy group or an acyloxy group is excellent in the adhesive to a substrate and the shape of the resulting pattern ([0059, 0084]).
The combination of Chen1, Chen2 and Yamaguchi et al. teaches “the interposer is a silicon interposer” as claimed, because the interposer of Chen1 after the combination would contain silicon in the dielectric layers of the interposer of Chen1, i.e. the interposer would be a silicon (containing) interposer.
Regarding claim 26, Chen1 teaches the semiconductor package of claim 21, wherein the interposer (158).
Chen1 does not teach the interposer (158) is a silicon interposer.
In the same field of endeavor of semiconductor manufacturing, Yamaguchi et al. teaches a photo-sensitive polyimide composition having a silicon atom-containing compound having a reactive unsaturated functional group and an alkoxy group or an acyloxy group ([0059]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1, Chen2 and Yamaguchi et al., and to use the photo-sensitive polyimide composition of Yamaguchi et al. as the dielectric layers of 158 of Chen1, because Chen1 teaches that the interposer (158) has dielectric layers (160, 164, 168, 172; Fig. 12, [0028]) of photo-sensitive polyimide ([0028]) and Yamaguchi et al. teaches that the photo-sensitive polyimide composition having a silicon atom-containing compound having a reactive unsaturated functional group and an alkoxy group or an acyloxy group is excellent in the adhesive to a substrate and the shape of the resulting pattern ([0059, 0084]).
The combination of Chen1, Chen2 and Yamaguchi et al. teaches “the interposer is a silicon interposer” as claimed, because the interposer of Chen1 after the combination would contain silicon in the dielectric layers of the interposer of Chen1, i.e. the interposer would be a silicon (containing) interposer.
Regarding claim 31, Chen1 teaches the semiconductor package of claim 28, wherein the interposer (158).
Chen1 does not teach the interposer (158) is a silicon interposer.
In the same field of endeavor of semiconductor manufacturing, Yamaguchi et al. teaches a photo-sensitive polyimide composition having a silicon atom-containing compound having a reactive unsaturated functional group and an alkoxy group or an acyloxy group ([0059]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1, Chen2 and Yamaguchi et al., and to use the photo-sensitive polyimide composition of Yamaguchi et al. as the dielectric layers of 158 of Chen1, because Chen1 teaches that the interposer (158) has dielectric layers (160, 164, 168, 172; Fig. 12, [0028]) of photo-sensitive polyimide ([0028]) and Yamaguchi et al. teaches that the photo-sensitive polyimide composition having a silicon atom-containing compound having a reactive unsaturated functional group and an alkoxy group or an acyloxy group is excellent in the adhesive to a substrate and the shape of the resulting pattern ([0059, 0084]).
The combination of Chen1, Chen2 and Yamaguchi et al. teaches “the interposer is a silicon interposer” as claimed, because the interposer of Chen1 after the combination would contain silicon in the dielectric layers of the interposer of Chen1, i.e. the interposer would be a silicon (containing) interposer.
Claim(s) 9 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen1 and Chen2 as applied to claims 1 and 21 above, and further in view of Shih et al. (US 2016/0307852 A1) and Zhang et al. (US 2021/0202616 A1).
Regarding claim 9, Chen1 teaches the semiconductor package of claim 1, wherein the first die (126A) comprises a plurality of transistors ([0020]), wherein the first array of contact features (the first array of contact feature can be the four 162Bs of 126A electrically connected to the four topmost metal lines 162A of Fig. 9B).
Chen1 does not teach the first array of contact features include: power/ground (P/G) contact features coupled to a positive supply voltage or a ground voltage, and signal contact features coupled to the plurality of transistors, wherein a ratio of the signal contact features to the P/G contact features is smaller than 1.5.
In the same field of endeavor of semiconductor manufacturing, Shih et al. teach power/ground (P/G) lines (104; Figs. 1A-1B, [0013]) coupled to a positive supply voltage or a ground voltage (the ground line is coupled to a ground voltage by definition), and signal lines (106; Figs. 1A-1B, [0013]), wherein a ratio of the signal lines to the P/G lines is smaller than 1.5 (1 as shown in Figs. 1A-1B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1 and Shih et al. and to have the top four metal lines of Fig. 9B of Chen1 as the signal lines and the power/ground lines alternately arranged (for example, the topmost and the third topmost metal lines are signal lines and the second and fourth topmost lines are power/ground lines) as taught by Shih et al., because this arrangement can have reduced crosstalk and enhanced signal integrity as taught by Shih et al. ([0013]).
The combination of Chen1 and Shih et al. teaches the first array of contact features include: power/ground (P/G) contact features coupled to a positive supply voltage or a ground voltage, and signal contact features, wherein a ratio of the signal contact features to the P/G contact features is smaller than 1.5, because Shih et al. teach power/ground (P/G) lines (104; Figs. 1A-1B, [0013]) coupled to a positive supply voltage or a ground voltage (the ground line is coupled to a ground voltage by definition), and signal lines (106; Figs. 1A-1B, [0013]), wherein a ratio of the signal lines to the P/G lines is smaller than 1.5 (1 as shown in Figs. 1A-1B), while Chen1 teaches the first array of contact features (the four 162Bs of 126A electrically connected to the four topmost metal lines 162A of Fig. 9B) include: power/ground (P/G) contact features (the two 162Bs of 126A electrically connected to, for example, the second and fourth topmost metal lines 162A of Fig. 9B as the P/G lines), and signal contact features (the two 162Bs of 126A electrically connected to, for example, the first and third topmost metal lines 162A of Fig. 9B as the signal lines) and there is one to one correspondence between the contact features of the four 162Bs of 126A electrically connected to the four topmost metal lines 162A of Fig. 9B and the four topmost metal lines.
Shih et al. do not teach signal contact features coupled to the plurality of transistors.
In the same field of endeavor of semiconductor manufacturing, Zhang et al. teach signal lines (150, 170, Fig. 1, [0021]) coupled to the plurality of transistors (120; Fig. 1, [0021]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1, Chen2, Shih et al. and Zhang et al., and to have the signal lines couple to the plurality of transistor, because the transistors can be used to control the devices ([0021]).
The combination of Chen1, Chen2, Shih et al. and Zhang et al. teaches signal contact features coupled to the plurality of transistors, because Chen1 teaches signal contact features (the two 162Bs of 126A electrically connected to, for example, the first and third topmost metal lines 162A of Fig. 9B as the signal lines) is coupled to the signal lines (the first and third topmost metal lines 162A of Fig. 9B as the signal lines) and Zhang et al. teach signal lines (150, 170, Fig. 1, [0021]) are coupled to the plurality of transistors (110, 120; Fig. 1, [0021]).
Regarding claim 23, Chen1 teaches the semiconductor package of claim 21, wherein the first die (126A) comprises a plurality of transistors ([0020]), wherein the first array of contact features (the first array of contact feature can be the four 162Bs of 126A electrically connected to the four topmost metal lines 162A of Fig. 9B).
Chen1 does not teach the first array of contact features include: power/ground (P/G) contact features coupled to a positive supply voltage or a ground voltage, and signal contact features coupled to the plurality of transistors, wherein a ratio of the signal contact features to the P/G contact features is smaller than 1.5.
In the same field of endeavor of semiconductor manufacturing, Shih et al. teach power/ground (P/G) lines (104; Figs. 1A-1B, [0013]) coupled to a positive supply voltage or a ground voltage (the ground line is coupled to a ground voltage by definition), and signal lines (106; Figs. 1A-1B, [0013]), wherein a ratio of the signal lines to the P/G lines is smaller than 1.5 (1 as shown in Figs. 1A-1B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1 and Shih et al. and to have the top four metal lines of Fig. 9B of Chen1 as the signal lines and the power/ground lines alternately arranged (for example, the topmost and the third topmost metal lines are signal lines and the second and fourth topmost lines are power/ground lines) as taught by Shih et al., because this arrangement can have reduced crosstalk and enhanced signal integrity as taught by Shih et al. ([0013]).
The combination of Chen1 and Shih et al. teaches the first array of contact features include: power/ground (P/G) contact features coupled to a positive supply voltage or a ground voltage, and signal contact features, wherein a ratio of the signal contact features to the P/G contact features is smaller than 1.5, because Shih et al. teach power/ground (P/G) lines (104; Figs. 1A-1B, [0013]) coupled to a positive supply voltage or a ground voltage (the ground line is coupled to a ground voltage by definition), and signal lines (106; Figs. 1A-1B, [0013]), wherein a ratio of the signal lines to the P/G lines is smaller than 1.5 (1 as shown in Figs. 1A-1B), while Chen1 teaches the first array of contact features (the four 162Bs of 126A electrically connected to the four topmost metal lines 162A of Fig. 9B) include: power/ground (P/G) contact features (the two 162Bs of 126A electrically connected to, for example, the second and fourth topmost metal lines 162A of Fig. 9B as the P/G lines), and signal contact features (the two 162Bs of 126A electrically connected to, for example, the first and third topmost metal lines 162A of Fig. 9B as the signal lines) and there is one to one correspondence between the contact features of the four 162Bs of 126A electrically connected to the four topmost metal lines 162A of Fig. 9B and the four topmost metal lines.
Shih et al. do not teach signal contact features coupled to the plurality of transistors.
In the same field of endeavor of semiconductor manufacturing, Zhang et al. teach signal lines (150, 170, Fig. 1, [0021]) coupled to the plurality of transistors (120; Fig. 1, [0021]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Chen1, Chen2, Shih et al. and Zhang et al., and to have the signal lines couple to the plurality of transistor, because the transistors can be used to control the devices ([0021]).
The combination of Chen1, Chen2, Shih et al. and Zhang et al. teaches signal contact features coupled to the plurality of transistors, because Chen1 teaches signal contact features (the two 162Bs of 126A electrically connected to, for example, the first and third topmost metal lines 162A of Fig. 9B as the signal lines) is coupled to the signal lines (the first and third topmost metal lines 162A of Fig. 9B as the signal lines) and Zhang et al. teach signal lines (150, 170, Fig. 1, [0021]) are coupled to the plurality of transistors (110, 120; Fig. 1, [0021]).
Response to Arguments
On pages 7-9 of Applicant’s Response, Applicant argues that Chen1’s frontside redistribution 158 is patentably distinct from the claimed interposer, because the Restriction action indicates: “The species are independent or distinct because Category I of the package structure: Species 1 of Fig. 1 has the RDL structure for connecting the dies, and Species 2 of Fig. 2 has the interposer for connecting the dies”.
The Examiner respectfully disagrees with Applicant’s argument, because the restriction and the rejection are two distinct processes which should not be mixed together. When the restriction is exercised, the whole disclosure of each embodiment, including the figures and paragraphs of the specification related to the embodiment, is considered to determine whether it is independent or distinct from other embodiments. For example, regarding the Species 1 of Fig. 1 having the RDL structure for connecting the dies, all the structures shown in Fig. 1 and the features of the RDL structure, dies, substrate, and connections mentioned in the specification related to Fig. 1 are considered in determining whether Species of Fig. 1 is independent or distinct from other embodiments. When the art rejection is exercised, only claimed limitations are considered and the claim interpretation is based on “broadest reasonable interpretation” (MPEP 2111). The term “interposer” is a very broad term which means “one that interposes” based on https://www.merriam-webster.com/dictionary/interposer, and “interpose” means: “to be or come between” based on https://www.merriam-webster.com/dictionary/interpose. Thus, any element which is between the other two elements is an interposer. Chen1’s frontside redistribution 158 is between dies 126 and conductive connectors 176, and can be interpreted as “an interposer”. Thus, the rejections still stand.
On page 9 of Applicant’s Response, Applicant argues on claims 21 and 28 with the same argument on claim 1.
The Examiner respectfully disagrees with Applicant’s argument, because the Examiner’s response to Applicant’s argument on claim 1 also applies to Applicant’s argument on claims 21 and 28.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HSIN YI HSIEH/Primary Examiner, Art Unit 2899 3/24/2026