Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed June 1st, 2026 1-20 are pending, of which claims 1-20 are currently rejected.
Response to Arguments
The claims filed June 1st, 2026 have been entered. Claims 1-20 remain pending in the application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 24th, 2026 has been entered.
Claim Objections
Applicant has amended claims and resolved the objection issues as previously presented in the Final Rejection mailed March 31st, 2026. Therefore, the previous claim objections as presented have been withdrawn.
Prior Art Rejections
Applicant’s arguments regarding the previously cited art have been fully considered and are not persuasive.
With regards to arguments related to rejections under 103, Applicant alleges that the combination of Kennedy in view of Prabhakar in view of Koeplinger does not teach the recited compute-unit architecture as required in claim 1 (Applicant Remarks Pgs. 9-10). Examiner respectfully disagrees. As discussed in the Final Rejection mailed March 31st, 2026, Kennedy is not relied upon to teach each of the compute units having a streaming port for row ordered matrix data and a staging port for column ordered matrix data, rather Kennedy is relied upon to teach a grid of compute units (having a plurality of rows and columns) and the routing of matrix data through the computing grid based on the stage of computation that is being carried out (Kennedy: Pg. 9 Fig. Spatial Dataflow Within an RDU). As discussed in the Final Rejection Kennedy is then combined with Prabhakar to teach the internal structure and functionality of the various compute units (as shown in Prabhakar Pg. 5 Figs. 3 and 4), and as discussed with respect to claim 8, Prabhakar's vector FIFOs are used for vector based computations correspondingly, and work in collaboration in order to carry out the operand specific rows. Prabhakar also very clearly shows the vector-based outputs (Prabhakar: Pg. 5 Figs. 3 and 4) which would afterwards be output to another PMU or PCU correspondingly as driven by the controllers of the computing grid (Pg. 5 Fig. 5). Lastly, Koeplinger is combined with Kennedy in view of Prabhakar, and Koeplinger teaches packet switching for providing both row major and column major vectors to the computing grid and correspondingly to the compute units within the grid in parallel (Koeplinger: Paragraph 0027). In combining Kennedy, Prabhakar, and Koeplinger, the general structure and task-based assignment of compute units of Kennedy is further modified by the internal structure of the compute units as discussed in Prabhakar, which is further modified by the packet-switching of row major and column major vectors as taught by Koeplinger in order to arrive at the claimed invention and achieve the operand-specific rows-of-A-versus-columns-of-B port division as recited in the amended claims.
In response to applicant's arguments against the references individually, one cannot show
nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
In response to applicant's argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. V. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the motivations "more sophisticated mapping scheme" and "to improve operative efficiency an ease accessing of matrices" are more than enough reason for one of ordinary skill in the art to combine the teachings of the references. One with ordinary skill in the art would draw the same conclusion upon viewing the distinct references and seeing the obvious benefit to combine them in order to reach the claimed invention.
Limitations from claims 7-8, 10, and 12 were brought up into independent claims respectively and therefore require updated grounds of rejection.
New reasons of rejection were made as necessitated by amendments. See Claim Rejections - 35 USC § 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 6-16 are rejected under 35 U.S.C. 103 as being unpatentable over P. Kennedy (“SambaNova SN10 RDU at Hot Chips 33”, August 2021) (hereinafter “Kennedy”), further in view of R. Prabhakar et al. ("Plasticine: A Reconfigurable Architecture for Parallel Patterns", 2017) (hereinafter “Prabhakar”), further in view of Koeplinger et al. (US 2020/0241844 A1) (hereinafter “Koeplinger”).
Regarding claim 1, Kennedy teaches:
A system for multiplying matrices A and B and producing a result matrix R in a coarse-grained computing grid, the system comprising:
a reconfigurable dataflow unit (RDU) comprising a computing grid, the computing grid comprising C compute units arranged in a 2D grid comprising m logical rows and n logical columns (Kennedy: Pg. 9 first figure shows 2D computing grid comprised of C compute units arranged in logical rows and logical columns);
one or more processors configured to assign each compute unit c of C compute units to a unique submatrix Rc (Kennedy: Pg. 9 first figure shows compute units being assigned to submatrices based on the stage of computation; Pg. 6 first figure the configuration and pipeline controller as the one or more processors; Pg 9 PCUs as compute units, shown in further detail on Pg. 6 first figure “Cardinal SN10: PCU”);
the one or more processors further configured to generate memory unit configuration information that enables one or more source memory units to provide matrix data (Kennedy: Pg. 7 second figure “Cardinal SN10: AG and CU” address ALUs and coalescing units of memory unit configuration provide this configuration information i.e., one or more processors; Pg. 9 first figure PMUs as memory units, shown in further detail on Pg. 6 second figure “Cardinal SN10: PMU”) via a plurality of packets (Pg. 7 first figure switch allows for packet-switched communication, so data travels through packets);
the one or more processors further configured to generate compute unit configuration information that enables each compute unit c to produce the unique submatrix Rc (Kennedy: Pg. 6 first figure shows PCUs or compute units being divided into submatrices based on the stage being performed by the compute units; Pg. 6 first figure pipeline and configuration controller as one or more processors);
the one or more processors further configured to communicate the memory unit configuration information and the compute unit configuration information to the RDU and initiating data flow in the computing grid to produce the result matrix R within the desired memory units (Kennedy: Pg. 9 first figure shows grid of PCUs and PMUs connected via a switch; end of Pg. 6 discusses how the switch and router crossbar is what directs information from and to the RDU and to the various PCUs and PMUs within the RDU, including configuration information and data to be processed; shown in further detail on Pg. 7 first figure).
Kennedy does not explicitly teach:
of a result matrix R comprising M rows and N columns
provide relevant matrix A data and matrix B data to the C compute units via a plurality of packets
wherein a compute unit of the computing grid comprises an array of arithmetic units comprising I lanes and J pipelined stages
wherein the compute unit comprises a streaming port configurable to sequentially stream K vector packets comprising matrix A data through the I lanes of the array of arithmetic units where each vector packet of the K vector packets comprises I column-ordered data elements corresponding to I rows of matrix A data
wherein the compute unit comprises a staging port configurable to receive J vector packets corresponding to J columns of matrix B data and sequentially provide a data element from each of the J vector packets.
wherein each arithmetic unit of the array of arithmetic units is configurable to repetitively conduct a multiply-accumulate operation using a data element from the streaming port and a data element from the staging port
wherein providing matrix B data to the C compute units comprises narrowcasting packets to each column of compute units in the computing grid, wherein the narrow-casted packets comprise matrix B data corresponding to the column of compute units.
However, Prabhakar teaches:
of a result matrix R comprising M rows and N columns (Prabhakar: Pg. 3 Col. 1 Lines 22-23 output matrix i.e., result matrix of dimension M x P)
provide relevant matrix A data and matrix B data to the C compute units (Prabhakar: Pg. 10 Col. 2 Section 4.3 Lines 16-18 memory units are configured for operations; Abstract Lines 21-23, Pg. 3 Col. 2 Lines 2-3 and Fig. 1 shows multiplication of matrices A and B)
and send the unique submatrix Rc to one or more desired memory units (Prabhakar: Pg. 4 Col. 2 Section 3.1 Lines 20-31 reading and writing by PCU i.e., compute units to PMU i.e., memory unit for result matrix computation; Pg. 4 Col. 2 Section 3.1 Lines 6-11 configuration registers for PCUs can additionally be used for the one or more processors for configuration as discussed with regards to Kennedy);
wherein a compute unit of the computing grid comprises an array of arithmetic units comprising I lanes and J pipelined stages (Prabhakar: Pg. 5 Fig. 3 compute units having pipelined stages and lanes);
wherein the compute unit comprises a streaming port configurable to sequentially stream K vector packets comprising matrix A data through the I lanes of the array of arithmetic units where each packet of the K packets comprises I column-ordered data elements corresponding to I rows of matrix A data (Prabhakar: Pg. 5 Fig. 1 shows compute unit PCU having a streaming port through the vector FIFO connection where K packets stream through the I lanes of the array of AU or FU, the packets being column ordered corresponding to these rows i.e., lanes, Fig. 4 shows 2 vector FIFOs one for row based and one for column based, which correspond with each other in turn)
wherein the compute unit comprises a staging port configurable to receive vector packets corresponding to columns of matrix B data and sequentially provide a data element from each of the vector packets (Prabhakar: the PCUs i.e., compute units interfacing with vector FIFOs i.e., the staging port for providing an element to each of the compute units Pg. 5 Fig. 3; Pg. 6 Col. 1 Lines 18-20);
wherein each arithmetic unit of the array of arithmetic units is configurable to repetitively conduct a multiply-accumulate operation using a data element from the streaming port and a data element from the staging port (Prabhakar: Pg. 5 Fig. 1 shows compute unit PCU having a streaming port and staging port through the vector FIFO connections where K packets stream through the I lanes of the array of AU or FU, the packets being column ordered corresponding to these rows i.e., lanes, Fig. 4 shows 2 vector FIFOs one for row based and one for column based, which correspond with each other in turn, each of the FIFO connections allowing for the streaming port and staging port connections accordingly).
It would have been obvious before the effective filing date of the claimed invention to combine the result matrix, the specific computation of matrix A and matrix B, and communication between the compute units and memory units as taught by Prabhakar with the structure as taught by Kennedy as both teachings are directed towards matrix computation through the use of a 2D grid of compute units and memory units. One with ordinary skill in the art would be motivated to combine both teachings because Prabhakar simply provides a more sophisticated mapping scheme for the same structure as Kennedy, hence allowing for further increase in compute utilization and improving performance (Prabhakar: Pg. 12 Col. 1 Lines 17-20).
While Kennedy in view of Prabhakar teaches the use of packets to provide data to the compute and memory units (Kennedy: Pg. 7 first figure switch allows for packet-switched communication, so data travels through packets) Kennedy in view of Prabhakar does not explicitly teach the staging port allowing for the receiving of J vector packets corresponding to J columns of the matrix or narrowcasting.
However, Koeplinger teaches the staging port allowing for receiving of J vector packets that correspond to the J columns of the matrix (Koeplinger: ¶ 0027 column major or column based vectors are provided to a vector bus, for this vector bus to be later packet switched in order to provide the vector through packets to the compute units within the grid as discussed in ¶ 0035) as well as narrowcasting of packets (Koeplinger: ¶ 0035 vector and scalar buses are packet switched in order to determine to what column or row the packet of input data is sent to, these packets being narrow-casted; ¶ 0027 these vector buses contain column major i.e., column-based vectors; Fig. 2 shows the same structure of a 2D grid of compute units and memory units).
It would have been obvious before the effective filing date of the claimed invention to combine packet switching for column-based vectors as taught by Koeplinger with the system as taught by Kennedy in view of Prabhakar as all teachings are directed towards matrix multiplication on a 2D grid of compute units and memory units. One with ordinary skill in the art would be motivated to combine the teachings in order to improve operating efficiency and ease accessing of matrices by the units (Koeplinger: ¶ 0004).
Regarding claim 2, Kennedy in view of Prabhakar in view of Koeplinger further teaches:
The system of claim 1, wherein the one or more processors configures each compute unit to send submatrix Rc of the result matrix R to one or more desired memory units for the result matrix R (Prabhakar: Pg. 7 Col. 2 Lines 27-28 output i.e., result matrix sent to output buses for a given partitioning; Pg. 12 Col. 1 Lines 27-29 PCU i.e., compute unit produces output feature map i.e., result matrix and is sent to another PMU i.e., desired memory unit).
The motivation to combine with respect to claim 1 applies equally to claim 2.
Regarding claim 3, Kennedy in view of Prabhakar in view of Koeplinger teaches:
The system of claim 1, wherein each compute unit c of the C compute units produces the unique submatrix Rc by sequentially providing column-based vectors for matrix A to a vector bus and concurrently conducting a multiply accumulate operation for each data element of the column-based vectors (Koeplinger: ¶ 0027 column major or column based vectors are provided to a vector bus, for this vector bus to be later packet switched in order to provide the vector through packets to the compute units within the grid as discussed in ¶ 0035 for matrix-based computation i.e., multiply-accumulate operations).
The motivation to combine with respect to claim 1 applies equally to claim 3.
Regarding claim 6, while Kennedy in view of Prabhakar teaches compute units of a computing grid being connected to a grid connected memory unit (Prabhakar: Pg. 5 Fig. 5 PCUs i.e., compute units being grid connected to PMUs i.e., memory units), Kennedy in view of Prabhakar does not teach narrow-casted packets being provided.
However, Koeplinger teaches PMUs i.e., memory units containing a vector bus interconnect which is connected to the vector bus having the narrow-casted packets for column major or column-based vectors (Koeplinger: ¶ 0034 - ¶ 0035).
The motivation to combine with respect to claim 1 applies equally to claim 6.
Regarding claim 7, Kennedy in view of Prabhakar in view of Koeplinger further teaches:
The system of claim 1, wherein a compute unit of the computing grid comprises an array of arithmetic units comprising I lanes and J pipelined stages (Prabhakar: Pg. 5 Fig. 3 compute units having pipelined stages and lanes).
The motivation to combine with respect to claim 1 applies equally to claim 7.
Regarding claim 8, while Kennedy teaches compute units, Kennedy does not explicitly teach:
wherein the compute unit comprises a streaming port configurable to sequentially stream K vector packets comprising matrix A data through the I lanes of the array of arithmetic units where each vector packet of the K vector packets comprises I column-ordered data elements corresponding to I rows of matrix A data.
However, Prabhakar teaches:
wherein the compute unit comprises a streaming port configurable to sequentially stream K vector packets comprising matrix A data through the I lanes of the array of arithmetic units where each packet of the K packets comprises I column-ordered data elements corresponding to I rows of matrix A data (Prabhakar: Pg. 5 Fig. 1 shows compute unit PCU having a streaming port through the vector FIFO connection where K packets stream through the I lanes of the array of AU or FU, the packets being column ordered corresponding to these rows i.e., lanes, Fig. 4 shows 2 vector FIFOs one for row based and one for column based, which correspond with each other in turn).
The motivation to combine with respect to claim 1 applies equally to claim 8.
Kennedy in view of Prabhakar does not explicitly teach the packets being vector based.
However, Koeplinger teaches the packets being vector based (Koeplinger: ¶ 0034 - ¶ 0035).
The motivation to combine with respect to claim 1 applies equally to claim 8.
Regarding claim 9, Kennedy does not explicitly teach:
wherein a row connected memory unit is configurable to stream the I rows of matrix A data to the streaming port via the K vector packets.
However, Prabhakar teaches:
wherein a row connected memory unit is configurable to stream the I rows of matrix A data to the vector port via the K vector packets (Prabhakar: Pg. 5 Fig. 4 shows vector FIFO connected to PCU and configured to stream I rows to vector bus via the vector packets).
The motivation to combine with respect to claim 1 applies equally to claim 9.
Kennedy in view of Prabhakar does not explicitly teach the packets being vector based.
However, Koeplinger teaches the packets being vector based (Koeplinger: ¶ 0034 - ¶ 0035).
The motivation to combine with respect to claim 1 applies equally to claim 9.
Regarding claim 10, while Kennedy teaches corresponding stages of the array of compute units and data being provided accordingly (Kennedy: Pg. 9 first figure), Kennedy does not explicitly teach:
wherein the compute unit comprises a staging port configurable to receive J vector packets corresponding to J columns of matrix B data and sequentially provide a data element from each of the J vector packets.
However, Prabhakar teaches the PCUs i.e., compute units interfacing with vector FIFOs i.e., the staging port for providing an element to each of the compute units (Prabhakar: Pg. 5 Fig. 3; Pg. 6 Col. 1 Lines 18-20).
The motivation to combine with respect to claim 1 applies equally to claim 10.
Kennedy in view of Prabhakar does not explicitly teach this staging port allowing for the receiving of J vector packets that correspond to the J columns of the matrix.
However, Koeplinger teaches in ¶ 0027 how column major or column based vectors are provided to a vector bus, for this vector bus to be later packet switched in order to provide the vector through packets to the compute units within the grid as discussed in ¶ 0035. These column vector packets can be provided through the vector FIFO as discussed with respect to Prabhakar.
The motivation to combine with respect to claim 1 applies equally to claim 10.
Kennedy in view of Prabhakar in view of Koeplinger therefore teaches:
The system of claim 8, wherein the compute unit comprises a staging port configurable to receive J vector packets corresponding to J columns of matrix B data and sequentially provide a data element from each of the J vector packets to a corresponding stage of the array of arithmetic units.
Regarding claim 11, Kennedy in view of Prabhakar in view of Kennedy further teaches:
The system of claim 10, wherein the data element is concurrently provided to every arithmetic unit of the corresponding stage of the array of arithmetic units (Prabhakar: Pg. 3 Fig. 1 and 2 show the functions performed by RDU, multiply accumulate operations; Pg. 4 Col. 2 Section 3.1 Lines 5-18 providing data element concurrently to each of the arithmetic units i.e., functional units of the compute units).
The motivation to combine with respect to claim 1 applies equally to claim 11.
Regarding claim 12, Kennedy in view of Prabhakar in view of Koeplinger teaches:
The system of claim 10, wherein each arithmetic unit of the array of arithmetic units is configurable to repetitively conduct a multiply-accumulate operation using a data element from the streaming port and a data element from the staging port (Prabhakar: Pg. 5 Fig. 1 shows compute unit PCU having a streaming port and staging port through the vector FIFO connections where K packets stream through the I lanes of the array of AU or FU, the packets being column ordered corresponding to these rows i.e., lanes, Fig. 4 shows 2 vector FIFOs one for row based and one for column based, which correspond with each other in turn, each of the FIFO connections allowing for the streaming port and staging port connections accordingly).
The motivation to combine with respect to claim 1 applies equally to claim 12.
Claims 13-14 recite the method practiced by the system of claims 1-2 respectively, and are therefore rejected for the same reasons therein.
Regarding claim 15, while Kennedy in view of Prabhakar teaches packets, Kennedy does not teach the packets being vector-sized or being processed in parallel by a compute unit.
However, Koeplinger teaches:
wherein the plurality of packets are vector-sized packets each comprising a vector of data elements that can be processed in parallel by a compute unit c of the C compute units (Koeplinger: ¶ 0027 read operations of packets operating in parallel to allow for parallel computations of the packets; ¶ 0035 vector and scalar buses are packet switched in order to determine to what column or row the packet of input data is sent to, these packets being narrow-casted; ¶ 0027 these vector buses contain column major i.e., column-based vectors; Fig. 2 shows the same structure of a 2D grid of compute units and memory units).
The motivation to combine with respect to claim 1 applies equally to claim 15.
Claim 16 recites the method practiced by the system of claim 3, and is therefore rejected for the same reasons therein.
Claims 4-5 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kennedy in view of Prabhakar, in view of Koeplinger, further in view of Yinger et al. (US 2019/0012295 A1) (hereinafter “Yinger”).
Regarding claim 4, while Kennedy in view of Prabhakar in view of Koeplinger teaches the system of claim 1, Kennedy in view of Prabhakar in view of Koeplinger does not explicitly teach compute units for each row having a dedicated memory for that row.
However, Yinger teaches:
wherein the compute units for each row of the computing grid are connected to a memory unit dedicated to that row of the computing grid (Yinger: Fig. 1 Row feeder dedicated for each of the rows, claim 1 each of the row feeders have a corresponding buffer element i.e., the dedicated memory for each of the rows of the computing grid).
It would have been obvious before the effective filing date of the claimed invention to combine the dedicated memory as taught by Yinger with the system as taught by Kennedy in view of Prabhakar in view of Koeplinger as all teachings are directed towards matrix computations via a 2D grid of processing units. One with ordinary skill in the art would be motivated to combine the teachings because doing so would enable SRAM savings and enabling a quadratic reduction in external RAM bandwidth requirement (Yinger: ¶ 0015).
Regarding claim 5, Kennedy in view of Prabhakar in view Koeplinger in view of Yinger further teaches:
The system of claim 4, wherein all rows of matrix A are stored in the memory unit dedicated to that row of the computing grid (Yinger: Claim 1 second matrix is provided to computing grid row via row feeder and row feeder buffer, all rows of second matrix are stored in dedicated memory).
The motivation to combine with respect to claim 4 applies equally to claim 5.
Claims 17-18 recite the method practiced by the system of claims 4-5 respectively and are therefore rejected for the same reasons therein.
Regarding claim 19, while Kennedy in view of Prabhakar teaches compute units of a computing grid being connected to a grid connected memory unit (Prabhakar: Pg. 5 Fig. 5 PCUs i.e., compute units being grid connected to PMUs i.e., memory units), Kennedy in view of Prabhakar does not teach narrow-casted packets being provided.
However, Koeplinger teaches PMUs i.e., memory units containing a vector bus interconnect which is connected to the vector bus having the narrow-casted packets for column major or column-based vectors (Koeplinger: ¶ 0034 - ¶ 0035).
The motivation to combine with respect to claim 1 applies equally to claim 19.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kennedy in view of Prabhakar, in view of Koeplinger, further in view of Nemlekar (US 2020/0183734 A1) (hereinafter “Nemlekar”).
Claim 20 recites the non-transitory computer readable storage medium having instructions for executing the method practiced by the system of claim 1, which is taught by Kennedy in view of Prabhakar in view of Koeplinger. Kennedy in view of Prabhakar in view of Koeplinger does not explicitly teach a computer readable medium having instructions encoded to execute the method.
However, Nemlekar teaches a non-transitory computer readable medium with instructions to be executed for a method of matrix computation on a computer grid (Nemlekar: ¶ 0032, Fig. 1 shows a computing grid at 110).
It would have been obvious before the effective filing date of the claimed invention to combine the non-transitory computer readable medium as taught by Nemlekar with the system as taught by Kennedy in view of Prabhakar in view of Koeplinger as all teachings are directed towards grid-based matrix computations. One with ordinary skill in the art would be motivated to combine the teachings because this would allow the instructions for executing the method to be easily manipulatable (Nemlekar: ¶ 0033).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIA DE JESUS RIVERA whose telephone number is (571)272-2793. The examiner can normally be reached Monday-Friday 7:30AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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