DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
1. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The “ : “ after “between” in claim 1 is unclear. The claim recites, “signal routing paths extending between: the electrical contact structures; and some of the RX circuits or some of the TX circuits;” To make it clear what the signal routing paths are extending between, the Examiner suggests language similar to:
“signal routing paths extending between the electrical contact structures and some of the RX circuits or signal routing paths extending between the electrical contact structures and some of the TX circuits”
Response to Arguments
2. The drawings rejections, under 37 CFR 1.83(a), have been overcome. The corrected drawings show the signal routing paths extending between the electrical contact structures and some of the RX circuits for claims 11, 20 and 24, and the corrected drawings show signal routing paths extending between the electrical contact structures and some of the TX circuits for claims 11, 20 and 24.
The BRI claim language is till vague regarding the 35 USC § 112(b) rejection. The Examiner acknowledges the amended claim language to eliminate claim language “on one hand, and, on another hand,”. However, the amendment has introduced a new 112 issue. See 112 rejection above. The recitation of “some” are connected does not require that “some of them are not” connected for claims 11, 20 and 24.
Regarding the Applicant’s argument on page 14, the argument is non persuasive. Claim 1 language does not require that enable/disable functionality be mapped to the bump configuration and be capable of addressing a subset of the PHY. The claim recitation of “some are connected”, does not require that “some of them are not” connected. Therefore, the 102 rejection with reference Qian et al. for claim 1 is upheld.
Regarding the Applicant’s argument on page 15, the argument is non persuasive. Claim 1 language does not require the mechanism of reusing the same die for both high- and low- density bump configurations by selectively disabling redundant PHY circuits at the package level. Therefore, the 102 rejection with reference Qian et al. for claim 1 is upheld.
Regarding the Applicant’s argument on page 16, the argument is non persuasive. Claim 1 language does not require swappable PHY configurations. Therefore, the 102 rejection with reference Qian et al. for claim 1 is upheld.
Regarding the Applicant’s argument on page 17, the argument is non persuasive. Qian et al. is relied upon for the rejection of Claim 1. (See Examiner’s arguments above.) Therefore, the 102 rejection with reference Qian et al. for claim 1 is upheld.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claim(s) 1, 3, 5, 6 -10, 20, 22, 24-25 is/are rejected under 35 U.S.C. 102 (a)(1) and 102 (a)(2) as being anticipated by Qian et al. , herein referred to as Qian (US 20210398906).
As to claim(s) 1, a microelectronic device (See Figs. 2A, 3A, 3C ) including:
a substrate (¶ 0037, (382) Qian);
physical layer (¶ 0003 (PHY), Qian) circuitry on the substrate (¶ 0036, (382) Qian) including a plurality of receive (RX) circuits (¶ 0028 Fig. 2A, receiver region, R.sub.X ) and a plurality of transmit (TX) circuits (¶ 0028 Fig. 2A, transmitter region, T.sub.X);
electrical contact structures (¶ 0036 interconnects (383), Qian) at a bottom surface of the device;
signal routing paths (¶ 0054 Leadways 575 provide electrical coupling between the R.sub.X bumps 553.sub.R and the R.sub.X circuits 572.) extending between the electrical contact structures (¶ 0036 interconnects (383), Qian); and some of the RX circuits (¶ 0028 Fig. 2A, receiver region, R.sub.X ) or some of the TX circuits (¶ 0028 Fig. 2A, transmitter region, T.sub.X); and
electrical pathways (¶ 0024 An example of a PHY-based IO bump region is shown in FIG. 1A. FIG. 1A is a macro view of an IO region 180 and a logic region 185 of a die 100. ¶ 0027 teaches an example of PHY less circuitry is shown in Fig. 1B.) leading to the PHY circuitry (¶ 0003 (PHY) ¶ 0003, Qian) and configured such that at least one of: an enable signal input to the device is to travel through some of the electrical pathways to enable a portion of the PHY circuitry (PHY) ¶ 0003, Qian) and ¶ 0059 discloses how the communication chip 606 enables wireless communications for the transfer of data to and from the computing device 600); or
a disable signal input to the device is to travel through some of the electrical pathways to disable a corresponding portion of the PHY circuitry.
(Regarding claim 1, the Examiner has interpreted the language of claim 1 to be functional. Language in an apparatus or product claim directed to the function, operation, intent-of-use, and materials upon which the components of the structure work that does not structurally limit the components or patentably differentiate the claimed apparatus or product from an otherwise identical prior art structure will not support patentability. See, e.g., In re Rishoi, 197 F.2d 342, 344-45 (CCPA 1952); In re Otto, 312 F.2d 937, 939-40 (CCPA 1963); In re Ludtke, 441 F.2d 660, 663-64 (CCPA 1971); In re Yanush, 477 F.2d 958, 959 (CCPA 1973). The patentability of an apparatus claim depends only on the claimed structure, not on the use or purpose of that structure, Catalina Mktg. Int’l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 809 (Fed. Cir. 2002), or the function or result of that structure. In re Danly, 263 F.2d 844, 848 (CCPA 1959). Please also see M.P.E.P. 2114 [R-1].
The following italicized limitations of claim 1 lines: 12-15
are understood to be functional. (i.e. “configured such that at least one of: an enable signal input to the device is to travel through some of the electrical pathways to enable a portion of the PHY circuitry; or a disable signal input to the device is to travel through some of the electrical pathways to disable a corresponding portion of the PHY circuitry.”)
The limitation describes intended use of electrical pathways. However, the claim does not disclose a sufficient structure which supports the function. Since Qian et al. shows an identical structure as claimed, namely electrical pathways, the Examiner submits that the electrical pathways are capable of producing the claimed results.)
As to claim(s) 3, the microelectronic device of claim 1, wherein
the electrical pathways leading to the PHY circuitry are configured such that at least one of: an enable signal input to the device is to travel through some of the electrical pathways to enable
1
2
of the RX circuits and
1
2
of the TX circuit (See Fig. 3C, Qian); or
a disable signal input to the device is to travel through some of the electrical pathways to disable a remaining
1
2
of the RX circuits and
1
2
of the TX circuit (See Fig. 3C, Qian).
As to claim(s) 5 , the microelectronic device of claim 1, wherein
some of the signal routing paths extend between corresponding ones of the electrical contact structures and all (Fig. 3A, ¶ 0036- ¶ 0039, Qian) of the RX circuits, and
some of the signal routing paths extend between corresponding ones of the electrical contact structures and all (Fig. 3A, ¶ 0036- ¶ 0039, Qian) of the TX circuits.
(Regarding claim(s) 5, Qian teaches all the limitations of claim 5. All of the Rx circuits and all of the Tx circuits are routed to the signal routing paths of Rx electrical contacts or Tx electrical contacts as shown in Figs. 2A and 2B. See ¶ 0032 and ¶ 0028, “Referring now to FIG. 2A, a plan view illustration of an IO bump map 250 is shown, in accordance with an embodiment. In the illustrated embodiment, a transmitter region T.sub.X and a receiver region R.sub.X are provided. The transmitter region T.sub.X is positioned along the die edge 220 and the receiver region R.sub.X is stacked behind (i.e., below in FIG. 2A) the transmitter region T.sub.X. In an embodiment, the IO bump map 250 may comprise signaling bumps 253, power bumps 254, and ground bumps 255. The bumps 253, 254, 255 may be arranged in a hexagon pattern. However, other bump layout patterns may also be used in different embodiments.” )
As to claim(s) 6, the microelectronic device of claim 1, wherein
some of the signal routing paths extend between corresponding ones of the electrical contact structures (Fig. 3A, ¶ 0036- ¶ 0039, Qian) and a portion of the RX circuits, and
some of the signal routing paths extend between corresponding ones of the electrical contact structures (Fig. 3A, ¶ 0036- ¶ 0039, Qian) and a portion of the TX circuits.
(Regarding claim(s) 6, Qian teaches all the limitations of claim 6. The Applicants Fig. 4A and 4B appear to show signal routing paths extending between corresponding ones of the electrical contact structures for “all”, “some”, and “a portion” of the RX and TX circuits. The Applicants Figs 4A and 4B are similar to the Fig. 3A in the Qian reference, with regard to showing signal routing paths extending between corresponding ones of the electrical contact structures for “all”, “some”, and “a portion” of the RX and TX circuits.)
As to claim(s) 7, the microelectronic device of claim 6, wherein:
the portion of the RX circuits includes
1
2
of the RX circuits and the portion of the TX circuits includes or
1
2
of the TX circuits (¶ 0038 - ¶ 0042, Qian); or
the portion of the RX circuits includes
1
4
of the RX circuits and the portion of the TX circuits includes or
1
4
of the TX circuits.
As to claim(s) 8, the microelectronic device of claim 1, wherein
the electrical contact structures include bumps (See Fig. 3A) , ¶ 0036 “In an embodiment, the interconnects 383 are shown as solder balls”).
As to claim(s) 9-10, the microelectronic device of claim 1, wherein
a pitch between the electrical contact structures is between about 110 microns and about 130 microns. (¶ 0044-0046 “the underlying circuitry may remain the same whether a 55 μm bump pitch or a 110 μm bump pitch is used.”, Qian)
a pitch between the electrical contact structures is between about 36 microns and about 55 microns. (¶ 0044-0046 “the underlying circuitry may remain the same whether a 55 μm bump pitch or a 110 μm bump pitch is used”, Qian.)
(Regarding claim(s) 9-10, Quian teaches all the limitations of claim 9 and 10. Furthermore, the Applicant has not shown that a pitch between the electrical contact structures is between about 110 microns and about 130 microns, or between 36 microns and about 55 microns are novel and would not have been found through routine experimentation. Nonetheless, it would have been obvious to one having ordinary skill in the art at the time the invention was made to optimize the pitch between the electrical contact structures so as to be able in order to optimize the device reliability/design and connectivity requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. )
As to claim(s) 20, an integrated circuit (IC) (See Fig. 3A, 3B, 3C and Fig. 6) device assembly including:
a printed circuit board and a plurality of integrated circuit components coupled to the printed circuit board (¶ 0057 “FIG. 6 illustrates a computing device 600 in accordance with one implementation of the invention. The computing device 600 houses a board 602. The board 602 may include a number of components, including but not limited to a processor 604 and at least one communication chip 606. The processor 604 is physically and electrically coupled to the board 602. In some implementations the at least one communication chip 606 is also physically and electrically coupled to the board 602. In further implementations, the communication chip 606 is part of the processor 604., Qian)
individual ones of the integrated circuit components including one or more semiconductor packages (¶ 0060 “The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In some implementations of the invention, the integrated circuit die of the processor may be part of an electronic package that comprises a PHY less IO bump map, in accordance with embodiments described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory., Qian)
individual ones of the semiconductor packages including: a package substrate (¶ 0067 the electronic package of Examples 1-3, wherein the interconnects are within the package substrate, Qian);
a plurality of dies on the package substrate (¶ 0073 the electronic package of Examples 1-9, wherein the first bump map comprises: a first transmitter region; and a first receiver region, wherein the first transmitter region is along an edge of the first die; and wherein the second bump map comprises: a second transmitter region; and a second receiver region, wherein the second transmitter region is along an edge of the second die., Qian) individual ones of the dies including:
a die substrate; physical layer (PHY) circuitry on the die substrate including a plurality of receive (RX) circuits and a plurality of transmit (TX) circuits (¶ 0081 a semiconductor die, comprising: a semiconductor substrate, wherein the semiconductor substrate comprises: an IO transmitter region comprising a plurality of transmitter circuits; and an IO receiver region comprising a plurality of receiver circuits; a plurality of metal layers over the semiconductor substrate; Qian)
electrical contact structures at a bottom surface of the die (See Fig. 3A, 3D, Qian); signal routing paths extending between the electrical contact structures; and some of the RX circuits or some of the TX circuits;
electrical pathways leading to the PHY circuitry and configured such that at least one (¶ 0038 - ¶ 0042, Qian) of: an enable signal input to the die is to travel through some of the electrical pathways to enable a portion of the PHY circuitry (¶ 0064 an electronic package, comprising: a package substrate; a first die over the package substrate, wherein the first die comprises a first IO bump map, wherein bumps of the first IO bump map have a first pitch; a second die over the package substrate, wherein the second die comprises a second IO bump map, wherein bumps of the second IO bump map have a second pitch that is different than the first pitch; and interconnects between the first IO bump map and the second IO bump map., Qian); or
a disable signal input to the die is to travel through some of the electrical pathways to disable a corresponding portion of the PHY circuitry; and wherein
the package substrate includes package signal routing paths (Fig. 2A, 3A, 3B, Qian) extending between a first die of the plurality of dies and a second die of the plurality of dies to provide a device-to-device (D2D) signal interconnection therebetween (¶ 0064, Qian).
As to claim(s) 22, the IC device assembly of claim 20, wherein,
for individual ones of the dies (3301 and 3302 , Fig. 3A), the electrical pathways leading to the PHY circuitry are configured such that at least one of:
an enable signal input to the die (¶ 0039, “The first die 330.sub.1 comprises a first bump map 350.sub.1 and the second die 330.sub.2 comprises a second bump map 350.sub.2. The first bump map 350.sub.1 comprises a T.sub.X region 355.sub.1 and a pair of R.sub.X regions 356.sub.1. The T.sub.X region 355.sub.1 is located proximate to an edge of the first die 330.sub.1. The second bump map 350.sub.2 comprises a pair of T.sub.X regions 355.sub.2 and an R.sub.X region 356.sub.2.”, Qian) is to travel through some of the electrical pathways to enable
1
2
of the RX circuits and
1
2
of the TX circuit (¶ 0038 - ¶ 0042, Qian); or
a disable signal input to the die is to travel through some of the electrical pathways to disable a remaining
1
2
of the RX circuits and
1
2
of the TX circuit.
As to claim(s) 24, a method to fabricate a microelectronic device including:
providing a substrate (¶ 0037, (382) Qian);
providing a physical layer (¶ 0003 (PHY), Qian) (PHY) circuitry on the substrate (¶ 0036, (382) Qian) including a plurality of receive (RX) circuits (¶ 0028 Fig. 2A, receiver region, R.sub.X ) and a plurality of transmit (TX) circuits (¶ 0028 Fig. 2A, transmitter region, T.sub.X);
providing electrical contact structures (¶ 0036 interconnects (383), Qian) at a bottom surface of the device;
providing signal routing paths (¶ 0054 Leadways 575 provide electrical coupling between the R.sub.X bumps 553.sub.R and the R.sub.X circuits 572.) extending between the electrical contact structures; (¶ 0036 interconnects (383), Qian) and some of the RX circuits (¶ 0028 Fig. 2A, receiver region, R.sub.X ) or some of the TX circuits; (¶ 0028 Fig. 2A, transmitter region, T.sub.X) and
providing electrical pathways (¶ 0024 An example of a PHY-based IO bump region is shown in FIG. 1A. FIG. 1A is a macro view of an IO region 180 and a logic region 185 of a die 100. ¶ 0027 teaches an example of PHY less circuitry is shown in Fig. 1B.) leading to the PHY circuitry (¶ 0003 (PHY) ¶ 0003, Qian); at least one of: providing an enable signal into the device through some of the electrical pathways to enable a portion of the PHY circuitry; (PHY) ¶ 0003, Qian) and ¶ 0059 discloses how the communication chip 606 enables wireless communications for the transfer of data to and from the computing device 600) or
providing a disable signal into the device through some of the electrical pathways to disable a corresponding portion of the PHY circuitry.
As to claim(s) 25, the method of claim 24, wherein
the electrical pathways (¶ 0024 An example of a PHY-based IO bump region is shown in FIG. 1A. FIG. 1A is a macro view of an IO region 180 and a logic region 185 of a die 100. ¶ 0027 teaches an example of PHY less circuitry is shown in Fig. 1B.) leading to the PHY circuitry are configured such that at least one of: an enable signal input to the device is to travel through some of the electrical pathways to enable
1
2
of the RX circuits and
1
2
of the TX circuit (¶ 0038 - ¶ 0042, Qian); or
a disable signal input to the device is to travel through some of the electrical pathways to disable a remaining
1
2
of the RX circuits and
1
2
of the TX circuit.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
6. Claim(s) 2, 4, 21 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Qian et al., herein referred to as Qian (US 20210398906).
As to claim(s) 2, the microelectronic device (See Fig. 3A, 3B, 3C) of claim 1, wherein
the electrical pathways include at least one of a fuse or a register (obvious) to at least one of enable or disable said corresponding portion of the PHY circuitry.
(Regarding claim(s) 2, Qian teaches all the limitations of claim 2 but does not explicitly teach a register to at least one of enable or disable said corresponding portion of the PHY circuitry. Registers are known electronic circuits used for storing information and controlling signals. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed that the register in the device of Qian is a part of the electrical pathway enabling or disabling a portion of the PHY circuity.
Also, ¶ 0060 of Qian and ¶ 0087 of the Applicants Specification, both explicitly disclose the term “processor” which “may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.” Therefore, it is obvious that the register in the device of Qian, functions the same as the register in the Applicants device to enable the corresponding components of the PHY circuitry.)
As to claim(s) 4, the microelectronic device of claim 1, wherein
the electrical pathways leading to the PHY circuitry are configured such that at least one of (¶ 0038 - ¶ 0042, Qian): an enable signal input to the device is to travel through some of the electrical pathways to enable
1
4
of the RX circuits and
1
4
of the TX circuit (obvious); or
a disable signal input to the device is to travel through some of the electrical pathways to disable a remaining
3
4
of the RX circuits and
3
4
of the TX circuit.
(Regarding claim(s) 4, "PHY" refers to the physical layer of a network, which handles the physical transmission and reception of data. A "PHY less" design, on the other hand, eliminates the separate PHY chip and integrates some of its functions into the application-specific integrated circuit (ASIC) or other on-chip logic. The Qian reference teaches both PHY and PHY less designs with Example 11 of ¶ 0074 and Example 18 of ¶ 0081 pointing to a plurality of both transmitter (Tx) circuits and receiver (Rx) circuits. As stated in ¶ 0026 of Qian, “PHY less designs eliminate the need for custom HIP for each device. “ Yet there still exists a physical connection of circuit parts in the PHY less design, which includes electrical pathways enabling physical circuitry.
Qian does not explicitly teach a signal input to the device through at least some of the electrical pathways to enable
1
4
of the RX circuits and
1
4
of the TX circuit. (Fig. 3C, Qian) points to
1
2
electrical pathway design variation. While (Fig. 3B, Qian) points to
1
3
electrical pathway design variation. However, Qian’s teaching of Tx and Rx designs through both
1
3
and
1
2
electrical pathway design variations is indicative of the ability of Qian to vary the circuit design.
Obviously, as disclosed in ¶ 0026, modifying the design of the circuitry to enable or disable signal input to the device by travel through
1
2
,
1
3
and
1
4
pathways is an obvious design variation to optimize the device reliability/design and connectivity requirements. As shown by the variations of (3501 and 3502) in Figs. 3B, 3C and 3E of Qian, design variations allow for on chip variations. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to design the device of Qian to enable
1
4
of the RX circuits and
1
4
of the TX circuits as disclosed in the Applicant’s device so as to use an industrially tested and accepted device.)
As to claim(s) 21, the IC device assembly of claim 20, wherein,
for individual ones of the dies, the electrical pathways include at least one of a fuse or a register (obvious) to at least one of enable or disable said corresponding portion of the PHY circuitry.
(Regarding claim(s) 21, Qian teaches the limitations of claims 21. See Examiner’s rejection of claim 2. )
As to claim(s) 23, the IC device assembly of claim 20, wherein,
for individual ones of the dies, (3301 and 3302 , Fig. 3A), the electrical pathways leading to the PHY circuitry are configured such that at least one of:
an enable signal input to the die is to travel through at least some of the electrical pathways (obvious) to enable
1
4
of the RX circuits and
1
4
of the TX circuit; (¶ 0038 - ¶ 0042, Qian) or
a disable signal input to the die is to travel through at least some of the electrical pathways to disable a remaining
3
4
of the RX circuits and
3
4
of the TX circuit.
(Regarding claim(s) 23, See Examiner’s remarks for claims 4, above. )
7. Claim(s) 11-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Qian et al., herein referred to as Qian (US 2021039890) in view of Mathuriya et al., herein referred to as Mathuriya (US 12079475). (Fig. 3A, 3C)
As to claim(s) 11, discloses a semiconductor package, comprising:
a package substrate (Fig. 3A, Qian); two pairs of dies on the package substrate including a first pair of dies including a first die (3301, Qian) and a second die (3302, Qian), and
a second pair of dies (Fig. 35, Mathuriya) including a third die (die 2002-1, Mathuriya) and a fourth die (die 2002-1, Mathuriya), wherein: individual ones of the dies include:
a die substrate (¶ 0037, (382) Qian); physical layer (¶ 0003 (PHY), Qian) (PHY) circuitry on the die substrate (¶ 0036, (382) Qian) including a plurality of receive (RX) circuits (¶ 0028 Fig. 2A, receiver region, R.sub.X ) and a plurality of transmit (TX) circuits (¶ 0028 Fig. 2A, transmitter region, T.sub.X) electrical contact structures (¶ 0036 interconnects (383), Qian) at a bottom surface of the die;
individual ones of the first die (3301, Qian) and the second die (3302, Qian) include signal routing paths extending between the electrical contact structures (353/380, Qian) thereof; and some of the RX circuits (3561/3562 Qian) and some of the TX circuits (3551/3552 Qian) thereof; and
individual ones of the third die (die 2002-1, Mathuriya), and the fourth die (die 2002-1, Mathuriya), include signal routing paths extending between; the electrical contact structures thereof; and a portion of the RX circuits and a portion of the TX circuits thereof, wherein
the package substrate includes first package signal routing paths extending (¶[0060 The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In some implementations of the invention, the integrated circuit die of the processor may be part of an electronic package that comprises a PHY less IO bump map, in accordance with embodiments described herein., Qian) between the first die and the second die to provide a device-to-device (D2D) signal interconnection therebetween, (¶ 0009, ”FIG. 3A is a cross-sectional illustration of an electronic package with dies that are communicatively coupled across a bridge in the electronic package, in accordance with an embodiment.” Qian) and
second package signal routing paths extending between the first die and the second die to provide a device-to- device (D2D) signal interconnection therebetween. (¶ 0012, “ FIG. 3D is a cross-sectional illustration of an electronic package with dies that are communicatively coupled across a package substrate, in accordance with an embodiment.” Qian)
(Regarding claim(s) 11, Qian discloses all the limitations of claim 11 except a third and fourth die electrically coupled to the first and second die, respectively. However, it has been held that “mere duplication of parts has no patentable significance unless a new and unexpected result is produced” (See MPEP 2144.04(VI)(B)). In the present case, adding a third and fourth die to the device of Qian would simply allow for more room to couple components for multi-die communication and easy scaling to support different packaging technologies. Such a device would continue to function in the same manner and accomplish the same function. Therefore, it would have been obvious to duplicate the first and second dies of the Qian device to include a third and fourth die.
Furthermore, the device of Mathuriya is an analogous multi-dimensional packaging device related to Qian in that the multiple dies of Mathuriya are coupled via bumps for Flip-chip ball grid array routing, chip-on-wafer substrate, or embedded multi-die interconnect bridge bonding. Mathuriya teaches in column 49 lines 32-37, Fig. 33, an apparatus wherein the first die, the second die, the third die, and the fourth die are coupled to one another via at least one of: micro-bumps, copper-to-copper hybrid bond, or wire bond, Flip-chip ball grid array routing, chip-on-wafer substrate (COWOS), or embedded multi-die interconnect bridge. It would have been obvious to merely duplicate the number of die of Qian because such configuration was in fact known in the art as evidenced by Fig. 33 of Mathuriya explained above.
It is known in the art to design semiconductor packages with multiple dies so that individual chips are able to communicate with each other. The abstract and background section of the Qian reference teaches the industry need for ease of communication in multi-die packages with interconnects between dies. The embodiments disclosed in the Qian reference are specifically designed to provide enhanced functionality, improved performance, and improved yield at advanced processing nodes, die disaggregation into multiple chiplets.
Therefore, it would have been further obvious to one having ordinary skill in the art at the time the invention was filed to include a third and fourth die in the device of Qian so as to ensure proper alignment and connection of the chip's electrical contacts to a multiple die package, enabling the functionality of the semiconductor device, such as in the device of Mathuriya.
Also, the Applicants Fig. 4A and 4B appear to show signal routing paths extending between corresponding ones of the electrical contact structures for “all”, “some”, and “a portion” of the RX and TX circuits. The Applicants Figs 4A and 4B are similar to the Fig. 3A in the Qian reference, which show signal routing paths extending between corresponding ones of the electrical contact structures for “all”, “some”, and “a portion” of the RX and TX circuits.)
As to claim(s) 12 and 13, the semiconductor package of claim 11, wherein
the portion of the RX circuits includes
1
2
of the RX circuits, and the portion of the TX circuits includes
1
2
of the TX circuits (¶ 0038 - ¶ 0042, Qian).
the portion of the RX circuits includes
1
4
of the RX circuits, and the portion of the TX circuits (obvious) includes
1
4
of the TX circuits(¶ 0038 - ¶ 0042, Qian).
(Regarding claim(s) 12 and 13, as combined, Qian and Mathuriya teach the limitations of claims 12 and 13. See Examiner’s remarks for claims 4, above regarding claims 12 and 13. )
As to claim(s) 14, the semiconductor package of claim 11, wherein,
for individual ones of the dies, the RX circuits are at a first region (See 1st region Annotated Quin Fig. 3C, below) of the die, and the TX circuits are at a second region (See 2nd region Annotated Quin Fig. 3C, below) of the die different from the first region.
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361
549
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(Regarding claim(s) 14, as combined, Qian and Mathuriya teach the limitations of claim 14.)
As to claim(s) 15, the semiconductor package of claim 11, wherein,
for individual ones of the dies, the signal routing paths include electrically conductive traces (¶ 0037, “ In an embodiment, the package substrate 382 comprises layers of insulative material surrounding conductive traces”) and vias (obvious) of the die).
(Regarding claim(s) 15, as combined, Qian and Mathuriya teach the limitations of claim 15. Though Qian does teach traces of the package substrate(382), Qian does not explicitly teach vias of the die. It would have been obvious that the package of Qian includes vias since it is known in the industry that interconnects (383), such as described in ¶ 0036 of Qian, would include vias. The traces of the Qian device are not shown (See ¶ 0037, Qian). In an electronic interconnect, traces are the conductors that carry electrical signals between components, while vias provide electrical connections between different lay