Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-7 and 22-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2022/0223530) in view of Yu et al. (US 2021/0091084).
As for claims 1 and 27, Yu et al. disclose in Figs. 1A-1E and the related text a apparatus, comprising:
a first level structure (tier 2), wherein the first level structure comprises a first integrated circuit device (left LD) and a second integrated circuit device (middle LD), the first integrated circuit device and the second integrated circuit device of the first level structure each comprise integrated circuitry 20B, routing layers 124B over the integrated circuitry, the routing layers 124B at a frontside (upper) surface, external interconnects 28 over the routing layers and on the frontside surface (Fig. 1A), and through vias 26B extending from the routing layers to a backside (lower) surface (of 20B) opposite the routing layers front side surface (Fig. 1A), and wherein the external interconnects 28 are comprise solder balls [0032] to couple directly to an underlying carrier substrate (tier 3, Fig. 1A); and
a second level structure (tier 1) over the first level structure (Fig. 1A), wherein the second level structure comprises a first/third integrated circuit device MD1 hybrid bonded to the backside surface and within a perimeter of the backside surface of the first integrated circuit device of the first level structure (Fig. 1A) and a bridge hybrid BD bonded to the backside surface of the first integrated circuit device of the first level structure and hybrid bonded to the backside surface of the second integrated circuit device of the first level structure (Fig. 1A), the first/third integrated circuit device MD1 of the second level structure comprises integrated circuitry 20A, routing layers 124A over the integrated circuitry, the routing layers at a frontside (upper) surface, and a backside (lower) surface opposite the routing layers frontside surface and opposite the hybrid bond to the first integrated circuit device of the first level structure to form a face-to-back bond therebetween (Fig. 1A), the bridge BD comprises routing layers 124A and a backside (lower) surface opposite the routing layers frontside surface and opposite the hybrid bond to the first integrated circuit device and the second integrated circuit device of the first level structure to form face-to- back bonds therebetween (Fig. 1A), the first/third integrated circuit device (left MD1) of the second level structure and the bridge (BD) are each laterally smaller than both the first integrated circuit device (left LD) and the second integrated circuit device (middle LD) of the first level structure, and the bridge BD is absent any direct connection to couple to the underlying carrier substrate (tier 3) (Fig. 1).
Yu et al. do not disclose the through vias extending from the routing layers to a backside surface opposite the routing layers front side surface.
Yu et al. discloses in Fig. 3A-3B and the related text through vias 309 extending from the routing layers to a backside (lower) surface opposite the routing layers front side (upper) surface.
Yu et al. and Yu et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Yu et al. to include the limitations as taught by Yu et al., in order to improve interconnections.
As for claims 4 and 28, Yu et al. disclose the apparatus of claim 1, wherein the backside (lower) surface of the first/third integrated circuit device MD1 of the second level structure (tier 1) is planar with the backside (lower) surface of the bridge BD of the second level structure (Fig. 1A).
As for claims 5 and 29, Yu et al. disclose the apparatus of claim 1, further comprising: a second/fourth integrated circuit device (middle MD1) in the second level structure hybrid bonded to the backside surface of the second integrated circuit device (middle LD) of the first level structure (Fig. 1A), wherein the second/fourth integrated circuit device (middle MD1) of the second level structure comprises integrated circuitry 20A, routing layers 124A over the integrated circuitry, and a backside (lower) surface opposite the routing layers and the hybrid bond to the second integrated circuit device of the first level structure.
As for claims 4 and 28, Yu et al. disclose the apparatus of claim 5, wherein the second/fourth integrated circuit device (middle MD1) of the second level structure is within a perimeter of the backside surface of the second integrated circuit device (middle LD) of the first level structure (Fig. 1A).
As for claims 7 and 31, Yu et al. disclose the apparatus of claim 5, wherein the backside surface of the first/third integrated circuit device (left MD1) of the second level structure is planar with the backside surface of the second/fourth integrated circuit device (middle MD1) of the second level structure (fig. 1A).
As for claims 22 and 32, Yu et al. disclose the apparatus of claim 1, wherein the hybrid bonds between the first/third integrated circuit device of the second level structure and the first integrated circuit device of the first level structure, between the bridge and the first integrated circuit device of the first level structure, and between the bridge and the second/fourth integrated circuit device of the first level structure are face-to-back hybrid bonds (Fig. 1A).
As for claims 23 and 33, Yu et al. disclose the apparatus of claim 1, wherein the bridge BD further comprises integrated circuitry 20A between the routing layers and the backside surface of the bridge (Fig. 1A).
As for claims 24 and 34, Yu et al. disclose the apparatus of claim 1, wherein the bridge is a passive bridge comprising silicon ([0022]-[0023]).
As for claims 25 and 35, Yu et al. disclose the apparatus of claim 1, further comprising the underlying carrier substrate (tier 3) coupled to the external interconnects 28 of the first integrated circuit device and the second integrated circuit device (Fig. 1A).
As for claims 26 and 36, Yu et al. disclose the apparatus of claim 25, further comprising: a board 134; and an integrated circuit package MD3 electrically attached to the board, the integrated circuit package comprising the underlying carrier substrate 20C, the first level structure, and the second level structure (Fig. 1A).
Response to Arguments
Applicant’s arguments with respect to claim(s) above have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TRANG Q TRAN/ Primary Examiner, Art Unit 2811
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