Prosecution Insights
Last updated: July 17, 2026
Application No. 17/825,340

INTEGRATED CIRCUIT ASSEMBLIES HAVING INTERCONNECTION BRIDGES SPANNING INTEGRATED CIRCUIT DEVICES THEREIN

Non-Final OA §103
Filed
May 26, 2022
Examiner
TRAN, TRANG Q
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
3 (Non-Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
590 granted / 728 resolved
+13.0% vs TC avg
Moderate +7% lift
Without
With
+7.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
31 currently pending
Career history
768
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
77.5%
+37.5% vs TC avg
§102
16.7%
-23.3% vs TC avg
§112
4.4%
-35.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 728 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 4-7, 22-23, 25-33 and 35-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhai (US 2021/0125967) in view of Kim (US 2015/0113195). As for claim 1, Zhai discloses in fig. 1A and 7 (as view upside down) and the related text an apparatus, comprising: a first level structure, wherein the first level structure comprises a first integrated circuit device 130 and a second integrated circuit device 120, the first integrated circuit device 130 and the second integrated circuit device 120 of the first level structure each comprise integrated circuitry (lower portion of 130/120), routing layers 102/104 over the integrated circuitry (Fig. 7), external interconnects 172 over the routing layers, and through vias 170 extending to a backside surface opposite the routing layers (Fig. 7), and wherein the external interconnects 172 are to couple directly to an underlying carrier substrate 100; and a second level structure over the first level structure, wherein the second level structure comprises a first integrated circuit device 240 hybrid bonded to and within a perimeter of the backside surface of the first integrated circuit device of the first level structure and a bridge 230 hybrid bonded to the backside surface of the first integrated circuit device 130 of the first level structure and hybrid bonded to the backside surface of the second integrated circuit device 120 of the first level structure (Fig. 7), the first integrated circuit device 240 of the second level structure comprises integrated circuitry (upper portion of 240), routing layers 202/204 over the integrated circuitry, and a backside surface opposite the routing layers and the hybrid bond to the first integrated circuit device 130 of the first level structure (Fig. 7), the bridge 230 comprises routing layers 202/204 and a backside surface opposite the routing layers and the hybrid bond to the first integrated circuit device 130 and the second integrated circuit device 120 of the first level structure (Fig. 7), the first integrated circuit device 240 of the second level structure and the bridge 230 are each laterally smaller than both the first integrated circuit device 130 and the second integrated circuit device 120 of the first level structure (Fig. 7), and the bridge 230 is absent any direct connection to couple to the underlying carrier substrate (Fig. 7). Zhai et al. do not disclose through vias extending from the routing layers. Kim disclose in Fig. 4 and the related text through vias 60d extending from the routing layers 31a. Zhai et al. and Kim are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zhai et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Zhai et al. to include the limitations as taught by Kim in order to improve interconnections. As for claim 4, Zhai discloses the apparatus of claim 1, wherein the backside surface of the first integrated circuit device 240 of the second level structure is planar with the backside surface of the bridge 230 of the second level structure (fig. 7). As for claim 5, Zhai discloses the apparatus of claim 1, further comprising: a second integrated circuit device 220 in the second level structure hybrid bonded to the backside surface of the second integrated device 120 of the first level structure [0021], wherein the second integrated circuit device 220 of the second level structure comprises integrated circuitry (upper portion of 220), routing layers 202/204 over the integrated circuitry (Fig. 7), and a backside (upper) surface opposite the routing layers and the hybrid bond to the second integrated circuit device 120 of the first level structure (Fig. 7, [0021]). As for claim 6, Zhai discloses the apparatus of claim 5, wherein the second integrated circuit device 220 of the second level structure is within a perimeter of the backside surface of the second integrated circuit device 120 of the first level structure (Fig. 7). As for claim 7, Zhai discloses the apparatus of claim 5, wherein the backside surface of the first integrated circuit device 240 of the second level structure is planar with the backside surface of the second integrated circuit device 220 of the second level structure (Fig. 7). As for claim 22, Zhai discloses the apparatus of claim 1, wherein the hybrid bonds between the first integrated circuit device 240 of the second level structure and the first integrated circuit device 130 of the first level structure, between the bridge 230 and the first integrated circuit device 130 of the first level structure, and between the bridge 230 and the second integrated circuit device 120 of the first level structure are face-to-back hybrid bonds (Fig. 7, [0021]). As for claim 23, Zhai discloses the apparatus of claim 1, wherein the bridge 230 further comprises integrated circuitry (upper portion of 230) between the routing layers 202/204 and the backside surface of the bridge (Fig. 7). As for claim 25, Zhai discloses the apparatus of claim 1, further comprising the underlying carrier substrate 100/(upper 125) coupled to the external interconnects 172 of the first integrated circuit device and the second integrated circuit device (fig. 7). As for claim 26, Zhai discloses the apparatus of claim 25, further comprising: aboard (upper 115); and an integrated circuit package electrically attached to the board (Fig. 7), the integrated circuit package comprising the underlying carrier substrate (upper 125), the first level structure, and the second level structure (fig. 7). As for claim 27, Zhai discloses in fig. 1A and 7 (as view upside down) and the related text an apparatus, comprising: a first integrated circuit device 130 and a second integrated circuit device 120 in a first level, the first integrated circuit device 130 and the second integrated circuit device 120 comprising integrated circuitry (lower portion of 130/120), routing layers 102/104 over the integrated circuitry, external interconnects 172 over the routing layers 102/104, and through vias 170 extending to a backside surface opposite the routing layers (Fig. 7), and wherein the external interconnects 172 are to couple directly to an underlying carrier substrate 100; and a third integrated circuit device 240 and a bridge 230 in a second level, the third integrated circuit device 240 hybrid bonded to and within a perimeter of the backside surface of the first integrated circuit device 130 (Fig. 7, [0021]), and the bridge 230 hybrid bonded to the backside surface of the first integrated circuit device 130 and hybrid bonded to the backside surface of the second integrated circuit device 120 (Fig. 7, [0021]), wherein the third integrated circuit device 240 comprises integrated circuitry (upper portion of 240), routing layers 202/204 over the integrated circuitry, and a backside surface opposite the routing layers and the hybrid bond to the first integrated circuit device (Fig. 7, [0021]), the bridge 230 comprises routing layers (upper portion of 230) and a backside surface opposite the routing layers and the hybrid bond to the first integrated circuit device and the second integrated circuit device (Fig. 7, [0021]), the third integrated circuit device 240 and the bridge 230 are each laterally smaller than both the first integrated circuit device 130 and the second integrated circuit device 120, and the bridge 230 is absent any direct connection to couple to the underlying carrier substrate (Fig. 7). As for claim 28, Zhai discloses the apparatus of claim 27, wherein the backside surface of the third integrated circuit device 240 is planar with the backside surface of the bridge 230 (Fig. 7). As for claim 29, Zhai discloses the apparatus of claim 27, further comprising: a fourth integrated circuit device 220/210 in the second level hybrid bonded to the backside surface of the second integrated circuit device 120 (Fig. 7, [0021]), wherein the fourth integrated circuit device 220/210 comprises integrated circuitry (lower portion of 220), routing layers 202/204 over the integrated circuitry, and a backside surface opposite the routing layers and the hybrid bond to the second integrated circuit device (Fig. 7, [0021]). As for claim 30, Zhai discloses the apparatus of claim 29, wherein the fourth integrated circuit device 220/210 is within a perimeter of the backside surface of the second integrated circuit device 120 (Fig. 7). As for claim 31, Zhai discloses the apparatus of claim 29, wherein the backside surface of the third integrated circuit device 240 is planar with the backside surface of the fourth integrated circuit device 220/210 (Fig. 7). As for claim 32, Zhai discloses the apparatus of claim 27, wherein the hybrid bonds between the third integrated circuit device 240 and the first integrated circuit device 130, between the bridge 230 and the first integrated circuit device 130, and between the bridge 230 and the second integrated circuit device 120 are face-to-back As for claim 33, Zhai discloses the apparatus of claim 27, wherein the bridge 230 further comprises integrated circuitry (upper portion 230) between the routing layers 202/204 and the backside surface of the bridge (Fig. 7). As for claim 35, Zhai discloses the apparatus of claim 27, further comprising the underlying carrier substrate 100 coupled to the external interconnects 172 of the first integrated circuit device 130 and the second integrated circuit device 120 (Fig. 7). As for claim 36, Zhai discloses the apparatus of claim 35, further comprising: aboard (upper 125); and an integrated circuit package electrically attached to the board, the integrated circuit package comprising the underlying carrier substrate, the first level, and the second level (Fig. 7). Claim(s) 24 and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhai in view of Strong et al. and further in view of Chang et al. (US 2016/0093597). As for claims 24 and 34, Zhai and Strong et al. disclosed the apparatus of claim 1 and 27, except the bridge is a passive bridge comprising silicon. Chang et al. teach in Fig. 15 and the related text a bridge 206 is a passive bridge comprising silicon [0021]. Zhai, Strong et al. and Chang et al. are analogous art because they both are directed packaging device and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include the limitations as taught by Chang et al., in order to provide electrical communication between two or more dies bonded thereon (Chang et al. [0020]). Response to Arguments Applicant’s arguments with respect to claim(s) above have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached Monday-Thursday (9am-4pm). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TRANG Q TRAN/ Primary Examiner, Art Unit 2811
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Prosecution Timeline

Show 1 earlier event
Feb 09, 2023
Response after Non-Final Action
Jul 29, 2025
Non-Final Rejection mailed — §103
Oct 29, 2025
Response Filed
Feb 06, 2026
Final Rejection mailed — §103
Apr 06, 2026
Response after Non-Final Action
Apr 27, 2026
Request for Continued Examination
Apr 29, 2026
Response after Non-Final Action
May 12, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685191
INTERPOSER VIA INTERCONNECT SHAPES WITH IMPROVED PERFORMANCE CHARACTERISTICS AND METHODS OF FORMING THE SAME
4y 2m to grant Granted Jul 14, 2026
Patent 12685225
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
3y 1m to grant Granted Jul 14, 2026
Patent 12677681
ELECTRONIC PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
4y 7m to grant Granted Jul 07, 2026
Patent 12672576
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
4y 1m to grant Granted Jun 30, 2026
Patent 12667000
Semiconductor Device that Uses Bonding Layer to Join Semiconductor Substrates Together
4y 10m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
88%
With Interview (+7.1%)
2y 8m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 728 resolved cases by this examiner. Grant probability derived from career allowance rate.

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