DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 6-7, 8, 9, 10, 12, and 26-27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Strong et al. (US pat 11133263).
With respect to claim 1, Strong et al. teach an apparatus, comprising (see figs. 1-29, particularly fig. 1 and associated text):
a first level structure (level includes 120, IC 1801 and IC 1802), wherein the first level structure comprises a monolithic active device comprising a monolithic substrate (supporting structure) 190 (the structure between 120 and 310), the monolithic active device comprising a first reticle zone (area of IC 1801) comprising first integrated circuitry (within IC 1801) of the monolithic active device on the monolithic substrate, and a second reticle zone (area of IC 1802) comprising second integrated circuitry (within IC 1802) of the monolithic active device on the monolithic substrate comprising a single material structure (molding 190); and
a second level structure (level includes 3301, 3302, 3303), wherein the second level structure comprises an integrated circuit device 3301 and a bridge 3302 electrically attached to the first integrated circuitry of the first reticle zone of the monolithic active device and the bridge 3302 electrically attached to the first integrated circuitry of the first reticle zone of the monolithic active device and the second integrated circuitry of the second reticle zone of the monolithic active device.
With respect to claim 2, Strong et al. teach the monolithic active device further comprises a boundary zone (the area between IC 1801 and IC 1802) between the first reticle zone and the second reticle zone, the bridge is positioned over the boundary zone, and the boundary zone comprises a guard ring (the molding 190 between 1801 and 1802). See fig. 1 and associated text.
With respect to claim 6, Strong et al. teach a backside surface (top) of the integrated circuit device is planar with a backside surface (top) of the bridge. See fig. 1 and associated text.
With respect to claim 7, Strong et al. teach a second integrated device 3303 electrically attached to the second integrated circuitry of the second reticle zone of the monolithic active device. See fig. 1 and associated text.
With respect to claim 8, Strong et al. teach external interconnects 194 attached to the monolithic active device, wherein the external interconnects are electrically attached to the first integrated circuitry of the first reticle zone and the second integrated circuitry of the second reticle zone with a plurality of through-silicon vias 188 extending through the monolithic active device. See fig. 1 and associated text.
With respect to claim 9, Strong et al. teach the monolithic active device comprises first routing layers (connectors right above 342 on left) over the first integrated circuitry and second routing layers (connectors right above 342 on right) over the second integrated circuitry, the first routing layers separated from the second routing layers by dielectric material (3121-4). See fig. 1 and associated text.
With respect to claim 10, Strong et al. teach a plurality of external interconnects (bumps under 3301, 3302, 3303) attached to the second level structure. See fig. 1 and associated text.
With respect to claim 12, Strong et al. teach a mold material (darkened material around 3501, 3502) abutting the integrated circuit device and the bridge. See fig. 1 and 5 and associated text.
With respect to claim 26, Strong et al. teach a carrier substrate (120, 160, 140); and an integrated circuit package electrically attached to the carrier substrate, wherein the integrated circuit package comprises the first level structure and the second level structure. See fig. 1 and 5 and associated text.
With respect to claim 27, Strong et al. teach a board electrically attached to the carrier substrate. See fig. 1 and 5 and associated text and col. 3, lines 25-35.
Claim(s) 28, 29, 31-33, 35, and 37-39 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Strong et al. (US pat 11133263).
With respect to claim 28, Strong et al. teach an apparatus, comprising (see figs. 1-29, particularly fig. 1 and associated text):
a first level structure (level includes 120, IC 1801 and IC 1802) comprising a monolithic active device (the structure between 120 and 310), the monolithic active device comprising a monolithic substrate (supporting structure) 190, first integrated circuitry (within IC 1801) on the monolithic substrate defined by a first reticle zone (area of IC 1801) and a second integrated circuitry (within IC 1802) on the monolithic substrate defined by a second reticle zone (area of IC 1802), the monolithic substrate comprising a single material structure (molding 190); and
a second level structure (level includes 3301, 3302, 3303) comprising an integrated circuit device 3301 and a bridge 3302, the integrated circuit device electrically attached to the first integrated circuitry of the monolithic active device and the bridge electrically attached to the first integrated circuitry of the monolithic active device and electrically attached to the second integrated circuitry of the second reticle zone of the monolithic active device.
With respect to claim 29, Strong et al. teach the monolithic active device further comprises a boundary zone (the area between IC 1801 and IC 1802) between the first reticle zone and the second reticle zone, the bridge is positioned over the boundary zone, the boundary zone comprises a guard ring (the molding 190 between 1801 and 1802). See fig. 1 and associated text.
With respect to claim 31, Strong et al. teach a backside surface (top) of the integrated circuit device is planar with a backside surface (top) of the bridge. See fig. 1 and associated text.
With respect to claim 32, Strong et al. teach a second integrated device 3303 electrically attached to the second integrated circuitry of the second reticle zone of the monolithic active device. See fig. 1 and associated text.
With respect to claim 33, Strong et al. teach external interconnects 194 attached to the monolithic active device, wherein the external interconnects are electrically attached to the first integrated circuitry of the first reticle zone and the second integrated circuitry of the second reticle zone with a plurality of through-silicon vias 188 extending through the monolithic active device. See fig. 1 and associated text.
With respect to claim 35, Strong et al. teach a plurality of external interconnects (bumps under 3301, 3302, 3303) attached to the second level structure. See fig. 1 and associated text.
With respect to claim 37, Strong et al. teach a mold material (darkened material around 3501, 3502) abutting the integrated circuit device and the bridge. See fig. 1 and 5 and associated text.
With respect to claim 38, Strong et al. teach a carrier substrate (120, 160, 140); and an integrated circuit package electrically attached to the carrier substrate, wherein the integrated circuit package comprises the first level structure and the second level structure. See fig. 1 and 5 and associated text.
With respect to claim 39, Strong et al. teach a board electrically attached to the carrier substrate. See fig. 1 and 5 and associated text and col. 3, lines 25-35.
Claim(s) 28, 30, 33, 34, 35 and 36 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhai (US pub 20210125967).
With respect to claim 28, Zhai teaches an apparatus, comprising (see figs. 1-7, particularly fig. 7 and associated text):
a first level structure (level including 210, 220, 230, 240) comprising a monolithic active device (the structure cover 210, 220, 230, 240), the monolithic active device comprising a monolithic substrate (supporting structure) 206, first integrated circuitry 210 on the monolithic substrate defined by a first reticle zone (area of IC 210) and a second integrated circuitry 230 on the monolithic substrate defined by a second reticle zone (area of 230), the monolithic substrate comprising a single material structure 206; and
a second level structure (level including 110, 120, 130) comprising an integrated circuit device (left part of 120) and a bridge (right part of 120), the integrated circuit device electrically attached to the first integrated circuitry of the monolithic active device and the bridge electrically attached to the first integrated circuitry of the monolithic active device and electrically attached to the second integrated circuitry of the second reticle zone of the monolithic active device.
With respect to claim 30, Zhai teaches the bridge comprises a portion of the integrated circuit device. See fig. 7 and associated text.
With respect to claim 33, Zhai teaches a plurality of external interconnects 180 attached to the monolithic active device. See fig. 7 and associated text.
With respect to claim 34, Zhai teaches the monolithic active device comprises first routing layers (102,202 left) over the first integrated circuitry and second routing layers (102,202 right) over the second integrated circuitry, the first routing layers separated from the second routing layers by dielectric material 104,204. See fig. 7 and associated text.
With respect to claim 35, Zhai teaches a plurality of external interconnects 180 attached to the second level structure. See fig. 7 and associated text.
With respect to claim 36, Zhai teaches the external interconnects are electrically attached to the integrated circuit device with a plurality of through-silicon vias 170 extending through the integrated circuit device. See fig. 7 and associated text.
Claim(s) 1, 3, 8, 9, 10, 11, 12, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhai (US pub 20210125967).
With respect to claim 1, Zhai teaches an apparatus, comprising (see figs. 1-7, particularly fig. 7 and associated text):
a first level structure (level including 210, 220, 230, 240), wherein the first level structure comprises a monolithic active device (the structure cover 210, 220, 230, 240), the monolithic active device comprising a monolithic substrate 206, a first reticle zone (area of IC 210) comprising first integrated circuitry 210 of the monolithic active device on the monolithic substrate, and a second reticle zone (area of 230) comprising second integrated circuitry 230 of the monolithic active device on the monolithic substrate, the monolithic substrate comprising a single material structure 206; and
a second level structure (level including 110, 120, 130), wherein the second level structure comprises an integrated circuit device (left part of 120) and a bridge (right part of 120)electrically attached to the first integrated circuitry of the first reticle zone of the monolithic active device and the bridge electrically attached to the first integrated circuitry of the first reticle zone of the monolithic active device and the second integrated circuitry of the second reticle zone of the monolithic active device.
With respect to claim 3, Zhai teaches the bridge comprises a portion of the integrated circuit device. See fig. 7 and associated text.
With respect to claim 8, Zhai teaches external interconnects 180 attached to the monolithic active device, wherein the external interconnects are electrically attached to the first integrated circuitry of the first reticle zone and the second integrated circuitry of the second reticle zone with a plurality of through-silicon vias 270 extending through the monolithic active device. See fig. 7 and associated text.
With respect to claim 9, Zhai teaches the external interconnects are electrically attached to the first integrated circuitry of the first reticle zone and the second integrated circuitry of the second reticle zone with a plurality of through-silicon vias 270 extending through the monolithic active device. See fig. 7 and associated text.
With respect to claim 9, Zhai teaches the monolithic active device comprises first routing layers (102,202 left) over the first integrated circuitry and second routing layers (102,202 right)) over the second integrated circuitry, the first routing layers separated from the second routing layers by dielectric material 206. See fig. 7 and associated text.
With respect to claim 10, Zhai teaches a plurality of external interconnects 180 attached to the second level structure. See fig. 7 and associated text.
With respect to claim 11, Zhai teaches the external interconnects are electrically attached to the integrated circuit device with a plurality of through-silicon vias 170 extending through the integrated circuit device. See fig. 7 and associated text.
With respect to claim 12, Zhai teaches a mold material (the material covering over, between, and below 110, 120, 130) abutting the integrated circuit device and the bridge. See fig. 7 and associated text.
With respect to claim 13, Zhai teaches a through-mold via (connectors between 120 and 210 and 230 and 120) extending through the mold material and electrically attaching the external interconnects to the monolithic active device. See fig. 7 and associated text.
Response to Arguments
Applicant's arguments filed 7/28/26 have been fully considered but they are not persuasive. See the above rejections.
Conclusion
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LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897
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