Prosecution Insights
Last updated: July 17, 2026
Application No. 17/825,350

INTEGRATED CIRCUIT ASSEMBLIES HAVING INTERCONNECTION BRIDGES SPANNING RETICLE BOUNDARY / DICING STREETS OF MONOLITHIC STRUCTURES THEREIN

Final Rejection §102
Filed
May 26, 2022
Examiner
PHAM, LONG
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Final)
92%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1515 granted / 1655 resolved
+23.5% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
38 currently pending
Career history
1688
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.5%
+16.5% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1655 resolved cases

Office Action

§102
CTFR 17/825,350 CTFR 69602 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 2, 6-7, 8, 10, and 12 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Strong et al. (US pat 11133263) . With respect to claim 1, Strong et al. teach an apparatus, comprising (see figs. 1-29, particularly fig. 1 and associated text): a first level structure (level includes 120, IC 180 1 and IC 180 2 ), wherein the first level structure comprises a monolithic active device (the structure between 120 and 310), the monolithic active device comprising a first reticle zone (area of IC 180 1 ) comprising first integrated circuitry (within IC 180 1 ) of the monolithic active device, and a second reticle zone (area of IC 180 2 ) comprising second integrated circuitry (within IC 180 2 ) of the monolithic active device ; and a second level structure (level includes 330 1 , 330 2 , 330 3 ), wherein the second level structure comprises an integrated circuit device 330 1 and a bridge 330 2 electrically attached to the first integrated circuitry of the first reticle zone of the monolithic active device and the bridge 330 2 electrically attached to the first integrated circuitry of the first reticle zone of the monolithic active device and the second integrated circuitry of the second reticle zone of the monolithic active device . With respect to claim 2, Strong et al. teach the monolithic active device further comprises a boundary zone (the area between IC 180 1 and IC 180 2 ) between the first reticle zone and the second reticle zone and wherein the bridge is positioned over the boundary zone. See fig. 1 and associated text. With respect to claim 6, Strong et al. teach a backside surface (top) of the integrated circuit device is planar with a backside surface (top) of the bridge. See fig. 1 and associated text. With respect to claim 7, Strong et al. teach a second integrated device 330 3 electrically attached to the second integrated circuitry of the second reticle zone of the monolithic active device . See fig. 1 and associated text. With respect to claim 8, Strong et al. teach a plurality of external interconnects 194 attached to the monolithic active device . See fig. 1 and associated text. With respect to claim 10, Strong et al. teach a plurality of external interconnects (bumps under 330 1 , 330 2 , 330 3 ) attached to the second level structure. See fig. 1 and associated text. With respect to claim 12, Strong et al. teach a mold material (darkened material around 350 1 , 350 2 ) abutting the integrated circuit device and the bridge. See fig. 1 and 5 and associated text. With respect to claim 26, Strong et al. teach a carrier substrate (120, 160, 140); and an integrated circuit package electrically attached to the carrier substrate, wherein the integrated circuit package comprises the first level structure and the second level structure. See fig. 1 and 5 and associated text. With respect to claim 27, Strong et al. teach a board electrically attached to the carrier substrate. See fig. 1 and 5 and associated text and col. 3, lines 25-35 . 07-15-aia AIA Claim(s) 28, 29, 31-33, 35, and 37-39 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Strong et al. (US pat 11133263) . With respect to claim 28, Strong et al. teach an apparatus, comprising (see figs. 1-29, particularly fig. 1 and associated text): a first level structure (level includes 120, IC 180 1 and IC 180 2 ) comprising a monolithic active device (the structure between 120 and 310), the monolithic active device comprising first integrated circuitry (within IC 180 1 ) defined by a first reticle zone (area of IC 180 1 ) and a second integrated circuitry (within IC 180 2 ) defined by a second reticle zone (area of IC 180 2 ); and a second level structure (level includes 330 1 , 330 2 , 330 3 ) comprising an integrated circuit device 330 1 and a bridge 330 2 , the integrated circuit device electrically attached to the first integrated circuitry of the monolithic active device and the bridge electrically attached to the first integrated circuitry of the monolithic active device and electrically attached to the second integrated circuitry of the second reticle zone of the monolithic active device. With respect to claim 29, Strong et al. teach the monolithic active device further comprises a boundary zone (the area between IC 180 1 and IC 180 2 ) between the first reticle zone and the second reticle zone and wherein the bridge is positioned over the boundary zone. See fig. 1 and associated text. With respect to claim 31, Strong et al. teach a backside surface (top) of the integrated circuit device is planar with a backside surface (top) of the bridge. See fig. 1 and associated text. With respect to claim 32, Strong et al. teach a second integrated device 330 3 electrically attached to the second integrated circuitry of the second reticle zone of the monolithic active device. See fig. 1 and associated text. With respect to claim 33, Strong et al. teach a plurality of external interconnects 194 attached to the monolithic active device. See fig. 1 and associated text. With respect to claim 35, Strong et al. teach a plurality of external interconnects (bumps under 330 1 , 330 2 , 330 3 ) attached to the second level structure. See fig. 1 and associated text. With respect to claim 37, Strong et al. teach a mold material (darkened material around 350 1 , 350 2 ) abutting the integrated circuit device and the bridge. See fig. 1 and 5 and associated text. With respect to claim 38, Strong et al. teach a carrier substrate (120, 160, 140); and an integrated circuit package electrically attached to the carrier substrate, wherein the integrated circuit package comprises the first level structure and the second level structure. See fig. 1 and 5 and associated text. With respect to claim 39, Strong et al. teach a board electrically attached to the carrier substrate. See fig. 1 and 5 and associated text and col. 3, lines 25-35 . 07-15-aia AIA Claim(s) 28, 30, 33, 34, 35 and 36 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Zhai (US pub 20210125967) . With respect to claim 28, Zhai teaches an apparatus, comprising (see figs. 1-7, particularly fig. 7 and associated text): a first level structure (level including 210, 220, 230, 240) comprising a monolithic active device (the structure cover 210, 220, 230, 240), the monolithic active device comprising first integrated circuitry 210 defined by a first reticle zone (area of IC 210) and a second integrated circuitry 230 defined by a second reticle zone (area of 230); and a second level structure (level including 110, 120, 130) comprising an integrated circuit device (left part of 120) and a bridge (right part of 120), the integrated circuit device electrically attached to the first integrated circuitry of the monolithic active device and the bridge electrically attached to the first integrated circuitry of the monolithic active device and electrically attached to the second integrated circuitry of the second reticle zone of the monolithic active device. With respect to claim 30, Zhai teaches the bridge comprises a portion of the integrated circuit device. See fig. 7 and associated text. With respect to claim 33, Zhai teaches a plurality of external interconnects 180 attached to the monolithic active device. See fig. 7 and associated text. With respect to claim 34, Zhai teaches the external interconnects are electrically attached to the first integrated circuitry of the first reticle zone and the second integrated circuitry of the second reticle zone with a plurality of through-silicon vias 270 extending through the monolithic active device. See fig. 7 and associated text. With respect to claim 35, Zhai teaches a plurality of external interconnects 180 attached to the second level structure. See fig. 7 and associated text. With respect to claim 36, Zhai teaches the external interconnects are electrically attached to the integrated circuit device with a plurality of through-silicon vias 170 extending through the integrated circuit device. See fig. 7 and associated text . 07-15-aia AIA Claim(s) 1, 3, 8, 9, 10, 11, 12, and 13 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Zhai (US pub 20210125967) . With respect to claim 1, Zhai teaches an apparatus, comprising (see figs. 1-7, particularly fig. 7 and associated text): a first level structure (level including 210, 220, 230, 240), wherein the first level structure comprises a monolithic active device (the structure cover 210, 220, 230, 240), the monolithic active device comprising a first reticle zone (area of IC 210) comprising first integrated circuitry 210 of the monolithic active device, and a second reticle zone (area of 230) comprising second integrated circuitry 230 of the monolithic active device; and a second level structure (level including 110, 120, 130), wherein the second level structure comprises an integrated circuit device (left part of 120) and a bridge (right part of 120)electrically attached to the first integrated circuitry of the first reticle zone of the monolithic active device and the bridge electrically attached to the first integrated circuitry of the first reticle zone of the monolithic active device and the second integrated circuitry of the second reticle zone of the monolithic active device. With respect to claim 3, Zhai teaches the bridge comprises a portion of the integrated circuit device. See fig. 7 and associated text. With respect to claim 8, Zhai teaches a plurality of external interconnects 180 attached to the monolithic active device. See fig. 7 and associated text. With respect to claim 9, Zhai teaches the external interconnects are electrically attached to the first integrated circuitry of the first reticle zone and the second integrated circuitry of the second reticle zone with a plurality of through-silicon vias 270 extending through the monolithic active device. See fig. 7 and associated text. With respect to claim 10, Zhai teaches a plurality of external interconnects 180 attached to the second level structure. See fig. 7 and associated text. With respect to claim 11, Zhai teaches the external interconnects are electrically attached to the integrated circuit device with a plurality of through-silicon vias 170 extending through the integrated circuit device. See fig. 7 and associated text. With respect to claim 12, Zhai teaches a mold material (the material covering over, between, and below 110, 120, 130) abutting the integrated circuit device and the bridge. See fig. 7 and associated text. With respect to claim 13, Zhai teaches a through-mold via (connectors between 120 and 210 and 230 and 120) extending through the mold material and electrically attaching the external interconnects to the monolithic active device. See fig. 7 and associated text . Response to Arguments 07-37 AIA Applicant's arguments filed 2/17/26 have been fully considered but they are not persuasive. See the above rejection . THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/ Primary Examiner, Art Unit 2897 Application/Control Number: 17/825,350 Page 2 Art Unit: 2897 Application/Control Number: 17/825,350 Page 3 Art Unit: 2897 Application/Control Number: 17/825,350 Page 4 Art Unit: 2897 Application/Control Number: 17/825,350 Page 5 Art Unit: 2897 Application/Control Number: 17/825,350 Page 6 Art Unit: 2897 Application/Control Number: 17/825,350 Page 7 Art Unit: 2897 Application/Control Number: 17/825,350 Page 8 Art Unit: 2897 Application/Control Number: 17/825,350 Page 9 Art Unit: 2897 Application/Control Number: 17/825,350 Page 10 Art Unit: 2897
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Prosecution Timeline

May 26, 2022
Application Filed
Feb 09, 2023
Response after Non-Final Action
Nov 17, 2025
Non-Final Rejection mailed — §102
Feb 17, 2026
Response Filed
May 28, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.5%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1655 resolved cases by this examiner. Grant probability derived from career allowance rate.

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