Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed January 15, 2026 has been entered. Claims 5 and 20 remain pending in the application.
Response to Arguments
Applicant’s arguments, see pages 5-13 of the Remarks Made in Amendment, filed January 15, 2026 with respect to the rejection of Claims 5 and 19 have been fully considered in view of the Amendment but they are not persuasive.
The Applicant has commented upon the differences between the cited references, considered individually, as compared to the Amended claim language referred to as Features-A. For each reference applicant has listed included features, as well as the Features-A which are lacking. The Examiner will not comment upon each individual comparison, but rather on the assertion on page 12 of Remarks that a person skilled in the art would find no teaching or hint in any combination of the cited references to arrive at the Features-A.
The Examiner’s interpretation of the overall argument is that none of the individually cited references, considered alone, teaches all of the Features-A. The Examiner does not dispute this. However, the Examiner believes it has been shown that the combination of references cited includes each of the individual elements contained within the Features-A, and the Examiner maintains that it would have been obvious for a person having ordinary skill in art to have combined the known elements to arrive at Features-A. More specifically, each of surface-mount technology, wire-bonding technology, and flip-chip technology are known in the art, as is the mounting of various numbers of components comprising each of the technologies onto both sides of a substrate, and as is combining two or all three of the technologies into a single package. The Applicant appears to argue that the particular combination of elements in Features-A would not be obvious to a person having ordinary skill in the art, even though each of the elements included in Features-A is known in the art. With this, the Examiner disagrees, as explained above. Please see the updated claim rejections below.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 5 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin; Yaojian et al. (US 2016/0276258; hereinafter Lin) in view of Yang; Cheng et al. (US 10896877; hereinafter Yang), Lee; Seon H et al. (US 2022/0013370; hereinafter Lee), Pan; Ke-Hao et al. (US 2019/0044036; hereinafter Pan), Lin; Chih-Min et al. (US 2019/0051800; hereinafter Lin; Chih-Min), and Chuang; Cheng-Lung et al. (US 2010/0078747; hereinafter Chuang).
Regarding claim 5, Lin discloses a double-sided package structure manufacturing method, comprising:
partially sinking (deposited within a thickness of 204; ¶[0072]), into a temporary adhesive layer (204 and 202; Fig 5i; ¶ [0071-72]) of a first side of a master (upper side of 200; Fig 5i), electrical connection structures (164; Fig 5i; ¶ [0071-72]) comprised in at least two discrete double-sided mount structures (SoP packages 196 {comprising die 170 and package 166 on opposite sides of substrate 144; Fig 5g; ¶ [0070]}; Fig 5i; ¶ [0072]);
molding the first side of the master (with encapsulant 210; Fig 5k; ¶ [0074]) to form a molded body (214; Figs 5k-5m) encasing the at least two discrete double-sided mount structures (Fig 5k; ¶ [0074]);
removing the temporary adhesive layer to separate the master from the molded body (Fig 5m; ¶ [0076]);
and splitting the molded body to obtain the at least two discrete double-sided package structures (singulated; Fig 5q; ¶ [0086]);
wherein each of the at least two discrete double-sided mount structures comprises a substrate (144; Fig 5g; ¶ [0070]}; Fig 5i; ¶ [0072]), a first component (170; Fig 5g; ¶ [0070]}; Fig 5i; ¶ [0072]) on a first face (148; Fig 5f; ¶ [0060]) of the substrate, a fourth component (124; Figs 5b-5f; ¶ [0070]) on a second face (146; Fig 5f; ¶ [0060]) of the substrate, and an electrical connection structure of the electrical connection structures on the second face of the substrate (bumps 164; Fig 5i; ¶ [0064]); and
wherein before partially sinking, into the temporary adhesive layer of the first side of the master, the electrical connection structures comprised in the at least two discrete double-sided mount structures, the manufacturing method of the double-sided package structure further comprises:
mounting the first component onto the first face of the substrate using a surface-mount technology (as shown in Fig 5b; ¶ [0062]; SMT; ¶ [0087,0011]);
mounting the fourth component onto the second face of the substrate using the wire bonding technology (as shown in Fig 5c; ¶ [0063]); and
splitting (singulating; Fig 5g; ¶ [0069]) the substrate to obtain the each of the at least two discrete double-sided mount structures.
Lin does not disclose (1) wherein each of the electrical connection structures comprises a first solder ball, a communication carrier board and a second solder ball that are stacked together, and a depth of the second solder ball sunk into the temporary adhesive layer is greater than a radius of the second solder ball;
(2) wherein the temporary adhesive layer comprises at least one of a pyrolysis adhesive tape, a photolysis adhesive tape or a chemical etching adhesive tape, and removing the temporary adhesive layer to separate the master from the molded body comprises:
in response to the temporary adhesive layer comprising the pyrolysis adhesive tape, heating the temporary adhesive layer to separate the master from the molded body; in response to the temporary adhesive layer comprising the photolysis adhesive tape, illuminating the photolysis adhesive tape to separate the master from the molded body: or, in response to the temporary adhesive layer comprising the chemical etching tape, chemically etching the chemical etching tape to separate the master from the molded body;
(3) wherein each of the at least two discrete double-sided mount structures comprises a second component on the first face of the substrate, a third component on the first face of the substrate, a fifth component on the second face of the substrate, and;
mounting the second component onto the first face of the substrate using a wire bonding technology:
mounting the third component onto the first face of the substrate using a flip chip technology:
mounting the electrical connection structure onto the second face of the substrate using the surface-mount technology; and mounting the fifth component onto the second face of the substrate using the flip chip technology.
In the same field of endeavor, Yang discloses a similar structure comprising two discrete double-sided mount structures (202, 212; Fig 7; Col 8, lines 57-63) having electrical connection structures mounted on a first side of a master (222; Fig 7; Col 9, lines 8-22) and on a second face (210; Fig 7) of a substrate (206; Fig 7; Col 8, lines 57-63) using flip-chip technology (as the following describes), wherein each of the electrical connection structures comprises a first solder ball (218, 234; Fig 7; Col 9, lines 8-12), a communication carrier board (216, 232; Fig 7; Col 9, lines 8-22; interposers 216, 232 through the electrical connections structures of each, enable communication from 202, 212 to electrical connection points 230, that is, each of 216, 232 is a communication carrier board), and a second solder ball (220, 236; Fig 7; Col 9, lines 12-16) that are stacked together.
Accordingly, it would have been obvious to a person having ordinary skill in the art to have used the electrical connection structures of Yang in place of the electrical connection structures on the second face of the substrate of Lin (bumps 164; Fig 5i; ¶ [0064]). One would have been motivated to do this as an alternative electrical connection structure, that is, a simple substitution of one known element for another to obtain predictable results (see MPEP § 2143 I.B.), since Lin discloses in ¶ [0064] a number of alternate electrical connection (interconnect) structures that may be used. One would have had a reasonable expectation of success because of the similarity in the manufacturing methods and endeavors of Lin and Yang, and because each electrical connection structure is well-known and suitable in the art.
Neither Lin nor Yang discloses a depth of the second solder ball sunk into the temporary adhesive layer is greater than a radius of the second solder ball. However, Lin discloses that electrical connection structures (bumps 164) are deposited within a thickness of and surrounded by, a portion of the thermally releasable layer 204 (Fig 5i; ¶ [0072]). In addition, in the same field of endeavor, Lee discloses solder balls (240; Figs 4-5; ¶ [0062]) sunk into a temporary adhesive layer (release film 900; Figs 4-5; ¶ [0026-36]) to a depth greater than a radius of the solder balls 240 (as shown in Figs 5, 8). It would have been obvious to a person having ordinary skill in the art for the partially sinking of the electrical connection structures of Lin in view of Yang to be such that a depth of the second solder ball sunk into the temporary adhesive layer is greater than a radius of the second solder ball. One would have been motivated to come to this conclusion because (1) the disclosures of Lin and Lee indicate a certain depth, (2) one of ordinary skill in the art would recognize a minimum depth may be required for adequate adhesion, and (3) the depth of claim 5 may be arrived at through routine optimization (see MPEP 2144.05.II), in addition to being disclosed by Lee. One would have had a reasonable expectation of success due to the similar structures and endeavors of Lin, Yang, and Lee.
While Lin, Yang, and Lee do not specifically disclose (2), this would have been obvious to a person having ordinary skill in the art for the following reasons:
(a) Lin discloses the temporary adhesive layer (thermally releasable layer 204 and carrier tape 202) comprising the components of a pyrolysis adhesive tape, being tape and temporary adhesion enabled by thermal activation, and removing the temporary adhesive layer to separate the master (200; Fig 5l) from the molded body by activating thermally releasable layer 204 (¶ [0076]). It would have been obvious that activation of thermally releasable layer 204 to separate the master of the molded body (fully debonding and removing; ¶ [0076]) comprises heating the temporary adhesive layer. The Examiner considers this alone to satisfy the above limitation of claim 5.
(b) However, as additional or alternative interpretation, the thermally releasable layer 204 and carrier tape 202 may be considered as a simple substitution of one known element for another (“pyrolysis adhesive tape”) to obtain the predictable results (see MPEP § 2143 I.B.) of temporary adhesion, the only difference of “pyrolysis adhesive tape” of which the Examiner can conceive at present versus 202 and 204 of Lin is that “pyrolysis adhesive tape” may be a single film (temporary adhesive tape) rather than two (temporary adhesive plus tape) films. A single film is known in the art, see for example Pan (a heating process is performed to facilitate removal of pyrolysis tape 1420 {Fig 20C} to separate support plate 1410 from an LED package structure {Fig 20D}), in addition to temporary adhesive layer 202,204 of Lin, which, along with previous discussion above, the Examiner believes completes the considerations under MPEP § 2143 I.B.
(c) Further, photolysis adhesive tape is known in the art, see for example Lin; Chih-Min (an ultraviolet light irradiates the soluble adhesive layer 220 to reduce adhesiveness of the soluble adhesive layer 220 {Fig 5G; ¶ [0045]), where the soluble adhesive layer 220 may be a photolysis or pyrolysis sticky material, preferably the photolysis sticky material, for example, an ultraviolet light release tape {¶ [0044]}); and,
(d) a chemical etching adhesive tape is known in the art, see for example Chuang (adhesive layer 21 can be removed by chemical etching to dissolve an adhesive {¶ [0048]}, where preferably, the adhesive layer can be a tape {¶ [0045]}; ¶ [0022-23])); and,
(e) Lin further discloses that debonding of (separating) the master from the molded body may alternatively be done by chemical etching, thermal bake, and UV light (¶ [0076]), which may imply adhesion by one of pyrolysis adhesive tape, a photolysis adhesive tape or a chemical etching adhesive tape and therefore render obvious the use of any of them.
Regarding the additional limitations of (3), that is the second, third and fifth components and mounting thereof, and mounting the electrical connection structure onto the second face of the substrate using the surface-mount technology:
Firstly, it would have been obvious to a person having ordinary skill in the art that multiple components may be mounted on each of the first face and a second face of the substrate, as this is known in the art. For example, Yang discloses that multiple IC devices may be mounted to the surface 208 of substrate 206, rather than the single IC device 202 shown in Fig 7 (Yang; Col 9, lines 5-7), and that more than one component may be mounted to the surface 210 of the substrate 207 (within the center cavity, containing 212 in example, between 232 and 216; Fig 7; Col 13, lines 24-32).
Secondly, it would have been obvious that each of the components mounted may use one of various mounting technologies, including the specific combination listed in claim 5, because using multiple mounting technologies with a single package is known in the art. For example, Yang discloses in Fig 6 a package structure comprising a component 154 which is flip-chip mounted to a surface of substrate 148 and surface-mounted to a surface 160 of substrate 158, wherein wire bonding is used between the two substrates 148 and 158. As another example, Lin discloses various mounting technologies combined in Fig 2; ¶ [0051], as well as in other figures. Additional examples may be found in the additionally cited art. One may have been motivated to combine these three mounting technologies among the multiple components of claim 5 in order to accommodate particular cost, manufacturing, and/or performance needs. One would have had a reasonable expectation of success because each of the elements is known in the art, and have been known to be combined with one another in various ways.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lin; Yaojian et al. (US 2016/0276258; hereinafter Lin) in view of Yang; Cheng et al. (US 10896877; hereinafter Yang), Lee; Seon H et al. (US 2022/0013370; hereinafter Lee), Pan; Ke-Hao et al. (US 2019/0044036; hereinafter Pan), Lin; Chih-Min et al. (US 2019/0051800; hereinafter Lin; Chih-Min), and Chuang; Cheng-Lung et al. (US 2010/0078747; hereinafter Chuang), and further in view of Kimura; Junichi (JP 2012/028487; hereinafter Kimura).
Regarding claim 20, Lin in view of Yang, Lee, Pan, Lin; Chin-Min, and Chuang discloses the manufacturing method according to claim 5, wherein splitting the molded body to obtain the individual double-sided package structures comprises:
splitting the molded body by cutting (using a saw blade or laser cutting tool 250; Fig 5q; ¶ [0086]) the molded body to obtain the individual double-sided package structures,
but does not disclose wherein a cutting line has a width greater than a width of a gap between adjacent ones of the at least two double-sided mount structures.
In the same field of endeavor, Kimura discloses similar structure and method, comprising a molded body comprising a ground pattern (52a; Fig 15; ¶ [0053]) which is exposed (¶ [0064]) by the splitting (with a dicing blade or the like; ¶ [0062]) of the molded body to enable connection to the ground pattern (¶ [0065]). Accordingly, it would have been obvious to a person having ordinary skill in the art in the method as applied to claim 5 that in the splitting a cutting line has a width greater than a width of a gap between adjacent ones of the at least two double-sided mount structures. One would have been motivated to come to this conclusion for the method wherein the double-sided package structures comprise a ground line or other connection line to which connection is to be made at an edge of the double-sided package structure. It would have been obvious that, in order to expose the line for making connection, a cutting line should have said width in order to ensure that the connection point(s) are fully exposed for connection, and not covered by encapsulation which may be the case for a lesser width. One would have had a reasonable expectation of success due to Kimura’s disclosure, the similarity of the disclosure and endeavor to those of Lin, and because the method is well-known and suitable in the art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.A.K./
Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817