Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see remarks, filed 1/28/2026, with respect to claims 1-19 have been fully considered and are persuasive. The final rejection of claims 1-19 has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. Claims 1-3, 8-12, and 15 are rejected under 35 U.S.C. 103 as being 6. unpatentable over ONO et al. (US 2014/0131696) in view Ahmadi et al. (Materials issues and devices of @ and B Ga2O3) and Tokuta et al. (JP 2018-082144).
With respect to Claims 1, 2, 9, and 15, ONO teaches a semiconductor device 10 (i.e. TFT) at least a crystalline oxide semiconductor layer 24 having a band gap (i.e. containing Ga2O3). The crystalline oxide semiconductor layer is in contact with a gate insulating film 16 and contains Ga203 or the mixed crystal thereof. The semiconductor device has a field-effect mobility of 30 cm2/Vs or higher. (see paragraphs 78, 84, and 85; Figs. 1 and 2H).
ONO fails to explicitly recite the semiconductor layer of Ga2O3 having a band gap of 3eV or more (i.e. 5.3 eV). However, Ahmadi discloses semiconductor layer of Ga2O3 having a band gap of 3eV or more (i.e. 5.3 eV) (see page 2 2ⁿᵈ paragraph). Thus, ONO and Ahmadi have substantially the same environment of a semiconductor layer of Ga2O3 used in a power semiconductor device. Therefore, one skilled in the art before the effective filing date of the claimed invention incorporate a semiconductor layer of Ga2O3 having a band gap of 3eV or more for the semiconductor layer of ONO, since this band gap for Ga2O3 would facilitate in a high performance and improve thermal conductivity for a power device as taught by Ahmadi.
With respect to Claims 3 and 10-12, Tokuta discloses it is well known in the semiconductor industry of transistors (see page 5 lines 38-42) to have a n-type and p-type dopants for a vertical power MOSFET.
With respect to Claim 8, Tokuta discloses it is well known in the semiconductor industry the crystalline oxide semiconductor layer has a corundum structure (see page 6 lines 40-47).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over ONO et al. (US 2014/0131696), Ahmadi et al. (Materials issues and devices of @ and B Ga2O3) , and Tokuta et al. (JP 2018-082144) and as applied to claim 1 above, and further in view of Shibuya T (JP 2013175747).
With respect to Claim 13, ONO-Ahmadi-Tokuta disclose the features of the claimed invention as discussed above, but does not disclose wherein an on/off ratio is 1000 or more. However, Shibuya discloses wherein an on/off ratio is 10 sup.9. (see English Text). However, the selection of the claimed device parameters would have been obvious to one having ordinary skill in the art before he effective filing date was made to provide an on/off ratio is within the claimed range, since it is well settle that when the general conditions of a claim are discloses in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
With respect to Claim 14, ONO-Ahmadi-Tokuta disclose the features of the claimed invention as discussed above, but does not disclose wherein the semiconductor device is normally off. However, Shibuya discloses wherein the semiconductor device is normally off (see English Text). It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of ONO-Ahmadi-Tokuta to provide wherein the semiconductor device is normally off as taught by Shibuya for a purpose of improving the performance of the semiconductor device.
Double Patenting
6. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
7. Claims 16 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. (US 12,284,822). Although the claims at issue are not identical, they are not patentably distinct from each other because the application and the patent both recite a crystalline oxide semiconductor layer having a band gap of 3 eV or more. A high-resistance oxide film on which the crystalline oxide semiconductor layer is located, wherein the high-resistance oxide film has a resistance of 1.0x10⁶ Ω cm or higher. The semiconductor device has a field-effect mobility of 30 cm²/V·s or higher.
Allowable Subject Matter
8. Claims 4-7, 17, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
9.A high-resistance oxide film on which the crystalline oxide semiconductor layer is located, and wherein the high-resistance oxide film has a resistance of 1.0x10⁶ Ω cm or higher.in claim 4.
The semiconductor device is configured to allow a drain current to flow upon a drain voltage (Vd) being 10 V and a gate voltage (Vg) being 4 V or more in claim 18.
The semiconductor device is configured to allow a drain current of 10 µA or more to flow upon drain voltage (Vd) being 10 V and gate voltage (Vg) being 5 V or more in claim 19.
The prior art made of record and not relied upon is cited primarily to show the
product of the instant invention.
Conclusion
9. Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/February 15, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897