DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/04/2026 has been entered.
Response to Amendment
Claims 1, 10, 17, 19 and 21 have been amended; and claims 1-25 are currently pending.
Information Disclosure Statement
There is no information disclosure statement filed for this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-25 are rejected under 35 U.S.C. 103 as being unpatentable over Shimabukuro et al. (US 2016/0329341 A1, hereinafter “Shimabukuro”) in view of Kimura et al. (USPN 9576967 B1, hereinafter “Kimura”) and IION et al. (US 2012/0241843 A1, hereinafter “IINO”).
In regards to claim 1, Shimabukuro discloses (See, for example, Figs. 2/22/23) an apparatus comprising:
tiers located one over another (3, 19), the tiers including respective memory cells and control gates for the memory cells;
conductive contacts (303) contacting the control gates, the conductive contacts (303) having different lengths extending in a direction from one tier to another tier among the tiers (See, for example, Fig. 2B); and
a contact structure (109/111) adjacent one of the conductive contacts (303), the contact structure (109/111) including a conductive core portion (111) extending through the tiers and separated from the control gates, and
a dielectric liner portion (109) adjacent the conductive core portion (111), the dielectric liner portion (109) including a first dielectric material (801), a second dielectric material (901) adjacent the first dielectric material (801), and a third dielectric material (1001) adjacent the second dielectric material (901).
Shimabukuro discloses all limitations of claim 1 above except that the conductive contacts including a first conductive contact and a second conductive contact; and
a contact structure adjacent and between the first conductive contact and the second conductive contact.
Kimura while disclosing (See, for example, annotated Fig. 21B included below) the conductive contacts including a first conductive contact (661) and a second conductive contact (662); and
a contact structure (1551) adjacent and between the first conductive contact (661) and the second conductive contact (662).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate Kimura into Shimabukuro because having the patterning film prevents impurity implantation into the semiconductor substrate beneath the first memory openings, thereby avoiding the formation of unwanted epitaxial channel portions at the bottom pf the support openings.
Shimabukuro is silent about the first tier including a first control gate of the control gates and a first silicon dioxide material formed over the first control gate, the second tier including a second control gate of the control gates and a second silicon dioxide material formed over the second control gate
a first silicon nitride material formed over the first silicon dioxide material;
a first additional silicon oxide material formed over the first silicon nitride material;
a second silicon nitride material formed over the second silicon dioxide material;
a second additional silicon oxide material formed over the second silicon nitride material;
the first conductive contact extends through the first additional silicon oxide
material, through the first silicon nitride material, and through the first silicon dioxide material, and contacts the first control gate; and the second conductive contact extends through the second additional silicon oxide material, through the second silicon nitride material, and through the second silicon dioxide material, and contacts the second control gate.
IINO while disclosing a nonvolatile semiconductor device teaches (See, for example, Fig. 8)
the first tier including a first control gate (61) of the control gates and a first silicon dioxide material (62) formed over the first control gate (61), the second tier including a second control gate (61) of the control gates and a second silicon dioxide material (62) formed over the second control gate (61)
a first silicon nitride material (19a) formed over the first silicon dioxide material (62);
a first additional silicon oxide material (19b) formed over the first silicon nitride material (19a);
a second silicon nitride material (19a) formed over the second silicon dioxide material (62);
a second additional silicon oxide material (19b) formed over the second silicon nitride material (19a);
the first conductive contact (31) extends through the first additional silicon oxide
material (19b), through the first silicon nitride material (19a), and through the first silicon dioxide material (62), and
contacts the first control gate (61); and
the second conductive contact (31) extends through the second additional silicon oxide material (19b), through the second silicon nitride material (19a), and through the second silicon dioxide material (62), and contacts the second control gate (61).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Shimabukuro by IINO because this would provide reduced thermal contraction to suppress a film stress, and reduce warpage of the wafer, and hence stable performance and high productivity are achieved.
In regards to claim 10, Shimabukuro discloses (See, for example, Figs. 2/22/23) an apparatus comprising:
tiers located one over another (3, 19), the tiers including respective memory cells and control gates for the memory cells,
the control gates (3) including respective portions that collectively form a staircase structure;
a first pillar (303) including a conductive material extending in a direction from one tier to another tier among the tiers and contacting one of the control gates at a location of the staircase structure (See, for example, Fig. 2B); and
a second pillar (109/111) adjacent the first pillar (303) and separated from the control gates (3), the second pillar (109/111) including a conductive core portion (111) and a dielectric liner portion (109) adjacent the conductive core portion (111), the dielectric liner portion (109) including a first dielectric material (1001) adjacent the conductive core portion (111), a second dielectric material (901) adjacent the first dielectric material (1001), and a third dielectric material (801) adjacent the second dielectric material (901).
Shimabukuro discloses all limitations of claim 1 above except that an additional pillar including an additional conductive material extending in the direction from one tier to another tier among the tiers and contacting a second control gate of the control gates at the location of the staircase structure; and
a second pillar adjacent and between the first pillar and the additional pillar and separated from the control gates.
Kimura discloses (See, for example, annotated Fig. 21B included below) an additional pillar (662) including an additional conductive material (66) extending in the direction from one tier to another tier among the tiers and contacting a second control gate of the control gates at the location of the staircase structure (See, for example, Col. 21 line 60 thru Col. 22 line 3); and
a second pillar (1551) adjacent and between the first pillar (661) and the additional pillar (662) and separated from the control gates.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate Kimura into Shimabukuro because having the patterning film prevents impurity implantation into the semiconductor substrate beneath the first memory openings, thereby avoiding the formation of unwanted epitaxial channel portions at the bottom pf the support openings.
Shimabukuro is silent about the first tier including a first control gate of the control gates and a first silicon dioxide material formed over the first control gate, the second tier including a second control gate of the control gates and a second silicon dioxide material formed over the second control gate
a first silicon nitride material formed over the first silicon dioxide material;
a first additional silicon oxide material formed over the first silicon nitride material;
a second silicon nitride material formed over the second silicon dioxide material;
a second additional silicon oxide material formed over the second silicon nitride material;
the first pillar extends through the first additional silicon oxide
material, through the first silicon nitride material, and through the first silicon dioxide material, and contacts the first control gate; and
the second pillar extends through the second additional silicon oxide material, through the second silicon nitride material, and through the second silicon dioxide material, and contacts the second control gate.
IINO while disclosing a nonvolatile semiconductor device teaches (See, for example, Fig. 8)
the first tier including a first control gate (61) of the control gates and a first silicon dioxide material (62) formed over the first control gate (61), the second tier including a second control gate (61) of the control gates and a second silicon dioxide material (62) formed over the second control gate (61)
a first silicon nitride material (19a) formed over the first silicon dioxide material (62);
a first additional silicon oxide material (19b) formed over the first silicon nitride material (19a);
a second silicon nitride material (19a) formed over the second silicon dioxide material (62);
a second additional silicon oxide material (19b) formed over the second silicon nitride material (19a);
the first pillar (31) extends through the first additional silicon oxide
material (19b), through the first silicon nitride material (19a), and through the first silicon dioxide material (62), and
contacts the first control gate (61); and
the second pillar (31) extends through the second additional silicon oxide material (19b), through the second silicon nitride material (19a), and through the second silicon dioxide material (62), and contacts the second control gate (61).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Shimabukuro by IINO because this would provide reduced thermal contraction to suppress a film stress, and reduce warpage of the wafer, and hence stable performance and high productivity are achieved.
In regards to claim 17, Shimabukuro (See, for example, Figs. 2/22/23) a method comprising:
forming levels of first dielectric materials (19) interleaved with levels of second dielectric materials (121);
forming a contact structure (109/111) through the levels of first dielectric materials and the levels of second dielectric materials (See, for example, Fig. 21)
wherein forming the contact structure (109/111) includes forming a dielectric liner portion (109) and forming a conductive core portion (111) adjacent the dielectric liner portion (109),
the dielectric liner portion (109) including silicon nitride material (901) between a first silicon dioxide material (801) and a second silicon dioxide material (1001);
replacing the levels of second dielectric materials with respective levels of conductive materials (See, for example, Figs. 22/23) ,
wherein the levels of conductive materials (3) form respective control gates for memory cells of a memory device; and
forming a first conductive contact (303) adjacent the contact structure (109/111) and contacting a first level of the levels of conductive materials (3, See, for example, Fig. 2B).
Shimabukuro discloses all limitations of claim 1 except that forming a second conductive contact adjacent the contact structure and contacting a second level of the levels of conductive materials, wherein the contact structure is between the first conductive structure and the second conductive structure.
Kimura discloses (See, for example, annotated Fig. 21B included below) forming a second conductive contact (662) adjacent the contact structure (1551) and contacting a second level of the levels of conductive materials, wherein the contact structure (1551) is between the first conductive structure (661) and the second conductive structure (662).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate Kimura into Shimabukuro because having the patterning film prevents impurity implantation into the semiconductor substrate beneath the first memory openings, thereby avoiding the formation of unwanted epitaxial channel portions at the bottom pf the support openings.
Shimabukuro is silent about forming a first silicon nitride material over a first level of the levels of first dielectric materials at the staircase structure;
forming a first silicon oxide material over the first silicon nitride material;
forming a second silicon nitride material over a second level of the levels of first dielectric materials at the staircase structure;
forming a second silicon oxide material formed over the second silicon nitride material; wherein the levels of conductive materials include a first level of the conductive levels contacting the first level of the levels of first dielectric materials, and a second level of the conductive levels contacting the second level of the levels of first dielectric materials, wherein the first conductive contact extends through the first silicon oxide material, through the first silicon nitride material. and through the first level of the levels of first dielectric materials; wherein the second conductive contact extends through the second silicon oxide material, through the second silicon nitride material, and through the second level of the levels of first dielectric materials.
IINO while disclosing a nonvolatile semiconductor device teaches (See, for example, Fig. 8) forming a first silicon nitride material (19a) over a first level of the levels of first dielectric materials (62) at the staircase structure;
forming a first silicon oxide material (19b) over the first silicon nitride material (19a);
forming a second silicon nitride material (19a) over a second level of the levels of first dielectric materials (62) at the staircase structure;
forming a second silicon oxide material (19b) formed over the second silicon nitride material (19a);
wherein the levels of conductive materials include a first level of the conductive levels (61) contacting the first level of the levels of first dielectric materials (62), and a second level of the conductive levels (61) contacting the second level of the levels of first dielectric materials (62),
wherein the first conductive contact (31) extends through the first silicon oxide material (19b), through the first silicon nitride material (19a) and through the first level of the levels of first dielectric materials (62);
wherein the second conductive contact (31) extends through the second silicon oxide material (19b), through the second silicon nitride material (19a), and through the second level of the levels of first dielectric materials (62).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Shimabukuro by IINO because this would provide reduced thermal contraction to suppress a film stress, and reduce warpage of the wafer, and hence stable performance and high productivity are achieved.
In regards to claim 21, Shimabukuro discloses (See, for example, Figs. 2/22/23) a method comprising:
forming levels of first dielectric materials (19) interleaved with levels of second dielectric materials (121), the levels of first dielectric materials (19) having respective portions forming part of a staircase structure;
forming a contact structure (109/111) in an opening in the levels of first dielectric materials (19) and the levels of second dielectric materials (121) at the staircase structure,
wherein forming the contact structure (109/111) includes forming a dielectric liner portion (109) in the opening, and
forming a conductive core portion (111) in the opening such that at least a portion of the conductive core portion (111) is surrounded by the dielectric liner portion (109), and
forming the dielectric liner portion (109) includes: forming a first dielectric material (801) in the opening;
forming a second dielectric material (901) adjacent the first dielectric material (801); and
forming a third dielectric material (1001) adjacent the second dielectric material (901); replacing the levels of second dielectric materials (121) with respective levels of conductive materials (3, See, for example, Figs. 22/23),
wherein the levels of conductive materials (3) form respective control gates for memory cells of a memory device; and
forming a fist conductive contact (303) adjacent the contact structure and contacting a first level of the levels of conductive materials (3).
Shimabukuro discloses all limitations of claim 1 except that forming a second conductive contact adjacent the contact structure and contacting a second level of the levels of conductive materials, wherein the contact structure is between the first conductive structure and the second conductive structure.
Kimura discloses (See, for example, annotated Fig. 21B included below) forming a second conductive contact (662) adjacent the contact structure (1551) and contacting a second level of the levels of conductive materials, wherein the contact structure (1551) is between the first conductive structure (661) and the second conductive structure (662).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate Kimura into Shimabukuro because having the patterning film prevents impurity implantation into the semiconductor substrate beneath the first memory openings, thereby avoiding the formation of unwanted epitaxial channel portions at the bottom pf the support openings.
Shimabukuro is silent about forming a first silicon nitride material over a first level of the levels of first dielectric materials at the staircase structure;
forming a first silicon oxide material over the first silicon nitride material;
forming a second silicon nitride material over a second level of the levels of first dielectric materials at the staircase structure;
forming a second silicon oxide material formed over the second silicon nitride material;
wherein the levels of conductive materials include a first level of the conductive levels contacting the first level of the levels of first dielectric materials, and a second level of the conductive levels contacting the second level of the levels of first dielectric materials,
wherein the first conductive contact extends through the first silicon oxide material, through the first silicon nitride material. and through the first level of the levels of first dielectric materials;
wherein the second conductive contact extends through the second silicon oxide material, through the second silicon nitride material, and through the second level of the levels of first dielectric materials.
IINO while disclosing a nonvolatile semiconductor device teaches (See, for example, Fig. 8)
forming a first silicon nitride material (19a) over a first level of the levels of first dielectric materials (62) at the staircase structure;
forming a first silicon oxide material (19b) over the first silicon nitride material (19a);
forming a second silicon nitride material (19a) over a second level of the levels of first dielectric materials (62) at the staircase structure;
forming a second silicon oxide material (19b) formed over the second silicon nitride material (19a);
wherein the levels of conductive materials include a first level of the conductive levels (61) contacting the first level of the levels of first dielectric materials (62), and a second level of the conductive levels (61) contacting the second level of the levels of first dielectric materials (62),
wherein the first conductive contact (31) extends through the first silicon oxide material (19b), through the first silicon nitride material (19a) and through the first level of the levels of first dielectric materials (62);
wherein the second conductive contact (31) extends through the second silicon oxide material (19b), through the second silicon nitride material (19a), and through the second level of the levels of first dielectric materials (62).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Shimabukuro by IINO because this would provide reduced thermal contraction to suppress a film stress, and reduce warpage of the wafer, and hence stable performance and high productivity are achieved.
In regards to claim 2, Shimabukuro discloses (See, for example, Figs. 2/22/23) the first (801) and third (1001) dielectric materials are formed from a same material (See, for example, Pars [0053] and [0055]).
In regards to claim 3, Shimabukuro discloses (See, for example, Figs. 2/22/23) the first dielectric material (801) includes silicon dioxide (See, for example, Par [0053), and the second dielectric material (901) includes silicon nitride (See, for example, Par [0054]).
In regards to claim 4, Shimabukuro discloses (See, for example, Figs. 2/22/23) the third dielectric material (1001) includes silicon dioxide (Par [0055]).
In regards to claim 6, Shimabukuro discloses (See, for example, Figs. 2/22/23) the conductive core portion (111) includes metal (See, for example, Par [0029]).
In regards to claim 5, Shimabukuro discloses all limitations of claim 1 above except that the second dielectric material has a thickness less than a thickness of each of the first and second dielectric materials.
Notwithstanding, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular relative dimensions because applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Furthermore, the specification contains no disclosure of either the critical nature of the claimed thickness range or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. See In re Woodruff, 919, f.2d 1575, 1578, 16 USPQ2d, 1936 (Fed. Cir. 1990).
In regards to claim 7, Shimabukuro discloses (See, for example, Figs. 2/22/23) that each of the conductive contacts (109/111) includes a dielectric liner portion (109) having a different structure from the dielectric liner portion of the contact structure (109/111).
In regards to claim 8, Shimabukuro discloses (See, for example, Figs. 2/22/23) each of the conductive contacts (109/111) includes a conductive core portion (111) having a same structure as the conductive core portion of the contact structure.
In regards to claim 9, Shimabukuro discloses (See, for example, Figs. 2/22/23) the apparatus comprises a memory device, the memory device including circuitry located under the tiers, and the conductive core portion of the contact structure is coupled to the circuitry (See, for example, Abstract, Par [0020], and see also Claim 12).
In regards to claim 11, Shimabukuro discloses (See, for example, Figs. 2/22/23) the second dielectric material includes silicon nitride (901, See, for example, Par [0054]).
In regards to claim 12, Shimabukuro discloses (See, for example, Figs. 2/22/23) the first (1001) and third (801) dielectric materials include silicon dioxide (See, for example, Pars [0053] and [0055]).
In regards to claims 13 and 14, Shimabukuro discloses (See, for example, Figs. 2/22/23) the conductive core portion (111) of the second pillar includes metal, and at least a portion of the metal is surrounded by the dielectric liner portion (109) of the second pillar; and the conductive material of the first pillar includes metal.
However, the Shimabukuro is silent about that the conductive core portion includes tungsten.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to include tungsten for the conductive core portion or the conductive material, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In regards to claim 15, Shimabukuro discloses (See, for example, Figs. 2/22/23) the first pillar includes a dielectric liner portion (109) surrounding at least a portion of the tungsten of the conductive material (111) of the first pillar.
In regards to claim 16, Shimabukuro discloses (See, for example, Figs. 2/22/23) first pillar includes a conductive core portion (111) having a different structure from a structure of the conductive core portion (111) of the second pillar (See, for example, pillars 107, Fig. 2A).
In regards to claim 18, Shimabukuro discloses (See, for example, Figs. 2/22/23) the conductive core portion (111) includes a metal material (See, for example, Par [0029]).
In regards to claim 19, Shimabukuro as modified above discloses (See, for example, Figs. 2/22/23) forming the dielectric liner portion (109) includes:
forming an opening (501, See, for example, Fig. 6) through the levels of first dielectric materials (19) and the levels of second dielectric materials (121); wherein a portion of the levels of first dielectric materials (62, IION) is exposed at the opening after the opening is formed, an wherein a portion of the levels of second dielectric materials (62, IION) exposed at the opening after the opening is formed;
removing a portion of the levels of second dielectric materials (121) exposed at the opening (501) to form recesses (See, for example, Fig. 6;
forming the first silicon dioxide material in the recesses and on a sidewall of the opening (See, for example, Fig. 8 and Par [0053]);
forming the silicon nitride material on the first silicon dioxide material (See, for example, Fig. 9 and Par [0054]);
; and
forming the second silicon dioxide material on the silicon nitride material (See, for example, Fig. 10 and Par [0055]).
In regards to claim 20, Shimabukuro discloses (See, for example, Figs. 2/22/23) forming the conductive core portion (111) includes forming a metal material (See, for example, Par [0029]) in the opening such that at least a portion of the metal material is surrounded by the dielectric liner portion (109).
In regards to claim 22, Shimabukuro discloses (See, for example, Figs. 2/22/23) the second dielectric material (901) includes silicon nitride (Par [0054).
In regards to claim 23, Shimabukuro discloses (See, for example, Figs. 2/22/23) the first (801) and third (1001) dielectric materials include silicon dioxide (See, for example, Pars [0053] and [0055).
In regards to claim 24, Shimabukuro discloses (See, for example, Figs. 2/22/23) the levels of conductive materials include tungsten (See, for example, Par [0042]).
In regards to claim 25, Shimabukuro discloses (See, for example, Figs. 2/22/23) the levels of first dielectric materials (19) include silicon dioxide (See, for example, Par [0049]), and the levels of second dielectric materials (121) include silicon nitride (See, for example, Par [0049]).
Response to Arguments
Applicant’s arguments with respect to claims 1, 10, 17 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893