DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is FINAL and is in response to the amendment filed February 27th, 2026. Claims 1-20 are pending, of which claims 1-20 are currently rejected. Claims 1-20 have been cancelled by Applicant.
Response to Arguments
The amendment filed February 27th, 2026 has been entered. 1-20 remain pending in the application. Applicant’s amendments to the Specification have overcome each and every specification objection previously set forth in the Non-Final Office Action mailed November 28th, 2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/12/2025 are in compliance with the provisions of 37 CFR 1.97. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
112(f) Interpretation
Applicant alleges that “a first backup storage component” and “a second backup storage component” do not invoke 112(f) because (1) upon reading the specification, a person of ordinary skill in the art would understand the claim limitations identified above as having a definite meaning as the name for the respective structure that performs the function and (2) because claim limitations are not generic placeholders.
Examiner respectfully disagrees. In order for a claim limitation to invoke 112(f), three conditions must be met.
First, as explained in MPEP 2181(I)(A), is that the claim limitation uses the term "means" or "step" or a generic placeholder, examples of generic placeholders including but not limited to "mechanism for," "module for," "device for," "unit for," "component for," "element for," "member for," "apparatus for," "machine for," or "system for." Both limitations indicated as invoking 112(f) contain the nonce term “component”.
Second, as explained in MPEP 2181(I)(B), the term “means” or “step” or the generic placeholder must be modified by functional language. The main example shown in the term “for”, but this can be replaced as explicitly stated in the MPEP by the phrase “configured to” which is also contained in the limitations that invoke 112(f) (a first backup storage component configured to…; a second backup storage component configured to).
Lastly, as explained in MPEP 2181(I)C), the term “means” or “step” or the generic placeholder must not be modified by sufficient structure, material or acts for achieving the specified function. For “a first backup storage component”, the modifier “first backup storage” does not specify a structure for the component, only that it is to be used for storage. This structure can be any of a register, a flip-flop or latch, a hard drive, logical, physical memory, etc. The same occurs with “second backup storage component”.
Applicant’s argument as to having to read the specification in order to have clarity on the structure for the limitations is a direct consequence having to invoke 112(f). Without invocation of 112(f), although claims are understood in the light of specification, limitations are not read into the claims from the specification. As such the claims on their own do not allow for a clear understanding of the structural aspect of the invention as needed for apparatus claims.
For these reasons, the two limitations do in fact invoke 112(f).
See Claim Interpretation.
Prior Art Rejections
Applicant’s arguments regarding the previously cited art have been fully considered and are not persuasive.
Applicant alleges that neither Chih, nor Raha, nor Son teaches relying on the value of the first control signal to determine whether to provide the first MAC value through computing the first bits of the first and second input signals (obtained in a current cycle) or retrieving the second bits of the first and second input signals from the first backup storage component (obtained in a previous cycle) (Applicant Remarks: Pg. 11).
Examiner respectfully disagrees.
Applicant’s arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Additionally, in combining Chih, Raha, and Son, Chih teaches the plurality of macros structure (Chih: Fig. 16.4.1) as well as a control block for generating control signals, which is further expanded upon when relying upon Raha in terms of determination whether inputs are from a current round or previous round of computation, stored in a backup storage component (Raha: Fig. 9). This determination is further specified by having a bit by bit analysis as discussed in Son, and outputting of a control signal to allow for a MAC computation to be carried out (Son: Abstract; ¶ 0154; ¶ 0156).
Ultimately, the structure and functionality of Chih is modified by the addition of backup storage components and determination of input is from a current or previous round (and therefore obtained from a backup storage component, as is discussed in Raha, as well as a bit by bit determination to determine whether first or second bits are used for a MAC operation as discussed in Son.
Therefore, Chih in view of Raha in view of Son does in fact teach claim 1 as amended.
There are new reasons of rejection as necessitated by amendments. See Claim Rejections - 35 USC § 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chih et al. (“An 89TOPS/W and 16.3TOPS/mm-2 All Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications”, February 2021) (hereinafter “Chih”), further in view of Raha et al. (US 2021/0326144 A1) included in the IDS filed on 08/07/2023 (hereinafter “Raha”), in view of Son et al. (US 2021/0208878 A1) (hereinafter “Son”), further in view of Kang et al. (
Regarding claim 1, Chih teaches:
An integrated circuit, comprising:
a logic gate (Chih: Pg. 253 Fig. 16.4.2 shows receiving of input signals via a gate) configured to:
receive a first input signal and a second input signal (Chih: Pg. 253 Fig 16.4.1 each pair of weights and multipliers that are accumulated into 5b are a macro, taking as inputs 2 input signals (in first macro would be IN<0> and IN<1>, weights being taken from weight SRAM as shown in inset towards the top right of the figure, Fig. 16.4.1 shows the array of macros); and
generate a first control signal (Chih: Pg. 253 Fig. 16.4.1 shows a control block for generating control signals);
a plurality of first macros;
wherein each of the plurality of macros is configured to selectively compute, a first multiply-accumulate (MAC) value for the first bit of the first input signal and the first bit of the second input signal (Chih: Pg. 253 Fig 16.4.1 each of pair of weights and multipliers that are accumulated into 5b are a macro, taking as inputs 2 input signals (in first macro would be IN<0> and IN<1>, weights being taken from weight SRAM as shown in inset towards the top right of the figure, Fig. 16.4.1 shows the array of macros; Pg. 252 Col. 1 fourth paragraph describes MAC operations and outputting occurring over several cycles);
Chih does not explicitly teach generating a first control signal based on a first bit of the first and second input signals obtained in a current cycle, or a first backup storage component configured to store a second bit of the first and second input signals obtained in a previous cycle or computations being dependent on control signals being equivalent to a first or second value.
However, Raha teaches:
signal based on a first bit of the first input signal and a first bit of the second input signal obtained in a current cycle (Raha: Fig. 9 teaches the determination of inputs being of a current cycle)
a first backup storage component configured to store a second bit of the first input signal and a second bit of the second input signal obtained in a previous cycle (Raha: ¶ 0044 compressed machine learning parameter data i.e., the input data is stored in local memory 204; Fig. 9 shows MAC operations that may occur using information from a previous round, which takes data from local memory 204 as discussed in ¶ 0069 also explained in ¶ 0108);
and the second bit of the first input signal and the second bit of the second input signal stored in the first backup storage component (Raha: Fig. 9 shows determination of whether bits of input seconds i.e., first and second input signal being from a previous round i.e., being stored in a back up storage component or in this case local memory 204 of Raha).
It would be obvious to combine the current cycle determination and first backup storage component as taught by Raha with the integrated circuit and macros as taught by Chih as both teachings are directed towards MAC operation processing. One with ordinary skill in the art would be motivated to combine the teachings because doing so would facilitate access to operands in memory and increase execution speed (Raha: ¶ 0150) and would reduce clock cycles needed for operations (Raha: ¶ 0020).
Chih in view of Raha does not explicitly teach:
generate a first control signal based on a first bit of the first input signal and a first bit of the second input signal.
However, Son teaches a controller for generating a control signal based on a first bit of the first input signal and the second input signal through the use of a OR gate i.e. first gate and inverter (Son: Abstract; ¶ 0154; ¶ 0156).
It would be obvious to combine the generation of a control signal as taught by Son with the integrated circuit as taught by Chih in view of Raha as all teachings are directed towards MAC operations. One with ordinary skill in the art would be motivated to combine the teachings because doing so would allow for a reduction in power consumption (Son: ¶ 0187).
Chih in view of Raha in view of Son therefore teaches:
An integrated circuit, comprising:
a first logic gate configured to:
receive a first input signal and a second input signal; and
generate a first control signal based on a first bit of the first input signal and a first bit of the second input signal obtained in a current cycle;
a first backup storage component configured to store a second bit of the first input signal and a second bit of the second input signal obtained in a previous cycle; and
a plurality of first macros;
wherein each of the plurality of first macros is configured to compute, in response to the first control signal being equal to a first value, a first multiply-accumulate (MAC) value for the first bit of the first input signal and the first bit of the second input signal;
wherein each of the plurality of first macros is configured to provide the first MAC value using the second bit of the first input signal and the second bit of the second input signal stored in the first backup storage component, in response to the first control signal being equal to a second value.
Regarding claim 2, Chih in view of Raha in view of Son teaches:
The integrated circuit of claim 1, wherein each of the plurality of first macros is further configured to output the corresponding first MAC value as either a fixed logic value or being computed based on the first bit of the first input signal and the first bit of the second input signal (Son: Abstract outputting as MAC value a logic zero i.e., a fixed logic value, in the case that the input signals equal the logic value i.e., ‘0’ also discussed in ¶ 0154).
The motivation to combine with respect to claim 1 applies equally to claim 2.
Regarding claim 3, while Chih teaches a plurality of first macros and computation of MAC operations (Chih: Pg. 253 Fig 16.4.1 each of pair of weights and multipliers that are accumulated into 5b are a macro, taking as inputs 2 input signals (in first macro would be IN<0> and IN<1>, weights being taken from weight SRAM as shown in inset towards the top right of the figure, Fig. 16.4.1 shows the array of macros), Chih does not explicitly teach a second logic gate configured to output the corresponding first MAC value based on a logic inverse of the first control signal.
However, Raha teaches a data controller with zero skipper as shown in Fig. 4B leading to processing engine i.e., MAC unit or macro for MAC operations, macro containing second logic gate being the AND gate i.e., second logic gate for MAC operations as discussed in ¶ 0102.
The motivation to combine with respect to claim 1 applies equally to claim 3.
Chih in view of Raha does not explicitly teach a MAC value output corresponding to the inverse of a first control signal.
However, Son teaches zero detection logic in Fig. 35 that has a control unit (Son: Fig. 35 1300) that takes in zero detection logic from the two input signals, containing an OR gate i.e., first logic gate and an inverter, so MAC operations are carried out based on an inverted control logic signal.
The motivation to combine with respect to claim 1 applies equally to claim 3.
Therefore, Chih in view of Raha in view of Son teaches:
The integrated circuit of claim 1, wherein each of the plurality of first macros comprises a second logic gate configured to output the corresponding first MAC value based on a logic inverse of the first control signal.
Regarding claim 4, Chih in view of Raha in view of Son teaches:
The integrated circuit of claim 3, wherein the second logic gate includes an AND gate (Son: ¶ 0071 teaches processing device i.e. macro receiving control logic from controller with zero detection logic and OR gate and receiving operands into the macro via reading through an AND gate).
The motivation to combine with respect to claim 1 applies equally to claim 4.
Regarding claim 5, Chih in view of Raha in view of Son teaches:
The integrated circuit of claim 1, wherein the first logic gate includes an OR gate (Son: Fig. 35 zero detection logic unit has control unit 1300 that takes in zero detection logic from the two input signals, containing an OR gate and an inverter, so MAC operations made based on inverted control logic signal).
The motivation to combine with respect to claim 1 applies equally to claim 5.
Regarding claim 6, Chih in view of Raha in view of Son teaches:
The integrated circuit of claim 1, wherein the first bit of the first input signal has a larger value than the second bit of the first input signal (Raha: taking as first bit the least significant bit (operations start from least significant bits Fig 10 Block 1006), Fig. 5 least significant bit of first input 102A bit 4 is greater than the second bit 1 Fig. 5), and the first bit of the second input signal has a larger value than the second bit of the second input signal (Raha: taking as first bit the least significant bit (operations start from least significant bits Fig. 10 Block 1006), Fig. 5 least significant bit of second input 102B bit A is greater than the second bit 0).
The motivation to combine with respect to claim 1 applies equally to claim 6.
Regarding claim 7, Chih in view of Raha in view of Son teaches:
The integrated circuit of claim 1, wherein each of the plurality of first macros comprises:
a memory array (Chih: Pg 253 Fig 16.4.1 each of pair of weights and multipliers that are accumulated into 5b are a macro, taking as inputs 2 input signals (in first macro would be IN<0> and IN<1>, weights being taken from weight SRAM i.e., memory array as shown in inset towards the top right of the figure);
a first multiplier operatively coupled to a first bit cell of the memory array (Chih: Pg. 253 Fig. 16.4.1 first multiplier being circles with x's of first set of the pair (top left of figure in W0<0:3> column) coupled to first bit cell of weight SRAM as further described in Pg. 252 Col. 1 third paragraph);
a second multiplier operatively coupled to a second bit cell of the memory array (Chih: Pg. 253 Fig. 16.4.1 second multiplier being circles with x's of second set of the pair (top left of fig in W0<0:3> column) coupled to the following bit cell of weight SRAM as further described in Pg. 252 Col. 1 third paragraph); and
an adder operatively coupled to the first and second multipliers (Chih: adder labeled 5b to accumulate multiplications of input signals IN<0> and IN<1> with respect to weights taken from weight SRAM i.e., memory array).
Regarding claim 8, while Chih teaches the second multiplier (Chih: Pg. 253 Fig. 16.4.1 second multiplier being circles with x's of second set of the pair (top left of fig in W0<0:3> column)), Chih does not teach the first control signal being equal to the second value and therethrough taking input from the backup storage component.
However, Raha teaches the backup storage component in order to use operands obtained in previous cycles in the case that at least one of the input values are 0 in order to skip zero computations (Raha: ¶ 0044 compressed machine learning parameter data i.e., the input data is stored in local memory 204; Fig. 9 shows MAC operations that may occur using information from a previous round, which takes data from local memory 204 as discussed in ¶ 0069 also explained in ¶ 0108; ¶ 0142 discusses microprocessor 1600 also follows the block diagrams including Fig. 9, local memory of 1600 is 1618 plurality of registers and is used to store data or instructions including compressed machine learning parameters as discussed in ¶ 0144; ¶ 0102, ¶ 0104, ¶ 0108 describes functionality of zero compute load skipper and example data receiver which determine a control signal based on if any zero values are present, and whether input values were received the current cycle or a previous cycle, and therethrough directing the input to the corresponding logic gate circuitries for corresponding MAC operations; also shown in Figs. 8 and 9).
The motivation to combine with respect to claim 1 applies equally to claim 8.
Chih in view of Raha does not explicitly teach the first control signal being equal to the second value being used to determine MAC operations.
However, Son teaches the control signal being equal to one of two i.e., a second value and being used to determine MAC operations and the output MAC value (Son: ¶ 0156 - ¶ 0158).
The motivation to combine with respect to claim 1 applies equally to claim 8.
Chih in view of Raha in view of Son therefore teaches:
The integrated circuit of claim 7, wherein in response to determining that the first control signal is equal to the second value, the first multiplier remains coupled to the first backup storage component and the second multiplier remains coupled to the first backup storage component.
Regarding claim 9, while Chih teaches the first and second multipliers to receive a first bit of the first and second input signals respectively, Chih does not explicitly teach determining the first control signal being equal to the first value and enabling MAC operations of the current cycle as usual.
However, Raha teaches determination that the inputs were obtained in the current cycle (Raha: Figs. 8 and 9).
The motivation to combine with respect to claim 1 applies equally to claim 9.
Chih in view of Raha does not explicitly teach MAC operations being determined in response to determining the first control signal being equal to a first value.
However, Son teaches the control signal being equal to one of two i.e., the first value and being used to determine MAC operations and the output MAC value (Son: ¶ 0156 - ¶ 0158).
The motivation to combine with respect to claim 1 applies equally to claim 9.
Regarding claim 10, Chih in view of Raha in view of Son teaches:
The integrated circuit of claim 1, further comprising:
a third logic gate (Chih: Pg. 253 Fig. 16.4.1 in second pair of macros taking in inputs IN<254> and IN<255>, macros are further expanded in Fig. 16.4.2 showing inputs being taken in by logic gate i.e., third logic gate) configured to:
receive a third input signal and a fourth input signal (Chih: input signals being provided to CIM array including a third and fourth input signal IN<254> and IN<255>); and
a plurality of second macros each configured to selectively compute, based on the control signal, a second MAC value of the first bit of the third input signal and the first bit of the fourth input signal (Chih: second plurality of macros towards bottom of Fig. 16.4.1 taking as inputs IN<254> and IN<255> and calculating MAC value as discussed in Pg. 252 Col. 1 fourth paragraph).
Chih does not explicitly teach a second control signal based on a first bit of the third and fourth input signals obtained in a current cycle, or a second backup storage component configured to store a second bit of the third and fourth input signals obtained in a previous cycle.
However, Raha teaches:
signal based on a first bit of the third input signal and a first bit of the fourth input signal obtained in a current cycle (Raha: Fig. 9 teaches the determination of inputs being of a current cycle, in having a second plurality of macros as taught by Chih, and following the combination of claim 1, this determination would be needed for any following input signals including a third and fourth input signal)
a first backup storage component configured to store a second bit of the first input signal and a second bit of the second input signal obtained in a previous cycle (Raha: ¶ 0044 compressed machine learning parameter data i.e., the input data is stored in local memory 204; Fig. 9 shows MAC operations that may occur using information from a previous round, which takes data from local memory 204 as discussed in ¶ 0069 also explained in ¶ 0108; in having a second plurality of macros as taught by Chih, and following the combination of claim 1, a second backup storage component would be needed for any following input signals including a third and fourth input signal).
The motivation to combine with respect to claim 1 applies equally to claim 10.
Chih in view of Raha does not explicitly teach:
generate a second control signal based on a first bit of the third input signal and a first bit of the fourth input signal.
However, Son teaches a controller for generating a control signal based on a first bit of the input signals through the use of a OR gate and inverter (Son: Abstract; ¶ 0154; ¶ 0156; in having a second plurality of macros as taught by Chih, and following the combination of claim 1, a second control signal would be needed for any following input signals including a third and fourth input signal).
The motivation to combine with respect to claim 1 applies equally to claim 10.
Chih in view of Raha in view of Son therefore teaches:
The integrated circuit of claim 1, further comprising:
a third logic gate configured to:
receive a third input signal and a fourth input signal; and
generate a second control signal based on a first bit of the third input signal and a first bit of the fourth input signal in the current cycle;
a second backup storage component configured to store a second bit of the third input signal and a second bit of the fourth input signal in the previous cycle; and
a plurality of second macros each configured to selectively compute, based on the second control signal, a second MAC value of the first bit of the third input signal and the first bit of the fourth input signal.
Regarding claim 11, Chih in view of Raha in view of Son teaches the plurality of first macros and plurality of second macros forming a first and second column of a compute-in-memory array (Chih: Pg. 253 Fig. 16.4.1 columns are horizontal, taking in IN<0> and IN<1> for first plurality of macros, and IN<254> and IN<255> for another plurality of macros).
Regarding claim 18, Chih in view of Son teaches each macro comprising an AND gate configured to receive an input, and a logic state of the input of the AND gate being determined according to an output of an OR gate with inputs being a first bit of a first input signal and second input signal (Son: Fig. 35 zero detection logic unit has control unit 1300 that takes in zero detection logic from the two input signals, containing an OR gate and an inverter, so MAC operations made based on inverted control logic signal, the MAC operators take in operands through an AND gate as discussed in ¶ 0073), Chih in view of Son does not explicitly teach a determination of bits being of a current cycle.
However, Raha teaches receiving operands while determining that the operands are from the current cycle (Raha: Figs. 8 and 9).
The motivation to combine with respect to claim 1 applies equally to claim 18.
Claims 12-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chih in view of Son.
Regarding claim 12, Chih teaches:
An integrated circuit, comprising:
an array comprising a plurality of macros (Chih: Pg. 253 Fig 16.4.1 each of pair of weights and multipliers that are accumulated into 5b are a macro, taking as inputs 2 input signals (in first macro would be IN<0> and IN<1>, weights being taken from weight SRAM as shown in inset towards the top right of the figure, Fig. 16.4.1 shows the array of macros);
wherein each macro is configured to output a plurality of multiply-accumulate (MAC) values of a first input signal and a second input signal in respectively different cycles (Chih: Pg. 252 Col. 1 fourth paragraph describes MAC operations and outputting occurring over several cycles; Pg. 253 Fig. 16.4.1 first input signal IN<0> and second input signal IN<1>); and
wherein each macro is configured to determine a first one of the plurality of MAC values in a current one of the cycles as being computed based on a first bit of the first input signal and a first bit of the second input signal obtained in the current cycle (Chih: Pg. 252 Col. 1 fourth paragraph discusses multiplications with respect to the input signals and the bits in a cycle).
Chih does not explicitly teach:
wherein each macro is configured to determine a first one of the plurality of MAC values in a current one of the cycles as a fixed logic value.
However, Son teaches outputting as MAC value a logic zero i.e., a fixed logic value, in the case that the input signals equal the logic value i.e., ‘0’ (Son: Abstract; ¶ 0154) while taking into consideration the clock cycles during computation (Son: ¶ 0093), as well as using stored products as a MAC value calculated in a previous layer i.e., in a previous cycle (Son: ¶ 0083 - ¶ 0084).
It would be obvious to combine the outputting of a fixed logic value as taught by Son with the array of macros and MAC operation as taught by Chih as both teachings are directed to in-memory MAC operations. One with ordinary skill in the art would be motivated to combine the teachings because doing so would allow for a reduction in power consumption (Son: ¶ 0187).
Therefore, Chih in view of Son teaches:
An integrated circuit, comprising:
an array comprising a plurality of macros;
wherein each macro is configured to output a plurality of multiply-accumulate (MAC) values of a first input signal and a second input signal in respectively different cycles; and
wherein each macro is configured to determine a first one of the plurality of MAC values in a current one of the cycles as either a fixed logic value or being computed based on a first bit of the first input signal and a first bit of the second input signal obtained in the current cycle or being equal to a stored product computed based on a second bit of the first input signal and a second bit of the second input signal obtained in a previous one of the cycles.
Regarding claim 13, Chih in view of Son further teaches:
The integrated circuit of claim 12, wherein the plurality of macros are arranged along a row of the array (Chih: Pg. 253 Fig. 16.4.1 macros are arranged in rows and columns).
Regarding claim 14, Chih in view of Son teaches:
The integrated circuit of claim 12, wherein, in response to the first bit of the first input signal and the first bit of the second input signal obtained in the current cycle each being equal to a logic 0, each macro is configured to output the corresponding first MAC value as a logic 0 (Son: outputting as MAC value a logic zero i.e., a fixed logic value, in the case that the input signals equal the logic value i.e., ‘0’ as discussed in Abstract and ¶ 0154).
The motivation to combine with respect to claim 12 applies equally to claim 14.
Regarding claim 15, Chih in view Son teaches:
The integrated circuit of claim 12, wherein, in response to at least one of the first bit of the first input signal or the first bit of the second input signal obtained in the current cycle not being equal to a logic 0, each macro is configured to output the corresponding first MAC value as a MAC computation result (Chih: Pg. 252 Col. 1 fourth paragraph discusses MAC operations being as expressed as Qj and MAC operations happening over a number of cycles).
Regarding claim 16, Chih in view of Son teaches:
The integrated circuit of claim 15, wherein the MAC computation result is equal to a sum of the first bit of the first input signal multiplied by a first weight and the first bit of the second input signal multiplied by a second weight (Chih: Pg. 252 Col. 1 fourth paragraph discusses MAC operations being as expressed as Qj and input signals being multiplied by weights).
Regarding claim 17, Chih in view of Son teaches:
The integrated circuit of claim 16, wherein each macro comprises a memory array comprising a first memory cell storing the first weight (Chih: pg 253 Fig. 16.4.1 first multiplier being circles with x's of first set of the pair (top left of figure in W0<0:3> column) coupled to first bit cell of weight SRAM as further described in Pg. 252 Col. 1 third paragraph), and a second memory cell storing the second weight (Chih: Pg. 253 Fig. 16.4.1 second multiplier being circles with x's of first set of the pair (top left of figure in W0<0:3> column) coupled to second bit cell of weight SRAM as further described in Pg. 252 Col. 1 third paragraph).
Regarding claim 19, Chih teaches:
A method, comprising:
receiving a first input signal and a second input signal (Chih: Pg. 253 Fig. 16.4.1 receiving first input signal IN<0> and second input signal IN<1>);
computing a multiply-accumulate (MAC) value of the first bit of the first input signal and the first bit of the second input signal (Pg. 252 Col. 1 fourth paragraph discusses Mac operations being as expressed as Qj (line 11) and MAC operations happening over a number of cycles, input signals being used for MAC operation).
Chih does not explicitly teach:
in response to determining that at least one of a first bit of the first input signal or a first bit of the second input signal obtained in a current cycle is not equal to a first logic value
in response to determining that the first bit of the first input signal and the first bit of the second input signal obtained in the current cycle are each equal to the first logic value, outputting the MAC value as a stored product computed based on a second bit of the first input signal and a second bit of the second input signal obtained in a previous cycle.
However, Son teaches a controller with a zero detection logic unit that takes in the two input signals and determines if they are at a first logic value i.e., logic zero, and if so rather than compute the MAC value as usual, to output the first logic value i.e., logic zero (Son: Fig. 35 element 1300 control unit with element 1100 zero detection logic unit within; ¶ 0156 - ¶ 0158), while taking into consideration clock cycles for synchronization of reading in operands (Son: ¶ 0071), as well as using stored products as a MAC value calculated in a previous layer i.e., in a previous cycle (Son: ¶ 0083 - ¶ 0084).
It would be obvious to combine the zero detection and outputting of a logic value as taught by Son with the method as taught by Chih as both teachings are directed towards in-memory processing of MAC operations. One with ordinary skill in the art would be motivated to combine the teachings as doing so would allow for a reduction in power consumption (Son: ¶ 0187).
Chih in view of Son therefore teaches:
A method, comprising:
receiving a first input signal and a second input signal;
in response to determining that at least one of a first bit of the first input signal or a first bit of the second input signal obtained in a current cycle is not equal to a first logic value, computing a multiply-accumulate (MAC) value of the first bit of the first input signal and the first bit of the second input signal; and
in response to determining that the first bit of the first input signal and the first bit of the second input signal obtained in the current cycle are each equal to the first logic value, outputting the MAC value as a stored product computed based on a second bit of the first input signal and a second bit of the second input signal obtained in a previous cycle.
Regarding claim 20, while Chih teaches the MAC operation as a sum of the first bit of the first input signal multiplied by a first weight and the first bit of the second input signal multiplied by a second weight (Chih: Pg. 252 Col. 1 fourth paragraph discusses Mac operations beign as expressed as Qj and MAC operations happening over a number of cycles), Chih does not explicitly teach generating a control signal according to the first bits of the first and second input signals or operations being determined in response to a logic inverse of the control signal.
However, Son teaches:
generating a control signal according to the first bit of the first input signal and the first bit of the second input signal obtained in the current cycle (Son: ¶ 0156 - ¶ 0158 a control signal is generated based on the zero detection logic processing the first bit of the first and second input signals; ¶ 0071 reading in operands based on clock cycles);
in response to a logic inverse of the control signal being equal to a second logic value, ceasing computing the MAC value thereby outputting the MAC value as the first logic value (Son: ¶ 0156 - ¶ 0158 control logic outputs a ‘1’ second logic value when all the values are ‘0’ first logic value, causing the MAC value to be outputted as ‘0’ first logic value);
in response to the logic inverse of the control signal being equal to the first logic value, computing the MAC value as a sum of the first bit of the first input signal multiplied by a first weight and the first bit of the second input signal multiplied by a second weight (Son: ¶ 0156 - ¶ 0158 input to multiplier for MAC operation is disabled only in the case that at least one of the two input signals are 0, otherwise MAC operations are calculated as usual with no disabling of the multipliers for MAC operations).
The motivation to combine with respect to claim 19 applies equally to claim 20.
Conclusion
Applicant's amendment necessitated the new reasons of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIA DE JESUS RIVERA whose telephone number is (571)272-2793. The examiner can normally be reached Monday-Friday 7:30AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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