DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LIN (US 20140217597).
Regarding claim 1, LIN discloses a wiring substrate, comprising:
a dielectric layer (174 can be a dielectric layer, see fig 6a-b, para 56) that includes a plurality of unit regions (the regions overlapping 124, see fig 6a-b, para 46 and figure I below), a sawing region that surrounds each of the unit regions (the region between and surrounding 240 in which the sawing 246 will happen, see fig 6a-b and fig 6d, para 81 and figure I below), and an edge region that surrounds the unit regions and the sawing region (the region surrounding the unit and sawing regions in fig 6a-b, and see figure I below), when viewed in plan view (fig 6b is a plan view, see para 78);
a first upper protection pattern contacting a top surface of the dielectric layer on the unit regions and the sawing region (the dielectric 240 is at least indirectly in contact with the top surface of 174, see fig 6a-b, para 77); and
a second upper protection pattern contacting a top surface of the dielectric layer on the edge region (dielectric layer 164 which is in direct contact with the top surface of 174, see fig 6a-b, para 53),
wherein the second upper protection pattern surrounds the first upper protection pattern when viewed in the plan view (164 surrounds 240 in fig 6b which is a plan view) and includes a dielectric material different from a dielectric material of the first upper protection pattern (164 can be an epoxy resin with filler and 240 can be a polymer or glue, see fig 6b, para 77 and 53).
Regarding claim 2, LIN discloses the wiring substrate of claim 1, wherein the first upper protection pattern covers the unit regions and the sawing region (240 covers at least portions of the unit region including 124 and the sawing region between 124, see fig 6a-b).
Regarding claim 3, LIN discloses the wiring substrate of claim 1, further comprising:
upper wire patterns on the top surface of the dielectric layer on each of the unit regions (there are a plurality of electrode patterns 132 on the upper surface of 174, see fig 6a, para 48),
wherein the upper wire patterns are surrounded by the second upper protection pattern (164 is located on each side of 132, see fig 6a-b).
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Figure I: LIN figure 6 with added annotations
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIN (US 20140217597) in view of HAYASHI (US 20120198826).
Regarding claim 4, LIN discloses the wiring substrate of claim 1.
LIN fails to explicitly disclose a device, wherein each of the dielectric material of the first upper protection pattern and the dielectric material of the second upper protection pattern includes fillers, and
wherein a content of the fillers in the first upper protection pattern is different from a content of the fillers in the second upper protection pattern.
HAYASHI teaches a device, wherein each of the dielectric material of the first upper protection pattern (insulating layer 10 can be formed of a resin base 10 with a first filler 13a, see fig 1, para 38) and the dielectric material of the second upper protection pattern (second insulating layer 12a can contain filler 13b, see fig 1, para 56) includes fillers, and
wherein a content of the fillers in the first upper protection pattern is different from a content of the fillers in the second upper protection pattern (first insulating layer 10 can be 60% filler and 12a can be 10% filler, see fig 1, para 38 and 56).
LIN and HAYASHI are analogous art because they both are directed towards electric connection devices for semiconductor chips and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LIN with the dielectric fillers of HAYASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LIN with the dielectric fillers of HAYASHI in order to improve the signal transmission characteristics of the device (see HAYASHI para 110).
Regarding claim 6, LIN and HAYASHI disclose the wiring substrate of claim 4.
LIN fails to explicitly disclose a device, wherein the fillers include silicon oxide (SiO2).
HAYASHI teaches a device, wherein the fillers include silicon oxide (SiO2) (13a can be SiO2, see fig 1, para 38).
LIN and HAYASHI are analogous art because they both are directed towards electric connection devices for semiconductor chips and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LIN with the dielectric fillers of HAYASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LIN with the dielectric fillers of HAYASHI in order to improve the signal transmission characteristics of the device (see HAYASHI para 110).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIN (US 20140217597) in view of KOBAYASHI (US 20180315691).
Regarding claim 5, LIN discloses the wiring substrate of claim 4.
LIN fails to explicitly disclose a device, wherein each of the dielectric material of the first upper protection pattern and the dielectric material of the second upper protection pattern includes a solder resist.
KOBAYASHI teaches a device, wherein each of the dielectric material of the first upper protection pattern (the inner part of SR1, under CHP can be solder resist, see fig 3, para 63) and the dielectric material of the second upper protection pattern (the material of the outer portion of SR1 surrounding CHP, see fig 2-3, para 63) includes a solder resist.
LIN and KOBOYASHI are analogous art because they both are directed towards connection structures for semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LIN with the solder resist of KOBOYASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LIN with the solder resist of KOBOYASHI in order to improve the degree of freedom of the wiring design (see KOBAYASHI para 98).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIN (US 20140217597) in view of KUDO (US 20150235955).
Regarding claim 7, LIN discloses the wiring substrate of claim 1.
LIN fails to explicitly disclose a device, wherein the second upper protection pattern includes a material whose adhesive force is less than an adhesive force of the first upper protection pattern.
KUDO teaches a device, wherein the second upper protection pattern includes a material whose adhesive force is less than an adhesive force of the first upper protection pattern (the adhesive force between 107 and the first lower insulating layer of SiO2 105 can be 800 N/cm and the adhesive force between 107 and the second upper insulating layer of polyimide 106 can be 300 N/cm, see fig 1, para 101).
LIN and KUDO are analogous art because they both are directed towards electrical connection structures for semiconductor chips and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LIN with the material of KUDO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LIN with the material of KUDO in order to decrease the tensile stress in the connection hole (see KUDO para 101).
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIN (US 20140217597) in view of KASAHARA (US 20190221505).
Regarding claim 8, LIN discloses the wiring substrate of claim 1.
LIN fails to explicitly disclose a device, wherein the first and second upper protection patterns have a thickness of about 10 microns to about 20 microns.
KASAHARA teaches a device, wherein the first and second upper protection patterns have a thickness of about 10 microns to about 20 microns (first upper insulating layer 12 can be 15 microns thick, see fig 2, para 34 and second upper insulating layer 14 can be 15 microns, see fig 2, para 37).
LIN and KASAHARA are analogous art because they both are directed towards electric connection structures for semiconductor chips and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LIN with the materials and feature sizes of KASAHARA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LIN with the materials and feature sizes of KASAHARA in order to improve the strength (see KASAHARA para 50).
Regarding claim 9, LIN discloses the wiring substrate of claim 1.
LIN fails to explicitly disclose a device, wherein the dielectric layer has a thickness of about 20 microns to about 100 microns.
KASAHARA teaches a device, wherein the dielectric layer has a thickness of about 20 microns to about 100 microns (the thickness of 22 can be 30 microns, see fig 2, para 33 and 39).
LIN and KASAHARA are analogous art because they both are directed towards electric connection structures for semiconductor chips and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LIN with the materials and feature sizes of KASAHARA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LIN with the materials and feature sizes of KASAHARA in order to improve the strength (see KASAHARA para 50).
Regarding claim 10, LIN discloses the wiring substrate of claim 1, further comprising:
a plurality of lower wire patterns on a bottom surface of the dielectric layer on each of the unit regions (the plurality of electrodes 176 on the bottom of 174, see fig 6a, para 57); and
a lower protection layer on the bottom surface of the dielectric layer on the unit regions and the sawing region (fig 6a, 178, para 58).
LIN fails to explicitly disclose a device further comprising wherein the lower protection layer includes a dielectric material the same as a dielectric material of the first upper protection pattern.
KASAHARA teaches a device further comprising wherein the lower protection layer includes a dielectric material the same as a dielectric material of the first upper protection pattern (lower insulating protective layer 24 can be the same as the upper insulating protective layer 14, see fig 2, para 42 and 36).
LIN and KASAHARA are analogous art because they both are directed towards electric connection structures for semiconductor chips and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LIN with the materials and feature sizes of KASAHARA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LIN with the materials and feature sizes of KASAHARA in order to improve the strength (see KASAHARA para 50).
Response to Arguments
Applicant's arguments filed 11/10/2025 have been fully considered but they are not persuasive.
Regarding claim 1, the applicant argues that LIN does not disclose a device comprising “a first upper protection pattern contacting a top surface of the dielectric layer on the unit regions and the sawing region; and a second upper protection pattern contacting a top surface of the dielectric layer on the edge region,” because 240, which the examiner relies upon as the first upper protection pattern, is separated from the dielectric layer 174 by the second upper protection pattern 164. This argument is unpersuasive because the claim does not require that the first upper protection patter by in direct contact with the dielectric layer, only that they be in contact. This allows for indirect contact by means of an intervening layer. LIN discloses, in figure 6, a device wherein the first upper protection pattern 240 is at least indirectly in contact with the dielectric layer 174. For at least this reason, and those given in the rejection above, LIN discloses every element of claim 1, which is not patentable over LIN.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811