DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MOTOHASHI (US 20110221071).
Regarding claim 1, MOTOHASHI discloses a wiring substrate, comprising:
a dielectric layer (the lower layer 10 that includes dielectric 12, see fig 2 and 12-13, para 35) that includes a plurality of unit regions (portions of the circuit formation region 110 in which 3 are formed, see fig 2 and 12-13, para 40 and 36), a sawing region (the inner regions of 110 and 120 close to 110, see fig 2 and 12-13, para 40) that surrounds each of the unit regions, and an edge region (the outer region of 120 near the edge of the device , see fig 2) that surrounds the unit regions and the sawing region, when viewed in plain view (see fig 2 and figure I below);
a first upper protection pattern (5 which directly contacts the top surface of 32, see fig 12, para 38) directly contacting a top surface of the dielectric layer on the unit regions and the sawing region (32 directly contacts the top surface of 10, see fig 12 and figure I below); and
a second upper protection pattern (fig 2 and 12, 5, para 38) contacting a top surface of the dielectric layer on the edge region (5 directly contacts a top surface of 10, see fig 12),
wherein the second upper protection pattern surrounds the first upper protection pattern when viewed in the plan view (5 surrounds 32, see fig 2 and 12) and includes a dielectric material different from a dielectric material of the first upper protection pattern (5 is a resin containing filler and 32 is a resin not containing filler, see para 38).
Regarding claim 2, MOTOHASHI discloses the wiring substrate of claim 1, wherein the first upper protection pattern covers the unit regions and the sawing region (32 at least partially covers 10 in the unit and sawing region, see fig 12 and figure I below).
Regarding claim 3, MOTOHASHI discloses the wiring substrate of claim 1, further comprising:
upper wire patterns (wiring patterns 31, see fig 4 and 12, para 36) on the top surface of the dielectric layer on each of the unit regions (31 are formed directly on the top surface of 10, see fig 4),
wherein the upper wire patterns are surrounded by the second upper protection pattern (31 is surrounded by 5, see fig 12).
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Figure I: MOTOHASHI figure 12 with added annotations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over MOTOHASHI (US 20110221071) in view of HAYASHI (US 20120189826).
Regarding claim 4, MOTOHASHI discloses the wiring substrate of claim 1.
MOTOHASHI fails to explicitly disclose a device, wherein each of the dielectric material of the first upper protection pattern and the dielectric material of the second upper protection pattern includes fillers, and
wherein a content of the fillers in the first upper protection pattern is different from a content of the fillers in the second upper protection pattern.
HAYASHI teaches a device, wherein each of the dielectric material of the first upper protection pattern (insulating layer 10 can be formed of a resin base 10 with a first filler 13a, see fig 1, para 38) and the dielectric material of the second upper protection pattern (second insulating layer 12a can contain filler 13b, see fig 1, para 56) includes fillers, and
wherein a content of the fillers in the first upper protection pattern is different from a content of the fillers in the second upper protection pattern (first insulating layer 10 can be 60% filler and 12a can be 10% filler, see fig 1, para 38 and 56).
MOTOHASHI and HAYASHI are analogous art because they both are directed towards semiconductor mounting substrates and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MOTOHASHI with the filler content of HAYASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MOTOHASHI with the filler content of HAYASHI in order to improve the signal transmission characteristics of the device (see HAYASHI para 110).
Regarding claim 6, MOTOHASHI discloses the wiring substrate of claim 4.
MOTOHASHI fails to explicitly disclose a device, wherein the fillers include silicon oxide (SiO2).
HAYASHI teaches a device, wherein the fillers include silicon oxide (SiO2) (13a can be SiO2, see fig 1, para 38).
MOTOHASHI and HAYASHI are analogous art because they both are directed towards semiconductor mounting substrates and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MOTOHASHI with the filler content of HAYASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MOTOHASHI with the filler content of HAYASHI in order to improve the signal transmission characteristics of the device (see HAYASHI para 110).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over MOTOHASHI (US 20110221071) in view of HAYASHI (US 20120189826) and further in view of KOBOYASHI (US 20180315691).
Regarding claim 5, MOTOHASHI and HAYASHI disclose the wiring substrate of claim 4.
MOTOHASHI and HAYASHI fail to explicitly disclose a device, wherein each of the dielectric material of the first upper protection pattern and the dielectric material of the second upper protection pattern includes a solder resist.
KOBOYASHI teaches a device, wherein each of the dielectric material of the first upper protection pattern (the inner part of SR1, under CHP can be solder resist, see fig 3, para 63) and the dielectric material of the second upper protection pattern (the material of the outer portion of SR1 surrounding CHP, see fig 2-3, para 63) includes a solder resist.
MOTOHASHI, HAYASHI and KOBOYASHI are analogous art because they both are directed towards semiconductor device mounting substrates and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MOTOHASHI and HAYASHI with the material of KOBOYASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MOTOHASHI and HAYASHI with the material of KOBOYASHI in order to improve the degree of freedom of the wiring design (see KOBAYASHI para 98).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over MOTOHASHI (US 20110221071) in view of KUDO (US 20150235955).
Regarding claim 7, MOTOHASHI discloses the wiring substrate of claim 1.
MOTOHASHI fails to explicitly disclose a device, wherein the second upper protection pattern includes a material whose adhesive force is less than an adhesive force of the first upper protection pattern.
KUDO teaches a device, wherein the second upper protection pattern includes a material whose adhesive force is less than an adhesive force of the first upper protection pattern (the adhesive force between 107 and the first lower insulating layer of SiO2 105 can be 800 N/cm and the adhesive force between 107 and the second upper insulating layer of polyimide 106 can be 300 N/cm, see fig 1, para 101).
MOTOHASHI and KUDO are analogous art because they both are directed towards mounting substrates for semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MOTOHASHI with the adhesive materials of KUDO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MOTOHASHI with the adhesive materials of KUDO in order to decrease the tensile stress in the connection hole (see KUDO para 101).
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over MOTOHASHI (US 20110221071) in view of KASAHARA (US 20190221505).
Regarding claim 8, MOTOHASHI discloses the wiring substrate of claim 1.
MOTOHASHI fails to explicitly disclose a device, wherein the first and second upper protection patterns have a thickness of about 10 microns to about 20 microns.
KASAHARA teaches a device, wherein the first and second upper protection patterns have a thickness of about 10 microns to about 20 microns (first upper insulating layer 12 can be 15 microns thick, see fig 2, para 34 and second upper insulating layer 14 can be 15 microns, see fig 2, para 37).
MOTOHASHI and KASAHARA are analogous art because they both are directed towards mounting substrates for semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MOTOHASHI with the layer thickness of KASAHARA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MOTOHASHI with the layer thickness of KASAHARA in order to improve the strength (see KASAHARA para 50).
Regarding claim 9, MOTOHASHI discloses the wiring substrate of claim 1.
MOTOHASHI fails to explicitly disclose a device, wherein the dielectric layer has a thickness of about 20 microns to about 100 microns.
KASAHARA teaches a device, wherein the dielectric layer has a thickness of about 20 microns to about 100 microns (the thickness of 22 can be 30 microns, see fig 2, para 33 and 39).
MOTOHASHI and KASAHARA are analogous art because they both are directed towards mounting substrates for semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MOTOHASHI with the layer thickness of KASAHARA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MOTOHASHI with the layer thickness of KASAHARA in order to improve the strength (see KASAHARA para 50).
Regarding claim 10, MOTOHASHI discloses the wiring substrate of claim 1, further comprising:
a plurality of lower wire patterns (fig 13, 4, para 35) on a bottom surface of the dielectric layer on each of the unit regions (4 is on the bottom surface of 10, see fig 13).
MOTOHASHI fails to explicitly disclose a device further comprising a lower protection layer on the bottom surface of the dielectric layer on the unit regions and the sawing region,
wherein the lower protection layer includes a dielectric material the same as a dielectric material of the first upper protection pattern.
KASAHARA teaches a device further comprising a lower protection layer (24 on the bottom surface of 22, see fig 2, para 31) on the bottom surface of the dielectric layer on the unit regions and the sawing region,
wherein the lower protection layer includes a dielectric material the same as a dielectric material of the first upper protection pattern (lower insulating protective layer 24 can be the same as the upper insulating protective layer 14, see fig 2, para 42 and 36).
MOTOHASHI and KASAHARA are analogous art because they both are directed towards mounting substrates for semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of MOTOHASHI with the lower layers of KASAHARA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of MOTOHASHI with the lower layers of KASAHARA in order to improve the strength (see KASAHARA para 50).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811
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