THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND METHODS OF FABRICATING THE DEVICES

Application No. 17/828,170

• Filed: May 31, 2022
• Examiner: SWANSON, WALTER H
• Art Unit: 2815
• Tech Center: 2800 — Semiconductors & Electrical Systems
• Assignee: Samsung Electronics Co., Ltd.
• OA Round: 1 (Non-Final)

Office Action

DETAILED ACTION
AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicants' claim for foreign priority based on an application filed in KOREA on 14 SEP 2021. It is noted that applicants have filed a certified copy of said application as required by U.S.C 119, which papers have been placed of record in the file. See 29 JUN 2022 submission.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 31 MAY 2022 and 4 FEB 2026 were filed before the mailing of a first Office action on the merits. The submissions follow provisions of 37 CFR 1.97. Accordingly, the IDSs are being considered by the examiner.
Claim Objections
The following claim language lacks sufficient antecedent basis (MPEP § 2173.05(e)) or includes a typographical error.
Typographical errors:
claim 6, line 3, replace “first” with “second” (see base claim 1, lines 4 and 8-9); and
claim 14, line 3, replace “first” with “second” (see base claim 9, lines 4 and 8-9).
Appropriate correction is required.

Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows (Graham Factors):

1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.

Claims 1-15 and 31-35 are rejected under 35 U.S.C. 103 as obvious over Jeon et al. (KR 20210025032; below, “Jeon” – 31 MAY 2022 IDS noted prior art reference) with evidence from and/or in view of CHOI (KR 20210052928; below, “CHOI” – 4 FEB 2026 IDS noted prior art reference). At least “combining prior art elements”, “simple substitution”, “obvious to try”, and “applying a known technique to a known method” rationales support a conclusion of obviousness. MPEP § 2143(A)-(G).
RE 1, Jeon, in FIGS. 1-16 and related text, e.g., Abstract, paragraphs [0001] to [0125], discloses a method of fabricating a three-dimensional semiconductor memory device, the method comprising:

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forming a peripheral circuit structure (PS) on a first surface of a first substrate (20);
forming a cell array structure (CS) on a first surface of a second substrate (10); and
attaching the cell array structure (CS) to the peripheral circuit structure (PS) such that the first surface of the first substrate (20) and the first surface of the second substrate (10) face each other,
wherein the forming of the cell array structure (CS) comprises:
forming a back-side via (LP1) and a preliminary contact pad (LP2) on the first surface of the second substrate (10);
(see CHOI for: forming a semiconductor layer contacting top surfaces of the back-side via (LP1) and the preliminary contact pad (LP2);
forming a hole (hole for PPLG) extending through the semiconductor layer (see CHOI) and exposing the preliminary contact pad (LP2) and removing an upper portion of the preliminary contact pad (LP2), thereby forming a contact pad separated from the semiconductor layer (see CHOI);
forming a stack (ST) on the semiconductor layer (see CHOI);
forming a first insulating layer (110) on the stack (ST); and
forming a contact plug (PPLG) extending through the first insulating layer (110) and being connected to the contact pad (LP2).
Jeon is silent regarding forming a semiconductor layer contacting top surfaces of the back-side via (LP1) and the contact pad (LP2); forming a hole extending through the semiconductor layer and exposing the preliminary contact pad (LP2) and removing an upper portion of the preliminary contact pad, thereby forming a contact pad separated from the semiconductor layer.

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CHOI, in FIGS. 3a to 13i and related text, Abstract, paragraphs [0001] to [0246], teaches forming a semiconductor layer (31A, 20C) contacting top surfaces of a back-side via (11A) and a contact pad (11C); forming a hole (e.g., OP1) extending through the semiconductor layer (31A, 20C) and exposing the preliminary contact pad (11C in lieu of LP2) and removing an upper portion of the preliminary contact pad (11C), thereby forming a contact pad separated from the semiconductor layer (20C).
Jeon and CHOI are analogous art from the same field of endeavor as the claimed invention. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify Jeon as taught by CHOI because: 1. signal integrity/power delivery is enhanced by reducing resistance at contact interface; 2. better thermal management is achieved due to conductive layer; and 3. all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007).
RE 2, modified Jeon discloses the method of claim 1, wherein the forming of the back-side via (LP1) and the preliminary contact pad (LP2) comprises:
forming a second insulating layer (110) on the second substrate (10):
forming a first hole (T1) and a second hole (T2) extending through the second insulating layer (110); and
forming the back-side via (LP1) in the first hole (T1) and forming the preliminary contact pad (LP2) in the second hole (T2) by forming a conductive material in the first hole (T1) and the second hole (T2).
RE 3, modified Jeon discloses the method of claim 2, wherein the semiconductor layer (CHOI’s 31A, 20C) is formed of the conductive material (material not particularly limited).
RE 4, modified Jeon is silent regarding the method of claim 3, wherein the conductive material comprises poly silicon.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to use poly silicon; since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
RE 5, modified Jeon discloses the method of claim 2, wherein the conductive material comprises tungsten, titanium, and/or tantalum (e.g., [0055]-[0058]), and
the semiconductor layer (31A, 20C) comprises poly silicon (material not particularly limited).
RE 6, modified Jeon discloses the method of claim 1, after the attaching the cell array structure (CS) to the peripheral circuit structure (PS), further comprising:
removing the first ([sic], “second”?) substrate (10) to expose the back-side via (LP1) and the contact pad (LP2);
forming a third insulating layer (50) on the back-side via (LP1) and the contact pad (LP2); and
forming a via (narrow part of LP2) extending through the third insulating layer (50) and being connected to the contact plug (PPLG).
RE 7, modified Jeon discloses the method of claim 6, further comprising forming a back-side conductive pattern (PAD) on the via (narrow part of LP2).
RE 8, modified Jeon discloses the method of claim 6, wherein the via (narrow part of LP2) extends into the contact pad (LP2).
RE 9, Jeon, in FIGS. 1-16 and related text, e.g., Abstract, paragraphs [0001] to [0125], discloses a method of fabricating a three-dimensional semiconductor memory device, the method comprising:
forming a peripheral circuit structure (PS) on a first surface of a first substrate (20);
forming a cell array structure (CS) on a first surface of a second substrate (10);
and
attaching the cell array structure (CS) to the peripheral circuit structure (PS) such that the first surface of the first substrate (20) and the first surface of the second substrate (10) face each other,
wherein the forming of the cell array structure (CS) comprises:
forming a back-side via (LP1) and a contact pad (LP2) on the first surface of the second substrate (10);
(see CHOI for: forming a semiconductor layer on the back-side via (LP1) and the contact pad (LP2);
forming a stack (ST) on the semiconductor layer (see CHOI);
forming a first insulating layer (120) on the stack (ST); and
forming a contact plug (PPLG) extending through the first insulating layer (120) and being connected to the contact pad (LP2),
wherein the forming of the back-side via (LP1) and the contact pad (LP2) comprises:
forming a second insulating layer (110) on the second substrate (10);
forming a first hole (T1+VH1) and a second hole (T2+VH2) extending through the second insulating layer (110); and
forming a conductive material in the first hole (T1+VH1) and the second hole (T2+VH2).
Jeon is silent regarding forming a semiconductor layer on the back-side via (LP1) and the contact pad (LP2).
CHOI, in FIGS. 3a to 13i and related text, Abstract, paragraphs [0001] to [0246], teaches forming a semiconductor layer (31A, 20C) on a back-side via (11A) and a contact pad (11C).
Jeon and CHOI are analogous art from the same field of endeavor as the claimed invention. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify Jeon as taught by CHOI because: 1. signal integrity/power delivery is enhanced by reducing resistance at contact interface; 2. better thermal management is achieved due to conductive layer; and 3. all the claimed elements were known … and one … could have combined the elements …, and the combination would have yielded predictable results …. KSR, 550 U.S. 398 (2007).
RE 10, modified Jeon discloses the method of claim 9, wherein the forming of the cell array structure (CS) further comprises forming a third hole (e.g., OP1) extending through the semiconductor layer (CHOI’s 20C) and exposing the contact pad (CHOI’s 11C), and
during the forming of the third hole (OP1), an upper portion of the contact pad (CHOI’s 11C) is removed such that the contact pad (11C) is spaced apart from the semiconductor layer (20C).
RE 11, modified Jeon discloses the method of claim 9, wherein the semiconductor layer (31A, 20C) is formed of the conductive material (materials not particularly limited).
RE 12, modified Jeon is silent regarding the method of claim 9, wherein the conductive material comprises poly silicon.
It would have been obvious … to use poly silicon; since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
RE 13, modified Jeon discloses the method of claim 9, wherein the conductive material comprises tungsten, titanium, and/or tantalum (e.g., [0055]-[0058]), and
the semiconductor layer (31A, 20C) comprises poly silicon (material not particularly limited).
RE 14, modified Jeon discloses the method of claim 9, after the attaching of the
cell array structure (CS) to the peripheral circuit structure (PS), further comprising:
removing the first ([sic], “second”?) substrate (10) to expose the back-side via (LP1) and the contact pad (LP2);
forming a third insulating layer (50) on the back-side via (LP1) and the contact pad (LP2); and
forming a via (narrow part of LP2) extending through the third insulating layer (50) and being connected to the contact plug (PPLG).
RE 15, modified Jeon discloses the method of claim 14, further comprising forming a back-side conductive pattern (e.g., PAD) on the via (narrow part of LP2).
RE 31, Jeon, in FIGS. 1-16 and related text, e.g., Abstract, paragraphs [0001] to [0125], discloses a method of fabricating a semiconductor device, the method comprising:
forming a cell array structure (CS) on a substrate (10); and
attaching the cell array structure (CS) to a peripheral circuit structure (PS), wherein the cell array structure (CS) is between the substrate (10) and the peripheral circuit structure (PS) after the attaching,
wherein forming the cell array structure (CS) comprises:

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forming a first insulating layer (110) comprising a first hole (T1+VH1) and a second hole (T2+VH2) on the substrate (10), the first and second holes extending through the first insulating layer (110) and exposing the substrate (10);
forming a back-side via (LP1) in the first hole (T1+VH1) and a preliminary contact pad (LP2) in the second hole (T2+VH2) by forming portions of a conductive layer respectively in the first and second holes;
(see CHOI for: forming a semiconductor layer (31A, 20C) extending on the first insulating layer (110) and contacting the back-side via (LP1) and the preliminary contact pad (LP2);
forming a third hole extending through the semiconductor layer (see CHOI) and exposing the preliminary contact pad (LP2);
forming a contact pad (LP2) by removing a portion of the preliminary contact pad (LP2) through the third hole;
forming a stack (ST) on the semiconductor layer (see CHOI);
forming a second insulating layer (120) on the stack (ST); and
forming a contact plug (PPLG) extending through the second insulating layer (120) and contacting the contact pad (LP2).
Jeon is silent regarding forming a semiconductor layer on the back-side via (LP1) and the contact pad (LP2).
CHOI, in FIGS. 3a to 13i and related text, Abstract, paragraphs [0001] to [0246], teaches forming a semiconductor layer (31A, 20C) on a back-side via (11A) and a contact pad (11C).
Jeon and CHOI are analogous art from the same field of endeavor as the claimed invention. It would have been obvious … to modify Jeon as taught by CHOI because: 1. signal integrity/power delivery is enhanced by reducing resistance at contact interface; 2. better thermal management is achieved due to conductive layer; and 3. all the claimed elements were known … and one … could have combined the elements …, and the combination would have yielded predictable results …. KSR, 550 U.S. 398 (2007).
RE 32, modified Jeon is silent regarding the method of claim 31, wherein the conductive layer comprises poly silicon.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to use poly silicon; since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
RE 33, modified Jeon discloses the method of claim 31, wherein the back-side
via (LP1) contacts (FIG. 13) the substrate (10).
RE 34, modified Jeon discloses the method of claim 33, wherein forming the cell array structure (CS) further comprises forming a channel structure (CH, FIG. 3a) extending through the stack (ST) and contacting the semiconductor layer (CHOI’s 31A).
RE 35, modified Jeon discloses the method of claim 31, wherein the first insulating layer (110) and the contact pad (LP2) each comprise a lower surface facing the substrate (10) and an upper surface opposite the lower surface, and
the upper surface of the contact pad (LP2) is recessed (CHOI’s OP1) toward the substrate (10) relative to the upper surface of the first insulating layer (110).
Claims 1-15 and 31-35 are rejected.
Conclusion
The prior art made of record and not relied upon, Chuang et al. (US 20210358891), is considered pertinent to applicants’ disclosure. Chuang et al. does not teach, inter alia, forming a hole (184, FIG. 11A) extending through the semiconductor layer (195) and exposing the preliminary contact pad (192) and removing an upper portion of the preliminary contact pad (192), thereby forming a contact pad (193) separated from the semiconductor layer (195); forming a stack (ST, FIG. 13A) on the semiconductor layer (195); forming a first insulating layer (50, 60, FIG. 13A) on the stack (ST); and forming a contact plug (TCP, FIG. 13A) extending through the first insulating layer (50, 60) and being connected to the contact pad (193).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Walter Swanson whose telephone number is [phone]. The examiner can normally be reached Monday to Thursday, 8:30 to 17:30 EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez, can be reached on [phone]. The fax phone number for the organization where this application or proceeding is assigned is [phone].
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/WALTER H SWANSON/Primary Examiner, Art Unit 2815

Prosecution Timeline

• May 31, 2022: Application Filed
• Feb 20, 2026: Non-Final Rejection — §103
• Mar 24, 2026: Applicant Interview (Telephonic)
• Mar 30, 2026: Examiner Interview Summary