Status of Claims
Claims 1-12 and 21-34 are pending.
Claims 13-20 are cancelled.
Response to Amendment
The amendment filed on 03/30/2026 has been accepted and entered
Response to Arguments
Applicant’s arguments, see Objections to the Drawings on page 6 of Applicant’s remarks, filed 03/30/2026, with respect to the Objection to the Drawings in the non-final rejection filed 11/28/2025 have been fully considered and are persuasive in view of the amendments to the claims. The Objection to the Drawings has been withdrawn.
Applicant’s arguments, see Claim Rejections under 35 U.S.C. 112 on page 6 of Applicant’s remarks, filed 03/30/2026, with respect to the rejection under 35 U.S.C. 112(a) in the non-final rejection filed 11/28/2025 of claims 5-12 have been fully considered and are persuasive in view of the amendments to the claims. The rejections under 35 U.S.C. 112(a) to claims 5-12 has been withdrawn.
Applicant’s arguments, see Claim Rejections under 35 U.S.C. 112 on page 6 of Applicant’s remarks, filed 03/30/2026, with respect to the rejection under 35 U.S.C. 112(b) in the non-final rejection filed 11/28/2025 of claims 21-24 and 30-39 have been fully considered and are persuasive in view of the amendments to the claims. The rejections under 35 U.S.C. 112(b) to claims 21-24 and 30-39 has been withdrawn.
Applicant’s amendment to independent claim 1, and its respective dependent claims and corresponding arguments, see page 7 of Applicant’s remarks filed 03/30/2026, with respect to the 35 U.S.C. 103 rejection of claim 1 has been fully considered and is persuasive. The standing rejection of claim 1 as being unpatentable over Frey in view of Chen does not teach all of the limitations of amended claim 1 (i.e. “a trench circumscribing a region of the semiconductor substrate”) and thus and its respective dependent claims.
In view of the amendment, new grounds of rejection have been applied (see below). Independent claim 1 now stands rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0038030 A1 Frey et al in view of US 2020/0006309 A1 Chen et al and further in view of US 2020/0203290 A1 Summerfelt et al.
Applicant’s amendment to independent claim 25, and its respective dependent claims and corresponding arguments, see page 7 of Applicant’s remarks filed 03/30/2026, with respect to the 35 U.S.C. 102 rejection of claim 25 has been fully considered and is persuasive. The standing rejection of claim 25 as being anticipated by Chen does not teach all of the limitations of amended claim 25 (i.e. “the semiconductor substrate including a trench that extends between the first and second surfaces and circumscribes a region of the semiconductor substrate”) and thus and its respective dependent claims.
In view of the amendment, new grounds of rejection have been applied (see below). Independent claim 25 now stands rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0006309 A1 Chen et al in view of US 2020/0203290 A1 Summerfelt et al.
Applicant’s amendment to independent claim 28, and its respective dependent claims and corresponding arguments, see page 7 of Applicant’s remarks filed 03/30/2026, with respect to the 35 U.S.C. 103 rejection of claim 28 has been fully considered and is persuasive. The standing rejection of claim 28 as being unpatentable over Frey in view of Chen does not teach all of the limitations of amended claim 28 (i.e. “at least one of the first trench or the second trench is partially filled by the dielectric material”) and thus and its respective dependent claims.
In view of the amendment, new grounds of rejection have been applied (see below). Independent claim 28 now stands rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0038030 A1 Frey et al in view of US 2020/0006309 A1 Chen et al.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-12, 21-24, and 32-33 are rejected under 35 U.S.C. 103 as being obvious over US 2012/0038030 A1 Frey et al (herein “Frey”) in view of US 2020/0006309 A1 Chen et al (herein “Chen”) and further in view of US 2020/0203290 A1 Summerfelt et al (herein “Summerfelt”)).
Regarding Claim 1, Frey discloses:
See generally Figs. 1-3 disclosing semiconductor substrate with isolation trenches.
a semiconductor substrate (#10);
a trench (#20A);
Frey does not explicitly disclose:
An integrated circuit comprising a semiconductor substrate;
a metallization stack overlapping the semiconductor substrate, the metallization stack having a portion that extends out of a footprint of the semiconductor substrate;
a trench circumscribing a region of the semiconductor substrate; and
a mold compound covering at least parts of the semiconductor substrate and the portion of the metallization stack.
However, in analogous art, Chen teaches:
An integrated circuit (see generally Figs. 1-12, specifically Fig. 12 for completed IC/SoC device unless otherwise noted) comprising a semiconductor substrate (#44A, #44B);
a metallization stack (Fig. 1, see dielectric layer #24, interconnect structure #26 comprising metal lines 28 and vias 30, which are formed in dielectric layers 32, herein referred to as #24, #26) overlapping the semiconductor substrate (#44A, #44B), the metallization stack (#24, #26) having a portion that extends out of a footprint of the semiconductor substrate (see left and right sides of metallization stack outside of footprint of #44A and #44B, see also annotated Fig. 1 below); and
a mold compound (#56) surrounding the semiconductor substrate (#44A, #44B) and the metallization stack (#24, #26).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Chen to the device disclosed by Frey since Frey shows an incomplete device, motivating those of ordinary skill to seek out teachings such as Chen to completely practice the invention of Frey. Doing so would be a substitution of materials of the metallization stack disclosed by Chen for that of the previously cited elements #12, #14, and #16, for the conductive elements and oxide elements referenced herein as #24, #26, see Chen [0018]. For the purposes of clarification for the remainder of this document, the “metallization stack” referenced in Frey (#12, #14, and #16) comprises the substituted layers from Chen for full device performance as previously motivated.
Note, Marriam Webster defines surrounding as “to extend around the margin or edge of”, in this case, looking at Chen Fig. 12 as viewed from the top down perspective, the mold compound extends all the way to the periphery of the metallization stack and dielectric layer, and fully encapsulates both substrates. It is suggested to amend the claim using a term such as fully encapsulates, fully surrounds… or something to that degree to overcome the cited prior art.
Frey in view of Chen does not explicitly disclose:
a trench circumscribing a region of the semiconductor substrate;
However, in analogous art, Summerfelt teaches:
See Fig. 6, #608, [0038].
a trench (#608) circumscribing a region (“straight portions” and “serpentine portions” of TWT in Fig. 6, [0038]) of the semiconductor substrate;
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Summerfelt to the device disclosed by Frey in view of Chen since Frey in view of Chen shows an incomplete device, motivating those of ordinary skill to seek out teachings such as Summerfelt to completely practice the invention of Frey in view of Chen. Specifically, Frey in view of Chen discloses isolation trenches #20A in Figs. 1-3, but does not provide a top-down view of the device showing isolated regions of substrate #10. Summerfelt discloses a non-linear portion #662 and a rectangular portion #612 isolated from each other by trenches #665 and #608 that surround (circumscribe) the respective portions, i.e. high-voltage vs. low voltage regions of the substrate, in order to electrically isolate the different regions from one another for optimal device performance, see [0038].
Regarding Claim 2, Frey in view of Chen and further in view of Summerfelt discloses the integrated circuit of claim 22.
Frey further discloses:
wherein the trench (#20A) is a first trench and the integrated circuit includes a second trench (see two trenches in Figs. 1-4) that extends between the first surface (top surface) and the second surface (bottom surface).
Regarding Claim 3, Frey in view of Chen and further in view of Summerfelt discloses: The integrated circuit of claim 2,
Summerfelt further teaches:
wherein the second trench is linear (see annotated Fig. 6 below).
PNG
media_image1.png
698
733
media_image1.png
Greyscale
Summerfelt Fig. 6 – Annotated by Examiner
Regarding Claim 4, Frey in view of Chen and further in view of Summerfelt discloses: The integrated circuit of claim 2,
Summerfelt further teaches:
wherein the second trench is linear (see annotated Fig. 6 above).
Regarding Claim 5, Frey in view of Chen and further in view of Summerfelt discloses: The integrated circuit of claim 2,
Summerfelt further teaches:
The integrated circuit of claim 2, wherein the second trench (see annotated Fig. 6 above) also extends between the opposing sidewall surfaces (linear trenches in annotated Fig. 6 above extend from left surface to right surface).
Regarding Claim 6, Frey in view of Chen and further in view of Summerfelt discloses: The integrated circuit of claim 21,
Summerfelt further discloses:
wherein the trench (#608, #665) is a first trench (#608), and the semiconductor substrate (#600) includes a second trench (#665) extending between the first and second surfaces (top/bottom surfaces, i.e. in/out of the page of Fig. 6, for reference see Frey Figs. 1-4 top/bottom surfaces that trench structure of Summerfelt has been applied to), the first trench (#608) and the second trench (#665) are in a first region (region disclosed as everything #600 encompasses in Fig. 6) of the semiconductor substrate (#600), the region circumscribed by the first trench (#608) is a second region (#612, Fig. 6) of the semiconductor substrate (#600), and the second trench (#665) circumscribes a third region (#661 or #662) of the semiconductor substrate (#600).
Regarding Claim 7, Frey in view of Chen and further in view of Summerfelt discloses: The integrated circuit of claim 6,
wherein the first trench (#608) and the second trench (#665) have a rectangular shape (see Fig. 6, portions of both #608 and #665 have a rectangular shape).
Regarding Claim 8, Frey in view of Chen and further in view of Summerfelt discloses: The integrated circuit of claim 6,
Frey further discloses:
wherein the first and second trenches are filled with the dielectric material (#30, [0024]).
Frey in view of Chen and further in view of Summerfelt does not explicitly disclose:
the substrate includes a third trench extending between the first and second surfaces and filled with a conductive material to form a via, an end of the via coupled to the metallization stack.
However, in analogous art, Chen further teaches:
the substrate includes a third trench (Fig. 4, #59) extending between the first (top) and second (bottom) surfaces and filled (see completed filled via structure in Fig. 12) with a conductive material ([0037]) to form a via (#60), an end (bottom end) of the via coupled to the metallization stack (#24, #26).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Chen to the device disclosed by Frey in view of Chen and further in view of Summerfelt and form a via structure in order to electrically connect a portion of the metallization stack to an external electrical pathway in order to use the device for its intended purpose.
Regarding Claim 9, Frey in view of Chen and further in view of Summerfelt discloses: The integrated circuit of claim 8,
Chen further teaches:
further comprising an interconnect (#66, #68, #74, #80, #82) over the first surface (top surface) and coupled to another end (top end) of the via (#60).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Chen to the device disclosed by Frey in view of Chen and further in view of Summerfelt and form a via structure including an overlying interconnect structure in order to electrically connect a portion of the metallization stack to an external electrical pathway in order to use the device for its intended purpose.
Regarding Claim 10, Frey in view of Chen and further in view of Summerfelt discloses: The integrated circuit of claim 9,
Chen further teaches:
See Fig. 21
wherein the semiconductor substrate (#44A, #44B) is part of a first die (lower portion of device shown in Fig. 21), the integrated circuit comprises a second die (upper portion, specifically see device die #136 in Fig. 21), and the second die (#136) is coupled to the via (#60) of the first die through the interconnect (#66, #68, #74, #80, #82, additionally see redistribution layer #150 including lines #154 and contacts #158).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Chen to the device disclosed by Frey in view of Chen and further in view of Summerfelt and form a via structure including an overlying interconnect structure in order to electrically connect a portion of the metallization stack, and subsequently the electrically connected dies to an external electrical pathway, in this case a second overlying die, in order to use the device for its intended purpose. See [0053]-[0054].
Regarding Claim 11, Frey in view of Chen and further in view of Summerfelt discloses: The integrated circuit of claim 10,
Frey further discloses:
further comprising a wire bond coupled to the via of the first die through the interconnect (see Frey [0022]: “…Contact piston 21 may be contacted by using either wire bonds on bond pad 28 or using a solder ball in the case of a flip-chip structure.”).
Regarding Claim 12, Frey in view of Chen and further in view of Summerfelt discloses: The integrated circuit of claim 21,
Frey further discloses:
wherein the dielectric material comprises a polymer material ([0024]).
Regarding Claim 21, Frey in view of Chen and further in view of Summerfelt discloses the integrated circuit of claim 1.
Chen further discloses:
wherein the semiconductor substrate (#44A, #44B) has opposing first (top) and second (bottom) surfaces and opposing sidewall surfaces (left/right sidewalls of #44A, #44B respectively),
the metallization stack (#24, #26) overlaps with the second surface (bottom surface, overlaps from top-down view), and at least one of the sidewall surfaces is covered with a dielectric material (side surfaces are directly covered with dielectric layer #54 and further covered by dielectric mold compound #56).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Chen to the device disclosed by Frey in view of Chen and further in view of Summerfelt and include the metallization stack such that it overlaps on all surfaces of the substrate other than top and bottom. In this case, with the portion that extends beyond the footprint of the substrate, it would clearly overlap the substrate and thus provide more surface area for electrical connections or other vias/interconnects in the IC device.
Regarding Claim 22, Frey in view of Chen and further in view of Summerfelt discloses the integrated circuit of claim 21.
Frey further discloses:
wherein the trench (#20A) extends between the first (top) and second (bottom) surfaces.
Regarding Claim 23, Frey in view of Chen and further in view of Summerfelt discloses: The integrated circuit of claim 22,
Frey further discloses:
wherein the dielectric material (#30) extends from the trench (#20A) onto and over the first surface (top surface, see Figs. 1-4).
Regarding Claim 24, Frey in view of Chen and further in view of Summerfelt discloses the integrated circuit of claim 21.
Chen further teaches:
wherein the dielectric material (mold compound #56, dielectric layer #54) extends from the at least one of the sidewall surfaces (side surfaces are directly covered with dielectric layer #54 and further covered by dielectric mold compound #56) onto and over the portion of the metallization stack (#24, #26).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Chen to the device disclosed by Frey in view of Chen and further in view of Summerfelt and include the dielectric layers to extend from the top surface of the semiconductor substrate down to the extra portion of the metallization stack. Doing so would ensure full electrical isolation of the metallization stack from both the top surface and the bottom surface, and additionally on sidewall surfaces which is beneficial for metal layers in contact with vias or interconnects to remain electrically isolated (only in electrical contact with the intended substrates, layers, or other vias/interconnects).
Regarding Claim 32, Frey in view of Chen discloses: The device of claim 28,
Frey in view of Chen does not explicitly disclose:
wherein the dielectric material includes a polymer.
However, in analogous art, Summerfelt teaches:
wherein the dielectric material (#110) includes a polymer.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Summerfelt to the device disclosed by Frey, as parylene is a known dielectric material in the art and would be an obvious substitution of elements, to fill in the isolation trenches in order to electrically isolate one region for another and would be a modification according to known methods that yield a predictable result.
Regarding Claim 33, Frey in view of Chen and further in view of Summerfelt discloses: The device of claim 1,
Frey in view of Chen does not explicitly disclose:
further comprising interconnects coupled to the metallization stack, the metallization stack being between the semiconductor substrate and the interconnects, wherein at least parts of the interconnects are exposed by the mold compound.
However, in analogous art, Chen teaches:
further comprising interconnects (see annotated Fig. 12 below) coupled to the metallization stack (#24, #26), the metallization stack (#24, #26) being between the semiconductor substrate (#44A, #44B) and the interconnects (see annotated Fig. 12 below), wherein at least parts of the interconnects (see annotated Fig. 12 below) are exposed by the mold compound (specifically portion #60 of the interconnect structure, see annotated Fig. 12 below).
Note, from a top down perspective, portions of the underlying metallization stack are “between” the interconnect structure and the substrates.
PNG
media_image2.png
636
796
media_image2.png
Greyscale
Chen Fig. 12 – Annotated by Examiner
(same annotated Figure as above, included here for convenience)
Claims 25-27 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0006309 A1 Chen et al (herein “Chen”) in view of US 2020/0203290 A1 Summerfelt et al (herein “Summerfelt”).
Regarding Claim 25, Chen discloses:
An integrated circuit (see generally Figs. 1-12, specifically Fig. 12 for completed IC/SoC device unless otherwise noted) comprising:
a semiconductor substrate (#44A, #44B) having opposing first (top surface) and second (bottom surface) surfaces and opposing sidewall surfaces (left/right surfaces of #44A, #44B);
a dielectric material (#54) covering at least one of the sidewall surfaces (left/right surfaces of #44A, #44B);
a metallization stack (Fig. 1, see dielectric layer #24, interconnect structure #26 comprising metal lines 28 and vias 30, which are formed in dielectric layers 32, herein referred to as #24, #26) overlapping the second surface (bottom surface, overlaps from top-down view); and
a mold compound (#56) covering the dielectric material (#54) and surrounding the semiconductor substrate (#44A, #44B) and the metallization stack (#24, #26).
Note, Marriam Webster defines surrounding as “to extend around the margin or edge of”, in this case, looking at Chen Fig. 12 as viewed from the top down perspective, the mold compound extends all the way to the periphery of the metallization stack and dielectric layer, and fully encapsulates both substrates. It is suggested to amend the claim using a term such as fully encapsulates, fully surrounds… or something to that degree to overcome the cited prior art.
Chen does not explicitly disclose:
the semiconductor substrate including a trench that extends between the first and second surfaces and circumscribes a region of the semiconductor substrate;
However, in analogous art, Summerfelt teaches:
See Fig. 6, #608, [0038].
a trench (#608) circumscribing a region (“straight portions” and “serpentine portions” of TWT in Fig. 6, [0038]) of the semiconductor substrate;
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Summerfelt to the device disclosed by Chen shows an incomplete device, motivating those of ordinary skill to seek out teachings such as Chen to completely practice the invention of Frey. Specifically, Chen discloses a dielectric isolation layer #54 and #56 in Fig. 12, and discloses in the abstract “forming a dielectric region to encircle the device die”, but does not provide a top-down view of the device showing the trenches needed to form the isolation region that surrounds the dies. Summerfelt discloses a non-linear portion #662 and a rectangular portion #612 isolated from each other by trenches #665 and #608 that surround (circumscribe) the respective portions of the substrate, i.e. high-voltage vs. low voltage regions of the substrate, in order to electrically isolate the different regions from one another for optimal device performance, see [0038].
Regarding Claim 26, Chen in view of Summerfelt discloses: The integrated circuit of claim 25,
Chen further discloses:
wherein the metallization stack (#24, #26) includes a portion that extends out of a footprint of the semiconductor substrate (see left and right sides of metallization stack outside of footprint of #44A and #44B, see also annotated Fig. 1 below).
Regarding Claim 27, Chen in view of Summerfelt discloses the integrated circuit of claim 25.
Chen does not explicitly disclose:
wherein the dielectric material includes a polymer.
However, in analogous art, Summerfelt teaches:
wherein the dielectric material (#110) includes a polymer.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Summerfelt to the device disclosed by Chen, as parylene is a known dielectric material in the art and would be an obvious substitution of elements, to fill in the isolation trenches in order to electrically isolate one region for another and would be a modification according to known methods that yield a predictable results.
Regarding Claim 34, Chen in view of Summerfelt discloses: The integrated circuit of claim 25,
Chen further discloses:
further comprising interconnects (see annotated Fig. 12 below) coupled to the metallization stack (#24, #26), the metallization stack (#24, #26) being between the semiconductor substrate (#44A, #44B) and the interconnects (see annotated Fig. 12 below), wherein at least parts of the interconnects (see annotated Fig. 12 below) are exposed by the mold compound (specifically portion #60 of the interconnect structure, see annotated Fig. 12 below).
Note, from a top down perspective, portions of the underlying metallization stack are “between” the interconnect structure and the substrates.
PNG
media_image2.png
636
796
media_image2.png
Greyscale
Chen Fig. 12 – Annotated by Examiner
Claims 28-31 are rejected under 35 U.S.C. 103 as being obvious over US 2012/0038030 A1 Frey et al (herein “Frey”) in view of US 2020/0006309 A1 Chen et al.
Regarding Claim 28, Frey discloses:
A device (see Figs. 1-6, specifically see example embodiment shown in Fig. 6 of alternative structures of isolation trenches) including:
a semiconductor substrate (#10) including a first trench (#20E), a second trench (#20E), and a third trench (#20A) between the first (#20E) and second trenches (#20E), the third trench (#20A) being narrower than the first (#20E) and second trenches (#20E), the third trench (#20A) being filled with a dielectric material (#30),
at least one of the first trench (#20E) or the second trench (#20E) is partially filled by the dielectric material (#30),
and sidewalls of the first (#20E) and second trenches (#20E) are covered by the dielectric material (#30); and
Frey does not explicitly disclose:
a metallization stack overlapping the semiconductor substrate.
However, in analogous art, Chen teaches:
a metallization stack (Fig. 1, see dielectric layer #24, interconnect structure #26 comprising metal lines 28 and vias 30, which are formed in dielectric layers 32, herein referred to as #24, #26) overlapping the semiconductor substrate (#44A, #44B).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Chen to the device disclosed by Frey since Frey shows an incomplete device that doesn’t explicitly include a metallization stack, motivating those of ordinary skill to seek out teachings such as Chen to completely practice the invention of Frey. Additionally, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider utilizing the teachings of Fig. 6 and include 3 separate isolation trenches in the semiconductor substrate, two of them with the varying width shape #20E, and one with constant width shown in first embodiment in Figs. 1-3. Doing so would allow varying levels of electrical isolation per trench, as well as allow the deposition of a via into the trench after coating the walls of the trench with the dielectric material.
Regarding Claim 29, Frey in view of Chen discloses: The device of claim 28,
Frey further discloses:
wherein the metallization stack (#12, #14, #16) is exposed in the first (#20E) and second (#20E) trenches with the sidewalls covered by the dielectric material (sidewalls of trenches are covered by dielectric material #30, see Fig. 6).
Prior to deposition of the dielectric material, like the processing step shown in Fig. 1, the metallization stack is clearly exposed by the trench. Paragraph [0032] discloses “FIG. 6 shows examples of different geometries for which the method according to the present invention is suitable.” Additionally, in this case the metallization stack is being referenced as #12, #14, and #16 simply as a matter of convenience as previously indicated, due to the substitution of layers from Chen.
Regarding Claim 30, Frey in view of Chen discloses: The device of claim 28,
Frey further discloses:
The device of claim 28, wherein the semiconductor substrate (#10) has opposing first (top surface) and second (bottom surface) surfaces, the metallization stack (#12, #14, #16) overlaps with the first surface (top surface, from a top down view the metallization stack would overlap directly with the top surface), and the dielectric material (#30) extends from the third trench (#30A) onto and over the second surface (for purposes of examination, this will be interpreted as the first surface) and joining the dielectric material (#30) over the sidewalls of the first (#20E) and second (#20E) trenches.
Note, in this case the metallization stack is being referenced as #12, #14, and #16 simply as a matter of convenience as previously indicated, due to the substitution of layers from Chen.
Regarding Claim 31, Frey in view of Chen discloses: The device of claim 28,
Frey further discloses:
wherein the first trench or the second trench includes a conductive via formed therein (see Fig. 1, contact piston occupies space formed by trench #20A, electrically connects underlying electrically conductive connection 24 to metallic bond pad #28).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is (571)272-2686. The examiner can normally be reached M-F 8:00a-4:30p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights