DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Group I, Species 2, as shown in FIGs. 2A-3B, was elected.
Amendment filed May 28, 2025 is acknowledged. Claims 1, 4, 9 and 13-14 have been amended. Non-Elected Invention and Species, claims 13-19 have been withdrawn from consideration. Claims 1-19 are pending.
Action on merits of Elected Invention and Species, claims 1-12 follows.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 10 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites: “the method according to claim 9, further comprising: filling the second semiconductor layer with a fifth dielectric layer, wherein a top surface of the fifth dielectric layer is flush with a top surface of the second semiconductor layer; and sequentially forming a contact node and a capacitor on the source layer”.
First, claim 9 dependents on claim 1. According to claim 9, the “second semiconductor layer” remain the same as that of claim 1.
According to claim 1, claim 1, lines 3-4, recites: “providing a base, wherein the base comprises a substrate, a first semiconductor layer and a second semiconductor layer sequentially formed on one another;”
According to claims 1 and 9, there is nothing has been done to the “second semiconductor layer”.
The limitation “filling the second semiconductor layer with a fifth dielectric layer,” is itself contradictory because semiconductor layer and dielectric layer are completely different materials.
Moreover, how to fill the second semiconductor layer with a dielectric layer?
Claim 10 contravenes claim 1 (and 9). Therefore, claim 10 is indefinite.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by NISHIMURA et al. (US. Pub. No. 2015/0255510) of record.
With respect to claim 1, NISHIMURA teaches a method for forming a semiconductor structure, as claimed including:
providing a base, wherein the base comprises a substrate, a first semiconductor layer (20) and a second semiconductor layer (30) sequentially formed on one another;
forming a plurality of first isolation structures (72) spaced apart from each other and a plurality of second isolation structures (71a) spaced apart from each other in the base, wherein a source layer (31) formed in the second semiconductor layer (31) and a drain layer (11) formed in the substrate are provided between any two adjacent first isolation structures (72) of the plurality of first isolation structures (72), each of the plurality of first isolation structures (72) extends in a first direction (Y), each of the plurality of second isolation structures (71) extends in a second direction (X), the plurality of first isolation structures (72) penetrate through the first semiconductor layer (20) and the second semiconductor layer (30) and partially extend into the substrate, and the plurality of second isolation structures (71) are arranged in the substrate;
wherein each of the plurality of second isolation structures (71) comprises a first dielectric layer (71), each of the plurality of first isolation structures (72) comprises a second dielectric layer (72a) and a third dielectric layer (40);
forming a channel layer (20) in the first semiconductor layer (20), wherein a through hole (TR2a) extending in a same direction as the first direction (Y) is provided between the channel layer (20) and each of two first isolation structures (72) adjacent to the channel layer (20); and
forming a gate structure (50) in the through hole (TR2a). (See FIGs. 2A-9A).
With respect to claim 2, before forming the plurality of first isolation structures (72) spaced apart from each other of NISHIMURA and the plurality of second isolation structures (71) spaced apart from each other in the base, further comprises:
performing ion doping on the second semiconductor layer (30) and a portion of the substrate to form a drain doped area (10) in the substrate, and to form a source doped area (30) in the second semiconductor layer.
With respect to claim 3, forming the plurality of first isolation structures (72) of NISHIMURA spaced apart from each other and the plurality of second isolation structures (71) spaced apart from each other in the base comprises:
forming a plurality of initial first isolation structures (72) and a plurality of initial second isolation structures (71) in the base, wherein each of the plurality of initial first isolation structures (72) extends in the first direction (Y), and each of the plurality of initial second isolation structures (71) extends in the second direction (X), and wherein the plurality of initial first isolation structures (72) and the plurality of initial second isolation structures (71) penetrate through the first semiconductor layer (20) and the second semiconductor layer (30), and partially extend into the substrate to form the source layer (30) in the second semiconductor layer (30) and to form the drain layer (10) in the substrate; and
etching the plurality of initial first isolation structures (72) to form the plurality of first isolation structures (72a), and etching the plurality of initial second isolation structures (71) to form the plurality of second isolation structures (71).
With respect to claim 4, forming the plurality of initial first isolation structures and the plurality of initial second isolation structures in the base of NISHIMURA comprises:
forming a plurality of second isolation structure trenches (TR1) in the base, and filling the plurality of second isolation structure trenches (TR1) with the first dielectric layer (71) to form the plurality of initial second isolation structures (71); and
after forming the plurality of initial second isolation structures (71) in the base, forming a plurality of first isolation structure trenches (TR2) in the base, and filling the plurality of first isolation structure trenches (TR2) with the second dielectric layer (40) and the third dielectric layer (72) to form the plurality of initial first isolation structures, wherein the plurality of first isolation structure trenches (TR2) and the plurality of second isolation structure trenches (TR1) penetrate through the first semiconductor layer (20) and the second semiconductor layer (30), and partially extend into the substrate.
With respect to claim 9, forming the gate structure (50) in the through hole of NISHIMURA comprises:
forming a gate oxide layer (40) in the through hole through thermal oxidation; and
filling a surface of the gate oxide layer (40) with a conductive material (51) to form the gate structure (50).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over NISHIMURA ‘510 as applied to claim 4 above, and further in view of SURTHI et al. (US. Pub. No. 2019/0273080).
With respect to claim 5, NISHIMURA teaches the method as described in claim 4 above including: filling the plurality of first isolation structure trenches (TR2) with the second dielectric layer (40) and the third dielectric layer (72) to form the plurality of initial first isolation structures of comprises:
filling the plurality of first isolation structure trenches (TR2) with the second dielectric layer (40) and filing the plurality of first isolation structure trenches (TR2) with the third dielectric layer (72) to form the plurality of initial first isolation structures (72).
Thus NISHIMURA is shown to teach all the features of the claim with the exception of explicitly disclosing removing the second dielectric layer at a bottom portion of each of the plurality of first isolation structure trenches and on a surface of the second semiconductor layer.
However, SURTHI teaches a method for forming a semiconductor structure including:
filling plurality of first isolation structure trenches (12) with a second dielectric layer (18) and a third dielectric layer (44) to form a plurality of initial first isolation structures comprises:
filling the plurality of first isolation structure trenches (12) with the second dielectric layer (18) and filing the plurality of first isolation structure trenches (12) with the third dielectric layer (44) to form the plurality of initial first isolation structures (72);
removing the second dielectric layer (18) at a bottom portion of each of the plurality of first isolation structure trenches (12) and on a surface of second semiconductor layer (36); and filing the plurality of first isolation structure trenches (12) with the third dielectric layer (44) to form the plurality of initial first isolation structures. (Se FIGs. 2 and 6A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to the initial first isolation structures of NISHIMURA including removing the second dielectric layer at a bottom portion of each of the plurality of first isolation structure trenches and on a surface of the second semiconductor layer as taught by SURTHI so that the buried conductor can be easily formed.
With respect to claim 8, in view of SURTHI, the method, after removing the second dielectric layer (18) at the bottom portion of each of the plurality of first isolation structure trenches (12) and on the surface of the second semiconductor layer (36), and before filing the plurality of first isolation structure trenches (12) with the third dielectric layer (44), further comprises:
depositing metal cobalt (38) at the bottom portion of each of the plurality of first isolation structure trenches (12); and
performing an annealing treatment to form silicide (cobalt silicide) in the substrate to form a buried bit line, wherein the drain layer (32) is arranged between the channel layer (34) and the buried bit line, a height of a portion of each of the plurality of first isolation structures extending into the substrate is less than a height of a portion of each of the plurality of second isolation structures (71) arranged in the substrate, and the plurality of second isolation structures (71) penetrate through the buried bit line (L1).
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over NISHIMURA ‘510 as applied to claim 9 above, and further in view of LIN (US. Pub. No. 2011/0079836).
With respect to claim 10, As best understood by the Examiner, the method of NISHIMURA further comprises:
filling the second semiconductor layer (30) with a fifth dielectric layer (not shown, between gate 50 and L2-4); and sequentially forming a contact node and a capacitor on the source layer (30). (See FIGs. 1A, 10A, 13A, 18A).
Thus, NISHIMURA is shown to teach all the features of the claim with the exception of explicitly disclosing wherein a top surface of the fifth dielectric layer is flush with a top surface of the second semiconductor layer.
However, LIN teaches a method for forming a semiconductor structure including:
filling second semiconductor layer (62) with a fifth dielectric layer (24), wherein a top surface of the fifth dielectric layer (24) is flush with a top surface of the second semiconductor layer (62); and sequentially forming a contact node (84) and a capacitor (96) on the source layer (62). (See FIG. 15).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to fill the second semiconductor layer of NISHIMURA with the first dielectric layer that is flush with a top surface of the second semiconductor layer as taught by LIN to isolate the TFT from the capacitor.
With respect to claim 12, in view of LIN, a material of the gate oxide layer (30) comprises silicon oxide, and a material of the fifth dielectric layer (24) comprises silicon nitride.
Allowable Subject Matter
Claims 6-7 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
prior art of record, particularly, NISHIMURA ‘510, fails to teach the method for forming the semiconductor structure in the combination of the limitations as claimed including:
etching the second dielectric layer in the plurality of initial first isolation structures in the second semiconductor layer, and etching the first dielectric layer in the plurality of initial second isolation structures in the second semiconductor layer;
filling the plurality of etched initial first isolation structures in the second semiconductor layer with a fourth dielectric layer; and
etching the second dielectric layer in the plurality of initial first isolation structures in the first semiconductor layer, and etching the first dielectric layer in the plurality of initial second isolation structures in the first semiconductor layer to form the plurality of first isolation structures and the plurality of second isolation structures. (Claim 6).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
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/ANH D MAI/ Primary Examiner, Art Unit 2893
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