DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Group I, Species 2, as shown in FIGs. 2A-3B, was elected.
Amendment filed November 25,2025 is acknowledged. Claim 13 has been amended. Non-Elected Invention and Species, claims 13-19 have been withdrawn from consideration. Claims 1-19 are pending.
Action on merits of Elected Invention and Species, claims 1-12 follows.
Drawings
The drawings were received on November 25, 2025. These drawings are acceptable.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 10 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites: “the method according to claim 9, further comprising: filling the second semiconductor layer with a fifth dielectric layer, wherein a top surface of the fifth dielectric layer is flush with a top surface of the second semiconductor layer; and sequentially forming a contact node and a capacitor on the source layer”.
According to claim 1, the spaces between the “second semiconductor layer” 103/106 are filled with the first and second isolation structure, thus no “room” left for the “fifth dielectric layer”.
Claim 10 contravenes claim 1 (and 9). Therefore, claim 10 is indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 9-10 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by NISHIMURA et al. (US. Pub. No. 2015/0255510) of record.
With respect to claim 1, NISHIMURA teaches a method for forming a semiconductor structure, as claimed including:
providing a base, wherein the base comprises a substrate (L1), a first semiconductor layer (20) and a second semiconductor layer (30) sequentially formed on one another;
forming a plurality of first isolation structures (72) spaced apart from each other and a plurality of second isolation structures (71) spaced apart from each other in the base, wherein a source layer formed in the second semiconductor layer (30) and a drain layer formed in the substrate are provided between any two adjacent first isolation structures of the plurality of first isolation structures (72), each of the plurality of first isolation structures (72) extends in a first direction (Y), each of the plurality of second isolation structures (71) extends in a second direction (X), the plurality of first isolation structures (72) penetrate through the first semiconductor layer (20) and the second semiconductor layer (30) and partially extend into the substrate, and the plurality of second isolation structures (71) are arranged in the substrate;
forming a channel layer (20) in the first semiconductor layer, wherein a through hole (TR2a) extending in a same direction as the first direction (Y) is provided between the channel layer (20) and each of two first isolation structures (72) adjacent to the channel layer (20); and
forming a gate structure (50) in the through hole (TR2a). (See FIGs. 4C, 6A, 9A-B).
With respect to claim 2, before forming the plurality of first isolation structures (72) spaced apart from each other and the plurality of second isolation structures (71) spaced apart from each other in the base, further comprises:
performing ion doping on the second semiconductor layer (30) and a portion of the substrate to form a drain doped area (10) in the substrate, and to form a source doped area (30) in the second semiconductor layer.
With respect to claim 3, forming the plurality of first isolation structures (72) spaced apart from each other and the plurality of second isolation structures (71) spaced apart from each other in the base comprises:
forming a plurality of initial first isolation structures (72) and a plurality of initial second isolation structures (71) in the base, wherein each of the plurality of initial first isolation structures (72) extends in the first direction (Y), and each of the plurality of initial second isolation structures (71) extends in the second direction (X), and wherein the plurality of initial first isolation structures (72) and the plurality of initial second isolation structures (71) penetrate through the first semiconductor layer (20) and the second semiconductor layer (30), and partially extend into the substrate to form the source layer (30) in the second semiconductor layer and to form the drain layer (10) in the substrate; and
etching the plurality of initial first isolation structures (72) to form the plurality of first isolation structures (72a), and etching the plurality of initial second isolation structures (72) to form the plurality of second isolation structures (72a).
With respect to claim 9, forming the gate structure (50) in the through hole of NISHIMURA comprises:
forming a gate oxide layer (40) in the through hole through thermal oxidation; and
filling a surface of the gate oxide layer (40) with a conductive material to form the gate structure (50).
With respect to claim 10, As best understood by the Examiner, the method of NISHIMURA further comprises:
filling the second semiconductor layer with a fifth dielectric layer, wherein a top surface of the fifth dielectric layer is flush with a top surface of the second semiconductor layer; and sequentially forming a contact node and a capacitor on the source layer.
With respect to claim 12, a material of the gate oxide layer (40) of NISHIMURA comprises silicon oxide, and a material of the fifth dielectric layer comprises silicon nitride.
Allowable Subject Matter
Claims 4-8 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art of record fails to teach the method for forming a semiconductor structure in the combination of the limitations including:
after forming the plurality of initial second isolation structures in the base, forming a plurality of first isolation structure trenches in the base, and filling the plurality of first isolation structure trenches with a second dielectric layer and a third dielectric layer to form the plurality of initial first isolation structures, … (Claim 4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANH D MAI/ Primary Examiner, Art Unit 2893