Prosecution Insights
Last updated: April 19, 2026
Application No. 17/829,446

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Non-Final OA §102§112
Filed
Jun 01, 2022
Examiner
LI, MEIYA
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
69%
Grant Probability
Favorable
1-2
OA Rounds
3y 8m
To Grant
95%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allow Rate
628 granted / 912 resolved
+0.9% vs TC avg
Strong +26% interview lift
Without
With
+26.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
52 currently pending
Career history
964
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
34.3%
-5.7% vs TC avg
§102
26.5%
-13.5% vs TC avg
§112
36.0%
-4.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 912 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of invention I, species I(a), claims 1-11 and 13-17, in the reply filed on March 6, 2025 is acknowledged. Claims 12 and 18-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 6, 2025. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statements (IDS) submitted on June 1, 2022, December 30, 2022 and May 12, 2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-11 and 13-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There appears to be no adequate description in the specification for the claim limitation of "a first contact on the first pad and adjacent to the bit line in the first direction; an insulating separation pattern on the word line and adjacent to the first contact in the second direction, wherein: the first contact includes: a barrier pattern on the first pad, and a conductive pattern vertically extending from the barrier pattern, and a side surface of the conductive pattern of the first contact is in direct contact with the insulating separation pattern", as recited in claim 1; “the bit line spacer is in direct contact with the conductive pattern of the first contact”, as recited in claim 2; “the fourth spacer is in contact with the barrier pattern of the first contact and vertically extends along the side surface of the conductive pattern of the first contact”, as recited in claim 3; “a second contact on a center portion of the active portion and connected to the bit line, wherein the second contact is spaced apart from the first pad in the first direction”, as recited in claim 8; “a contact insulating structure between the second contact and the device isolation pattern; and a gapfill insulating structure between the second contact and the first pad, wherein: the second contact includes: a first portion, which has an increasing width with increasing distance from the substrate, and a second portion on the first portion, the second portion having a decreasing width with increasing distance from the substrate, the first portion of the second contact is enclosed by the contact insulating structure, and the second portion of the second contact is enclosed by the gapfill insulating structure”, as recited in claim 9; “a bottom surface of the insulating separation pattern is at a level lower than a bottom surface of the first contact”; as recited in claim 10; “the insulating separation pattern includes a protruding portion protruding toward the first contact, and the protruding portion is in contact with the barrier pattern of the first contact”, as recited in claim 11; “an ohmic contact layer between the first pad and the first contact”, as recited in claim 13; “a side surface of the conductive pattern of the second contact is in direct contact with the insulating separation pattern and the fourth spacer of the bit line spacer”, as recited in claim 14; “the fourth spacer is in contact with the barrier pattern of the first contact and vertically extends along a side surface of the conductive pattern of the first contact”, as recited in claim 15 (note: Figs. 1B, 1C, 8A, 10, 15A-15C and corresponding paragraphs disclose that a second contact on the first pad and adjacent to the bit line in the first direction; a first contact on a center portion of the active portion and connected to the bit line; the first portion of the first contact is surrounded (not enclosed) by the contact insulating structure, and the second portion of the first contact is surrounded (not enclosed) by the gapfill insulating structure; a first side surface of the second contact is in direct contact with the bit line spacer; and a second side surface of the second contact is in direct contact with the second insulating separation pattern). The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-11 and 13-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claimed limitation of "a word line … extending in a first direction", as recited in claims 1 and 14, is unclear as to which dimension of a wordline extending in a first direction applicant refers. The claimed limitation of "a bit line … extending in a second direction …", as recited in claims 1 and 14, is unclear as to which dimension of a bit line extending in a second direction applicant refers. The claimed limitation of “a first contact on the first pad and adjacent to the bit line in the first direction; an insulating separation pattern on the word line and adjacent to the first contact in the second direction, wherein: the first contact includes: a barrier pattern on the first pad, and a conductive pattern vertically extending from the barrier pattern, and a side surface of the conductive pattern of the first contact is in direct contact with the insulating separation pattern”, as recited in claim 1, which indefinite and renders the claim uncertain because said limitation is inconsistent with the specification disclosure: i.e. [0030], [0045], [0049]. See MPEP §2173.03. The claimed limitation of “the bit line spacer is in direct contact with the conductive pattern of the first contact”, as recited in claim 2, which indefinite and renders the claim uncertain because said limitation is inconsistent with the specification disclosure: i.e. [0047]. See MPEP §2173.03. The claimed limitation of “the fourth spacer is in contact with the barrier pattern of the first contact and vertically extends along the side surface of the conductive pattern of the first contact”, as recited in claim 3, which indefinite and renders the claim uncertain because said limitation is inconsistent with the specification disclosure: i.e. [0047]. See MPEP §2173.03. The claimed limitation of “a second contact on a center portion of the active portion and connected to the bit line, wherein the second contact is spaced apart from the first pad in the first direction”, as recited in claim 8, which indefinite and renders the claim uncertain because said limitation is inconsistent with the specification disclosure: i.e. [0034]. See MPEP §2173.03. The claimed limitation of “a contact insulating structure between the second contact and the device isolation pattern; and a gapfill insulating structure between the second contact and the first pad, wherein: the second contact includes: a first portion, which has an increasing width with increasing distance from the substrate, and a second portion on the first portion, the second portion having a decreasing width with increasing distance from the substrate, the first portion of the second contact is enclosed by the contact insulating structure, and the second portion of the second contact is enclosed by the gapfill insulating structure”, as recited in claim 9, which indefinite and renders the claim uncertain because said limitation is inconsistent with the specification disclosure: i.e. [0031]-[0032]. See MPEP §2173.03. The claimed limitation of “a bottom surface of the insulating separation pattern is at a level lower than a bottom surface of the first contact”; as recited in claim 10, which indefinite and renders the claim uncertain because said limitation is inconsistent with the specification disclosure: i.e. [0052]. See MPEP §2173.03. The claimed limitation of “the insulating separation pattern includes a protruding portion protruding toward the first contact, and the protruding portion is in contact with the barrier pattern of the first contact”, as recited in claim 11, which indefinite and renders the claim uncertain because said limitation is inconsistent with the specification disclosure: i.e. [0060]. See MPEP §2173.03. The claimed limitation of “an ohmic contact layer between the first pad and the first contact”, as recited in claim 13, which indefinite and renders the claim uncertain because said limitation is inconsistent with the specification disclosure: i.e. [0035]. See MPEP §2173.03. The claimed limitation of “a side surface of the conductive pattern of the second contact is in direct contact with the insulating separation pattern and the fourth spacer of the bit line spacer”, as recited in claim 14, which indefinite and renders the claim uncertain because said limitation is inconsistent with the specification disclosure: i.e. [0047]. See MPEP §2173.03. The claimed limitation of “the fourth spacer is in contact with the barrier pattern of the first contact and vertically extends along a side surface of the conductive pattern of the first contact”, as recited in claim 15, which indefinite and renders the claim uncertain because said limitation is inconsistent with the specification disclosure: i.e. [0049]. See MPEP §2173.03. Claim 15 recites the limitation "the barrier pattern of the first contact" in line 4. There is insufficient antecedent basis for this limitation in the claim. Claim 15 recites the limitation "the conductive pattern of the first contact" in line 5. There is insufficient antecedent basis for this limitation in the claim. The claimed limitation of "the first", as recited in claim 16, is unclear as to the first of which element applicant refers. The claimed limitation of "fourth spacers", as recited in claim 16, is unclear as to whether said limitation is the same as or different from "a fourth spacer", as recited in claim 14. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 8 and 13, as best understood, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (2015/0061134). As for claim 1, Lee et al. show in Figs. 1A-1E and related text a semiconductor device, comprising: a substrate 100 including an active portion ACT defined by a device isolation pattern 102; a word line WL in the substrate, the word line crossing the active portion and extending in a first direction D2; a bit line BL crossing the active portion and the word line and extending in a second direction D3 intersecting the first direction; a first pad XP on an end portion of the active portion; a first contact 11a/13a on the first pad and adjacent to the bit line in the first direction; and an insulating separation pattern 173 on the word line and adjacent to the first contact in the second direction, wherein: the first contact includes: a barrier pattern 11a on the first pad, and a conductive pattern 13a vertically extending from the barrier pattern, and a side surface of the conductive pattern of the first contact is in direct contact with the insulating separation pattern. As for claim 8, Lee et al. show a second contact DC on a center portion of the active portion and connected to the bit line, wherein the second contact is spaced apart from the first pad in the first direction (Fig. 1B). As for claim 13, Lee et al. show an ohmic contact layer 9 between the first pad and the first contact, wherein the ohmic contact layer includes a metal silicide (Fig. 1B; [0087]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LYNNE GURLEY can be reached at (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MEIYA LI/Primary Examiner, Art Unit 2811
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Prosecution Timeline

Jun 01, 2022
Application Filed
Aug 29, 2025
Non-Final Rejection — §102, §112
Oct 28, 2025
Interview Requested
Nov 05, 2025
Applicant Interview (Telephonic)
Nov 05, 2025
Examiner Interview Summary
Dec 02, 2025
Response Filed
Dec 02, 2025
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
69%
Grant Probability
95%
With Interview (+26.0%)
3y 8m
Median Time to Grant
Low
PTA Risk
Based on 912 resolved cases by this examiner. Grant probability derived from career allow rate.

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