Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 3/3/2026.
Claims 1, 3-6, 8-17, and 20-24 are currently pending.
Claims 6 and 17 have been amended.
Claims 2, 7, and 18-19 have been canceled.
Claims 23 and 24 are new.
Claims 1, 3-6, 8-17, and 20-24 have been examined.
Response to Arguments
Applicant's arguments filed 12/12/2025 have been fully considered but they are not persuasive.
The Applicant’s argues that the combination of Morris, Chang, and Kobayashi for claim 1 is improper because there is no motivation to combine the references. In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Motivation to combine Morris and Chang is provided on page 8 of the office action that the gate length is longer for the device providing a longer effective channel length in a modified device. Motivation for a person of ordinary skill in the art to further combine Kobayashi with the device of Morris as modified by Chang is provided on page 8 of the office action dated 12/12/2025, specifically that Kobayashi that Kobayashi has improved on-resistance/channel resistance than conventional channel devices (Kobayashi, translation page 3/7, [0023]) due to the gate electrodes being kept at a fixed width from the edge of the silicon substrate (Kobayashi, translation page 3/7, [0019]).
In response to applicant's argument that the bodily incorporation of Chang into Morris specifically would result in a situation where feature A is no longer present in the combination (Remarks 3/3/2026, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning (Remarks 3/3/2026, page 10), it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
The rejection provides a mapping of the claim 1 starting on page 7, to say which is elongated structure (Morris, Fig. 2, sub-fin 216 formed from fin 202.) and that the fin is aligned with one or more edges of the die (Morris, Fig. 2, sub-fin 216 is aligned with the x-axis). The combination of Morris and Chang which starts in the office action at page 8 teaches that the gate would be oriented related to the elongated structure and by necessity also the edge of the die because the elongated structure of the device of Morris is already described in relationship with the edge of the of the die (Chang, Fig. 2A, angle of the fin 205 relative to the gate 203). Chang also teaches that the gate orientation would be an angle between 10 degrees and 80 degrees (Chang, [0021], the angle of each gate is between 50 and 70 degrees.) Accordingly, the rejection to claim 1 is maintained. As stated above, the motivation for the combination is provided on page 8.
Claim 6 has been amended to incorporate previously rejected dependent claim 7 and applicant has not provided reasons for why this would overcome the previous rejection. Claim 17 has been amended to incorporated previously rejected dependent claim 19 and applicant has not provided reasons for why this would overcome the previous rejection. Accordingly, the rejections to claim 6 and 17 are maintained.
The rejection from 12/12/2025 is maintained.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 6, 8-9, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Morris et al. US 20200091162 A1 (hereinafter Morris) in view Kobayashi et al. JP 2004146626 A (Google translation provided and hereinafter Kobayashi).
Regarding claim 6, Morris discloses:
An integrated circuit (IC) device (Morris, Fig. 3, memory array 300 which includes the transistor of Fig. 2), comprising:
a support structure; ([0067] the device is on a substrate)
a first elongated structure (fin 202-1) and a second elongated structure (fin 202-2) over the support structure, wherein longitudinal axis (Morris, Fig. 2, Y-axis) of the first elongated structure (gate structure 212 of the memory cell 100-1) is aligned with (one or more edges of the support structure, and (the gate structure is parallel to the y-axis) a longitudinal axis (Fig. 2, Y-axis) of the second elongated structure (gate structure 212 of the memory cell 100-1) is parallel to the longitudinal axis of the first elongated structure. (the gate structure is parallel to the y-axis)
a plurality of transistors (memory cells 100-1 to 100-5), each transistor comprising a gate ([0065], each finFET 110 includes gate electrode 212a as described in Fig.2) over or at least partially wrapping around a channel region (channel portion 218), wherein the plurality of transistors includes a first transistor (Fig. 3, memory cell 100-1) and a second transistor (Fig. 3, memory cell 100-2), and wherein the channel region of the first transistor includes a semiconductor material (channel 218, [0053] formed of monocrystalline semiconductors) of the first elongated structure (Fig. 3 is a plan view utilizing the memory cell structure defined in Fig. 2, Fig. 2 channel structure 216 is an elongated material made of semiconductor material which includes the channel 218) and the channel region of the second transistor includes a semiconductor material (channel material 218, [0053] formed of monocrystalline semiconductors) of the second elongated structure; and (Fig. 3 is a plan view utilizing the memory cell structure defined in Fig. 2, Fig. 2 channel structure 216 is an elongated material made of semiconductor material)
a gate line (WL 150-1 which forms gate electrode 212, [0065]) having a first portion that forms, or is in electrically conductive contact with, the gate of the first transistor ([0074], WL 150-1 being coupled to, or forming, a gate electrode 212 of the FinFET 110) and having a second portion that forms, or is in electrically conductive contact with, the gate of the second transistor, ([0065], WL 150-2 being coupled to, or forming, a gate electrode 212 of the FinFET 110)
Morris does not appear to teach:
wherein a projection of the gate line onto a plane of the support structure is at an angle between 10 degrees and 80 degrees with respect to one or more edges of the support structure
Kobayashi, which teaches a power MOSFET or IGBT (Kobayashi, Description [0001]), discloses:
wherein the projection of the gate (Fig.1 gate 8) onto the plane of the die is at an angle between 10 degrees and 80 degrees with respect to one or more edges of the die. ([0025], the gate electrode 8 is formed at an angle of 450 with respect to one end 5 of the silicon substrate 3 (i.e. die), See also Fig. 1.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Morris and Chang to have the projection of the gate onto the plane of the die is at an angle between 10 degrees and 80 degrees with respect to one or more edges of the die as taught by Kobayashi for purposes of having lower on-resistance compared to conventional MOSFET. (Kobayashi, [0023].)
Regarding claim 8, Morris and Kobayashi disclose all the elements of claim 6.
Morris further discloses:
each transistor of the plurality of transistors includes further includes a first region and a second region (Fig. 2, [0054] the fin 202 has a source region and drain region on either side of the gate stack 210), wherein one of the first region and the second region is a source region and another one of the first region and the second region is a drain region, and ([0054])
the IC device further includes a contact line having a first portion that forms, or is in electrically conductive contact with, the second region of the first transistor (source/drain terminal 220) and having a second portion that forms, or is in electrically conductive contact with, the second region of the second transistor (source/drain terminal 220), wherein a projection of the contact line onto the plane of the support structure is substantially parallel to the projection of the gate line onto the plane of the support structure. (Fig. 2, 220 is substantially parallel to 212)
Regarding claim 9, Morris and Kobayashi disclose all the elements of claim 6.
Morris further discloses:
the plurality of transistors further includes a third transistor (Fig. 3, memory cell 100-3) and a fourth transistor (Fig. 3, memory cell 100-4), the channel region (Fig. 2,channel portion, 218) of the third transistor includes the semiconductor material (channel material 218, [0053] formed of monocrystalline semiconductors) of the first elongated structure (Fig. 3 is a plan view utilizing the memory cell structure defined in Fig. 2, Fig. 2 the channel structure 216 is an elongated material made of semiconductor material) and the channel region(Fig. 2,channel portion, 218) of the fourth transistor includes the semiconductor material (channel material 218, [0053] formed of monocrystalline semiconductors) of the second elongated structure, (Fig. 3 is a plan view utilizing the memory cell structure defined in Fig. 2, Fig. 2 channel structure 216 is an elongated material made of semiconductor material) the gate line is a first gate line, and ([0074], WL 150-1 being coupled to, or forming, a gate electrode 212 of the FinFET 110)
the IC device further includes a second gate line (WL 150-2 being coupled to, or forming, a gate electrode 212 of the FinFET 110) having a first portion that forms, or is in electrically conductive contact with, the gate of the third transistor (WL 150-3 is electrically in contact with WL 150-2) and having a second portion that forms, or is in electrically conductive contact with, the gate of the fourth transistor (WL 150-4), wherein a projection of the second gate line onto the plane of the support structure is substantially parallel to the projection of the first gate line onto the plane of the support structure. (WL 150-2 is parallel to WL 150-1)
Regarding claim 14, Morris and Kobayashi disclose all the elements of claim 6.
Morris further discloses:
the semiconductor material of the first elongated structure that is in the channel region of the first transistor is a P-type semiconductor material, and ([0053], the channel material can be P-type)
the semiconductor material of the second elongated structure that is in the channel region of the second transistor is an N-type semiconductor material. ([0053], the channel material can be N-type)
Regarding claim 15, Morris and Kobayashi disclose all the elements of claim 6.
Morris further discloses:
a metallization stack (interconnects 2258) comprising lines that includes one or more electrically conductive materials ([0129] the contacts are made of electrically conductive material), the lines being in electrical contact with various terminals of the plurality of transistors, wherein projections of the lines onto the plane of the support structure are aligned with one or more edges of the support structure. (Fig. 16)
Regarding claim 16, Morris and Kobayashi disclose all the elements of claim 6.
Morris further discloses:
the first elongated structure is a first fin or a first nanoribbon, and ([0078], base 202 is a nanoribbon.)
the second elongated structure is a second fin or a second nanoribbon. ([0078], base 202 is a nanoribbon.)
Claims 1, 3-5, 17, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Morris and Chang et al. US 20190172832 A1 (hereinafter Chang) in view Kobayashi.
Regarding claim 1, Morris discloses:
An integrated circuit (IC) device (Morris, Fig. 2, transistor 110), comprising:
a die; (Fig. 14A, [0105], top view of a wafer includes dies 2002 which include one or more transistors 110.)
an elongated structure over the die (Fig. 2, sub-fin 216 which is formed from fin 202), the elongated structure comprising a semiconductor material ([0053], the sub-fin 216 may be a semiconductor material) and having a longitudinal axis aligned with one or more edges of the die (Fig. 2, the sub-fin 216 is aligned with x-axis);
and a transistor comprising a gate (Fig. 2, transistor 110 which has a gate 212), wherein a part of the semiconductor material of the elongated structure is a channel region (channel portion 218, [0050], the channel portion 218 is at the end of the sub-fin 216) of the transistor.
Morris does not appear to teach:
wherein an angle between a projection of the gate onto a plane of the die and a projection of the longitudinal axis of the elongated structure onto the plane of the die is between 10 degrees and 80 degrees.
Chang, which teaches a method of forming an finFET SRAM and related device (Chang, Abstract), discloses:
wherein an angle (Fig. 2A, angle of the fin 205 relative to the gate 203) between a projection of the gate onto a plane of the die and a projection of the longitudinal axis of the elongated structure onto the plane of the die is between 10 degrees and 80 degrees. ([0021], the angle of each is between 50 and 70 degrees.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Morris to have wherein an angle between a projection of the gate onto a plane of the die and a projection of the longitudinal axis of the elongated structure onto the plane of the die is between 10 degrees and 80 degrees as taught by Chang for purposes of have a longer effective channel length. (Chang, [0022].)
Neither Morris or Chang appear to disclose:
wherein the projection of the gate onto the plane of the die is at an angle between 10 degrees and 80 degrees with respect to one or more edges of the die.
Kobayashi, which teaches a power MOSFET or IGBT (Kobayashi, Description [0001]), discloses:
wherein the projection of the gate (Fig.1 gate 8) onto the plane of the die is at an angle between 10 degrees and 80 degrees with respect to one or more edges of the die. ([0025], the gate electrode 8 is formed at an angle of 450 with respect to one end 5 of the silicon substrate 3 (i.e. die), See also Fig. 1.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Morris and Chang to have the projection of the gate onto the plane of the die is at an angle between 10 degrees and 80 degrees with respect to one or more edges of the die as taught by Kobayashi for purposes of having lower on-resistance compared to conventional MOSFET. (Kobayashi, [0023].)
Regarding claim 3, Morris, Chang, and Kobayashi disclose all the elements of claim 1.
Morris further discloses:
the transistor (Fig. 2, transistor 110) further includes a first region and a second region, wherein one of the first region and the second region is a source region and another one of the first region and the second region is a drain region, ([0054], the fin 202 may include a source region and drain region) the IC device further includes a first contact and a second contact, the first contact being an electrical contact to the first region and the second contact being an electrical contact to the second region, and ([0054], source/drain terminal on the source drain region)
Chang further discloses:
an angle (Fig. 2A, [0021] a diagonal finFET plot/layout showing in a plane view the angle of the fin 205 relative to the gate 203) between a projection of the first contact (PD device 215 has a gate 203) onto the plane of the die and the projection of the longitudinal axis of the elongated structure (fin 205) onto the plane of the die is between 10 degrees and 80 degrees. ([0021], the angle of each is between 50 and 70 degrees.)
Regarding claim 4, Morris, Chang, and Kobayashi disclose all the elements of claim 3.
Change further discloses:
an angle (Fig. 2A, angle of the fin 205 relative to the gate 203) between a projection of the second contact (PU device 217 has a gate 203) onto the plane of the die and the projection of the longitudinal axis of the elongated structure (fin 205) onto the plane of the die is between 10 degrees and 80 degrees. ([0021], the angle of each is between 50 and 70 degrees.)
Regarding claim 5, Morris, Chang, and Kobayashi disclose all the elements of claim 1.
Morris further discloses:
wherein the elongated structure is a fin (sub-fin 216) or a nanoribbon. ([0078], base 202 is a nanoribbon.)
Regarding claim 17, Morris discloses:
An integrated circuit (IC) device, (Morris, Fig. 3, memory array 300, which includes the device design of the access transistor 110 in Fig. 2), comprising:
a substrate; ([0067] the device is on a substrate)
a plurality of elongated structures (sub-fin 216) over the substrate, the elongated structures comprising fins or nanoribbons; (Fig. 2, fins 202-1 to 202-5)
a logic circuitry comprising a plurality of transistors (memory cells 100-1 to 100-5), each transistor having a channel region (channel portion 218) that includes a portion of one or more semiconductor materials of one of the elongated structures; (channel material 218, [0053] formed of monocrystalline semiconductors)
and a plurality of gate lines, (WL 150-1 to 150-5) each gate line forming, or electrically coupled to, gates of one or more of the plurality of transistors, (Fig. 3)
Morris does not appear to teach:
wherein a projection of the gate line onto a plane of the support structure is at an angle between 10 degrees and 80 degrees with respect to one or more edges of the support structure
Chang, which teaches a method of forming and finFET SRAM and related device (Chang, Abstract), discloses:
wherein a projection of the gate line onto a plane of the support structure is at an angle (Fig. 2A, angle of the fin 205 relative to the gate 203) between 10 degrees and 80 degrees with respect to one or more edges of the support structure ([0021], the angle of each is between 50 and 70 degrees.) the projections of the elongated structures (gate structures 212 of the memory cells 100) onto the plane of the substrate are parallel with respect to one or more edges of the substrate. (the gate structure is parallel to the Y-axis in Fig. 2)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Morris to have wherein an angle between a projection of the gate onto a plane of the die and a projection of the longitudinal axis of the elongated structure onto the plane of the die is between 10 degrees and 80 degrees as taught by Chang for purposes of have a longer effective channel length. (Chang, [0022].)
Neither Morris or Chang appear to disclose:
wherein the projection of the gate onto the plane of the die is at an angle between 10 degrees and 80 degrees with respect to one or more edges of the die.
Kobayashi, which teaches a power MOSFET or IGBT (Kobayashi, Description [0001]), discloses:
wherein the projection of the gate (Fig.1 gate 8) onto the plane of the die is at an angle between 10 degrees and 80 degrees with respect to one or more edges of the die. ([0025], the gate electrode 8 is formed at an angle of 450 with respect to one end 5 of the silicon substrate 3, See also Fig. 1.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Morris and Chang to have the projection of the gate onto the plane of the die is at an angle between 10 degrees and 80 degrees with respect to one or more edges of the die as taught by Kobayashi for purposes of having lower on-resistance compared to conventional MOSFET. (Kobayashi, [0023].)
Regarding claim 21, Morris, Chang and Kobayashi discloses all of claim 1.
Morris further discloses:
herein the projection of the longitudinal axis of the elongated structure (fin 202) onto the plane of the die is at an angle of either 0 degrees or 90 degrees with respect to the one or more edges of the die. (Fig. 3 and [0067], fins 202 are parallel to the substrate.)
Regarding claim 22, Morris, Chang and Kobayashi discloses all of claim 3.
Kobayashi further discloses:
the projection of the first contact (source electrode 13 which goes over source contact openings 12, See Fig. 1) onto the plane of the die is at an angle between 10 degrees and 80 degrees with respect to the one or more edges of the die. ([0017] the source is formed such that it is at a 45o with respect to one end 5 of the silicon substrate 3 (i.e. die).)
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Morris as modified by Kobayashi as applied to claim 9 above, and further in view of John P. Uyemura, “CMOS Logic Circuit Design” (2002) (hereinafter Uyemura).
Regarding claim 10, Morris and Kobayashi disclose all the elements of claim 9.
Morris further discloses:
further comprising a two-legged inverter circuit, ([0105], the embodiments (shown in Fig. 2 and Fig. 3) may be implemented or include a logic device or SRAM, it is known in the art that an SRAM cell core is two cross coupled inverters) the two-legged inverter circuit including the first transistor, the second transistor, the third transistor, and the fourth transistor.
While Morris does not explicitly disclose the inverter design such two-legged inverter circuit, Uyemura shows that such an inverter design that has a complementary pair of transistors for the input was known in the art. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Morris as modified by Chang to have the first transistor, the second transistor, the third transistor, and the fourth transistor for a two-legged (i.e. two input) inverter device as taught by Uyemura for purposes of having a two-legged inverter circuit. (Uyemura page 103) and as shown by the standard inverter design in Chang in Fig. 2B used in a SRAM cell.
Regarding claim 11, Morris and Kobayashi disclose all the elements of claim 9.
Morris further discloses:
further comprising a buffer circuit, ([0105], the embodiments (shown in Fig. 2 and Fig. 3) may be implemented or include a logic device or suitable circuit element) the buffer circuit including the first transistor, the second transistor, the third transistor, and the fourth transistor.
While Morris does not explicitly disclose the inverter design such two buffer circuit including four transistors Uyemura shows that such an a non-inverting buffer would consist of two cascaded inverters (Uyemura, third paragraph on page 389) was known in the art. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Morris as modified by Chang to have the first transistor, the second transistor, the third transistor, and the fourth transistors taught by Uyemura for purposes of having a buffer circuit which consists of two cascaded inverters (a single inverter in a CMOS configuration consisting of a two transistors). (Uyemura page 389.)
Regarding claim 12, Morris and Kobayashi disclose all the elements of claim 9.
Morris further discloses:
further comprising a two-input NAND circuit, ([0105], the embodiments (shown in Fig. 2 and Fig. 3) may be implemented or include a logic device such as NAND device) the two-input NAND circuit including the first transistor, the second transistor, the third transistor, and the fourth transistor.
While Morris does not explicitly disclose the inverter design such two-input NAND circuit including four transistors Uyemura shows that such a NAND design (Uyemura, 5.2.4, N-input NAND, page 205, “N-input NAND would have N complementary pairs. Therefore a 2 input NAND would consist of 4 transistor in 2 complementary pairs of NMOS and PMOS.) was known in the art. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Morris as modified by Chang to have the first transistor, the second transistor, the third transistor, and the fourth transistor as taught by Uyemura for purposes of having a two-input NAND circuit. (Uyemura 5.2 CMOS NAND page 195-206 and at Fig. 5.5.)
Regarding claim 13, Morris and Kobayashi disclose all the elements of claim 9.
Morris further discloses:
further comprising a two-input NOR circuit, ([0105], the embodiments (shown in Fig. 2 and Fig. 3) may be implemented or include a logic device such as NOR device) the two-input NOR circuit including the first transistor, the second transistor, the third transistor, and the fourth transistor.
While Morris does not explicitly disclose the inverter design such two-input NOR circuit including four transistors Uyemura shows that such an inverter design (Uyemura, 5.3.4 N-Input NOR, page 213, “N-input NOR gate can be constructed by using complementary structuring with N nFETS and N pFETs in series. Therefore a two input NOR circuit would have four transistors 2 nFETs and 2 pFETs.) was known in the art. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Morris as modified by Chang to have the first transistor, the second transistor, the third transistor, and the fourth transistor as taught by Uyemura for purposes of having a two-input NOR circuit. (Uyemura 5.3 CMOS NOR page 206-213 and at Fig. 5.16)
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Morris as modified by Chang and Kobayashi as applied to claim 17 above, and further in view of John P. Uyemura, “CMOS Logic Circuit Design” (2002) (hereinafter Uyemura).
Regarding claim 20, Morris, Chang, and Kobayashi disclose all of claim 17.
Morris further discloses:
wherein the logic circuitry includes one or more of a two-legged inverter circuitry, a buffer circuitry, a two-input NAND circuitry, and a two-input NOR circuitry. ([0105], “In some embodiments, the wafer 2000 or the die 2002 may implement or include a memory device (e.g., a SRAM device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element,” i.e. logic circuity can be NAND, NOR, inverter and buffer circuits as specified.)
While Morris does not explicitly disclose the inverter design such two-input NAND circuit including four transistors Uyemura shows that such a NAND design (Uyemura, 5.2.4, N-input NAND, page 205, “N-input NAND would have N complementary pairs. Therefore a 2 input NAND would consist of 4 transistor in 2 complementary pairs of NMOS and PMOS.) was known in the art. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Morris as modified by Chang to have logic circuity to include a two-input NAND Uyemura for purposes of having a two-input NAND circuit. (Uyemura 5.2 CMOS NAND page 195-206 and at Fig. 5.5.)
Claims 23 and 24 is rejected under 35 U.S.C. 103 as being unpatentable over Morris as modified by Kobayashi as applied to claim6 above, and further in view of Kim et al. US 20110111568 A1 (hereinafter Kim).
The following annotated figure will be used in discussion:
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Regarding claim 23, Morris and Kobayashi disclose all the elements of claim 6.
Morris and Kobayashi do not appear to disclose “a projection of the longitudinal axis of the first elongated structure onto a plane of the support structure is at an angle of either 0 degrees or 90 degrees with respect to the one or more edges of the support structure.”
However, Kim which teaches, a transistor with vertical channels which also word lines at an angle related to the vertical channel (Kim, Abstract and [0051]), discloses:
a projection (Fig. 8A, a plan view of a memory device of Fig. 1) of the longitudinal axis (Fig. 1A, C direction) of the first elongated structure (annotated Fig. 8A, vertical channel 112a) onto a plane of the support structure (substrate 100) is at an angle of either 0 degrees or 90 degrees ([0051] the C direction is perpendicular to the Y direction) with respect to the one or more edges of the support structure. ([0053], the vertical channel 112 extends in the C direction therefore is 0 degrees with respect to the support structure, see also Fig. 8A)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Morris and Kobayashi to have a projection of the longitudinal axis of the first elongated structure onto a plane of the support structure is at an angle of either 0 degrees or 90 degrees with respect to the one or more edges of the support structure as taught by Kim for purposes of improve integration of horizontal channel structures. (Kim, [0005].)
Regarding claim 24, Morris and Kobayashi disclose all the elements of claim 23.
Morris and Kobayashi do not appear to disclose “a projection of the longitudinal axis of the first elongated structure onto a plane of the support structure is at an angle of either 0 degrees or 90 degrees with respect to the one or more edges of the support structure.”
However, Kim which teaches, a transistor with vertical channels which also word lines at an angle related to the vertical channel (Kim, Abstract and [0051]), discloses:
a projection (Fig. 8A, a plan view of a memory device of Fig. 1) of the longitudinal axis (Fig. 1A, C direction) of the second elongated structure (annotated Fig. 8A, vertical channel 112b) onto a plane of the support structure (substrate 100) is at an angle of either 0 degrees or 90 degrees ([0051] the C direction is perpendicular to the Y direction) with respect to the one or more edges of the support structure. ([0053], the vertical channel 112 extends in the C direction therefore is 0 degrees with respect to the support structure, see also Fig. 8A)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Morris and Kobayashi to have a projection of the longitudinal axis of the first elongated structure onto a plane of the support structure is at an angle of either 0 degrees or 90 degrees with respect to the one or more edges of the support structure as taught by Kim for purposes of improve integration of horizontal channel structures. (Kim, [0005].)
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kamo US 20140008728 A1 – Shows the projection the first contact being either 60 or 120 degrees with respect to the die edge.
Laforet et al US 20210367045 A1 – The projection of the gate being at different angles which are between 10 and 90 degrees.
Yang et al. US 20220059414 A1 – The projection of the channel (e.g. elongated structures) being 90 degrees from a top channel and bottom channel.
Burnett et al. US 7414877 B2 – Fig 5. Conductive member 5476 has a bend angle of 22.5 degrees.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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