DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on December 22th, 2025, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant's response filed on December 22th, 2025 is acknowledged and isanswered as follows.
Applicant's arguments, see pgs. 7-8, with respect to the rejections of claims under 35 U.S.C 103(a) have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 5, 9-10, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (Pub. No.: US 2018/0114776 A1), hereinafter as Han in view of MAO (Pub. No.: US 2019/0035705 A1).
Regarding claim 1, Han discloses a semiconductor device in Fig. 1, comprising: a substrate (substrate 300) having a first main surface (upper surface) and an opposing second main surface (lower surface) (see [0020]); a vertical stack of semiconductor dies (stack of chips 110, 120, 130 and 140) attached to the first main surface, the semiconductor dies being horizontally offset with respect to one another, the vertical stack having first (the stepped surface of the stack having no wiring) and second (the
PNG
media_image1.png
438
879
media_image1.png
Greyscale
stepped surface of the stack having wirings 420) stepped surfaces (see Fig. 1 and [0019-0020]), the first stepped surface overhanging a first area (the area of the upper surface of substrate 300 below the first stepped surface of the stack chips 110/120/130/140) of the first main surface of the substrate (see annotated Fig. 1 above and [0021]); a plurality of first bond wires (plurality of wires 420 and 410) electrically connecting the semiconductor dies one to another and to the first main surface of the substrate (see Fig. 1 and [0027-0029]); and a molding compound (molding member 600) encapsulating the semiconductor dies, the first bond wires, and at least the first area of the first main surface of the substrate (see [0030]).
Han fails to disclose one or more support structures attached to the first main surface of the substrate, including an individual support structure having at least a respective portion thereof along the first stepped surface and vertically between the first area and the first stepped surface; and the molding compound encapsulating the one or more support structures, the respective portion being in direct physical contact with two or more semiconductor dies of the vertical stack.
MAO discloses a semiconductor device in Fig. 1A comprising: a substrate (substrate 102) having a first main surface (upper surface) and an opposing second main surface (lower surface) (see [0020]); a vertical stack of semiconductor dies (stack of dies 106, 108, 110, 112, and 114) attached to the first main surface (see [0019]), the one or more support structures (underfill material 126) attached to the first main surface of the substrate, including an individual support structure (underfill material 126 being one individual support structure) having at least a respective portion (the stepped portion of underfill material 126) thereof along a first stepped surface of the vertical stack (the stepped surface of the stack dies facing the underfill material 126) and vertically between a first area of the first main surface of the substrate (an area of the upper surface of substrate 102 below the first stepped surface of the stack of dies) and the first stepped surface, the respective portion being in direct physical contact with two or more semiconductor dies of the vertical stack (see Fig. 1A and [0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the support structures (underfill material 126) of MAO for attaching to the first main surface of the substrate and along the first stepped surface of the vertical stack of semiconductor dies of Han because the modified structure would provide a reliable support structure for higher level of offset vertical stack of semiconductor dies and further reduce die deflection and die cracking.
Regarding claim 3, the combination of Han and MAO discloses the semiconductor device of claim 1, further comprising a plurality of solder balls (external terminals 700 includes solder balls) attached to the second main surface of the substrate (substrate 300) (see Han, Fig. 1 and [0031]).
Regarding claim 5, the combination of Han and MAO discloses the semiconductor device of claim 3, wherein the one or more support structures are not electrically connected to any of the solder balls (underfill material 126 not electrically connect to solder ball 130) (see Fig. 1A of MAO).
Regarding claim 9, the combination of Han and MAO discloses the semiconductor device of claim 1, wherein each of the one or more support structures has a respective shape (underfill material 126 has stepped shape) configured to counteract a bending force applied to the vertical stack by a flow of a fluid molding compound (counteract a bending force applied to stack of dies 106, 108, 110, 112, and 114 by a flow of molding material 128 during molding process) (see MAO, Figs. 1A, 2G and [0041]).
Regarding claim 10, the combination of Han and MAO discloses the semiconductor device of claim 1, wherein the respective portion (the stepped portion of underfill material 126) is sloped (the stepped portion can be a slope respect to certain angle when tilting substrate 102) and substantially straight (has some straight area of the stepped portion) (see Fig. 1A of MAO)
Regarding claim 13, the combination of Han and MAO discloses the semiconductor device of claim 1, wherein a center of mass of the vertical stack is vertically above the first area of the first main surface (center of mass of the vertical stack of chips 110, 120, 130 and 140 is indirectly above the first area of substrate 300) (see Han and annotated Fig. 1 above).
Regarding claim 20, Han discloses a semiconductor device using a manufacturing method in Fig. 1, the method comprising: providing a substrate (substrate 300) having a first main surface (upper surface) and an opposing second main surface (lower surface) (see [0020]); forming a vertical stack of semiconductor dies (stack of chips 110, 120, 130 and 140) on the first main surface, the semiconductor dies being horizontally offset with respect to one another, the vertical stack having first (the stepped surface of the stack having no wiring) and second (the step surface of the stack having wirings 420) stepped surfaces (see Fig. 1 and [0019-0020]), the forming of the vertical stack being performed such that the first stepped surface overhanging a first area (the area of the upper surface of substrate 300 below the first stepped surface of the stack chips 110/120/130/140) of the first main surface of the substrate (see annotated Fig. 1 above and [0021]); electrically connecting the semiconductor dies one to another and to the substrate with first bond wires (plurality of wires 420 and 410) (see Fig. 1 and [0027-0029]); and encapsulating the semiconductor dies (by molding member 600), the first bond wires, and at least a portion of the first main surface in a molding compound (see [0030]).
Han fails to disclose the method comprising attaching one or more support structures to a first main surface of the substrate; the forming the vertical stack being performed such that the first stepped surface overhangs one or more respective portions of the one or more support structures; encapsulating the one or more support structures; and with the one or more support structures counteracting a bending force applied to the vertical stack by a flow of the molding compound; and wherein the one or more support structures include an individual support structure having at least a respective portion thereof along the first stepped surface and vertically between the first main surface and the first stepped surface, the respective portion being in direct physical contact with two or more semiconductor dies of the vertical stack.
Mao discloses a semiconductor device in Fig. 1A and 2A-2G made using a manufacturing method comprising: attaching one or more support structures (underfill material 126) to a first main surface of the substrate (upper surface of substrate 102) (see Figs. 1A, 2E and [0020], [0039]); forming a vertical stack (stack of dies 106, 108, 110, 112, and 114) on the first main surface such that a first stepped surface of the vertical stack (stepped surface of the stack of dies) overhangs one or more respective portions of the one or more support structures (the stepped portion of underfill material 126) (see Figs. 2A-2B and [0019]); encapsulating the semiconductor dies, the one or more support structures in a molding compound (molding compound 128) with the one or more support structures counteracting a bending force applied to the vertical stack by a flow of the molding compound (counteract a bending force applied to stack of dies 106, 108, 110, 112, and 114 by a flow of molding material 128 during molding process); and wherein the one or more support structures include an individual support structure (underfill material 126 being one individual support structure) having at least a respective portion (the stepped portion of underfill material 126) thereof along the first stepped surface and vertically between the first main surface and the first stepped surface, the respective portion being in direct physical contact with two or more semiconductor dies of the vertical stack (see Fig. 1A and [0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the support structures (underfill material 126) of MAO for attaching to the first main surface of the substrate and along the first stepped surface of the vertical stack of semiconductor dies of Han because the modified structure would provide a reliable support structure for higher level of offset vertical stack of semiconductor dies and further reduce die deflection and die cracking.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (Pub. No.: US 2018/0114776 A1), hereinafter as Han in view of MAO (Pub. No.: US 2019/0035705 A1), as applied to claim 3 and further in view of CHUNG et al. (Pub. No.: US 2023/0111207 A1), hereinafter as Chung.
Regarding claim 4, the combination of Han and MAO discloses the semiconductor device of claim 3, but fails to disclose wherein the substrate comprises a plurality of electrical paths connecting the plurality of solder balls to the first main surface.
Chung discloses a semiconductor device in Fig. 1 comprising a substrate (supporting plane 120 including pads 138) comprises a plurality of electrical paths (plurality of vias 126) connecting a plurality of solder balls (solder balls 125) to a first main surface of the substrate (pads 138 on the upper surface of supporting plane 120) (see [0021-0023]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the substrate of Han having the plurality of electrical paths connecting the plurality of solders balls to the first main surface of the substrate as same as the semiconductor device of Chung because the modified structure would provide a conventional and commercial way for providing the connection of the stack of chips to the circuit board with low manufacturing cost.
Claims 14 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (Pub. No.: US 2018/0114776 A1), hereinafter as Han in view of MAO (Pub. No.: US 2019/0035705 A1), as applied to claim 1, and further in view of CUI et al. (Pub. No.: US 2021/0407967 A1), hereinafter as Cui.
Regarding claim 14, the combination of Han and MAO discloses the semiconductor device of claim 1, wherein a first one of the semiconductor dies (chip 110) is directly attached to the first main surface (upper surface of substrate 300) (see Fig. 1 of Han and [0023]); but the combination of Han and MAO fails to disclose and wherein a vertical projection of a center of mass of the vertical stack onto the first main surface is outside a footprint of the first one of the semiconductor dies.
Cui discloses a semiconductor device in Figs. 1 and 3 comprising a vertical stack of semiconductor dies (plurality of dies 123) wherein a vertical projection of a center of mass of the vertical stack (center of mass is located at the center of the upper surface of the 7th die 123) onto the first main surface of the substrate is outside a foot print (projection of the center of mass outside of the footprint of the 1st die 123 at the bottommost) (see Fig. 3 and [0042-0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vertical stack of semiconductor dies of Han to have at least 14 semiconductor dies as same as the vertical stack of semiconductor dies of Cui for having the center of mass projected on to the substrate outside of the footprint of the first die at the bottommost because the disclosure of Han suggesting more than 5 dies can be stacked offset and having large number of dies on one stack would reduce the overall size of packaging and lowering manufacturing cost.
Regarding claim 16, the combination of Han and MAO discloses the semiconductor device of claim 1, fails to disclose wherein the semiconductor dies are non-volatile memory dies.
Cui discloses a semiconductor device in Figs. 1 and 3 comprising a vertical stack of semiconductor dies (plurality of dies 123), wherein the semiconductor dies are non-volatile memory dies (see [0058]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor dies of the stack of semiconductor device of Han to be made as non-volatile memory dies as same as the semiconductor dies of Cui because the modified structure would provide highly compact and reliable packaging for memory device with low manufacturing cost.
Regarding claim 17, the combination of Han and MAO discloses the semiconductor device of claim 1, but fails to disclose wherein the first stepped surface has eight or more steps.
Cui discloses a semiconductor device in Figs. 1 and 3 comprising a vertical stack of semiconductor dies (plurality of dies 123) being offset and wherein the vertical stack having a first (the stepped surface above support structure 104) and second stepped surface (the stepped surface having wire 302) and wherein the first stepped surface has eight or more steps (at least 14 steps) (see Fig. 3 and [0042-0044], [0073]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vertical stack of semiconductor dies of Han to have at least 14 semiconductor dies as same as the vertical stack of semiconductor dies of Cui for having at least eight or more steps because the disclosure of Han suggesting more than 5 dies can be stacked offset and having large number of dies on one stack would reduce the overall size of packaging and lowering manufacturing cost.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (Pub. No.: US 2018/0114776 A1), hereinafter as Han in view of MAO (Pub. No.: US 2019/0035705 A1), as applied to claim 1 and further in view of CHOI et al. (Pub. No.: US 2020/0105637 A1), hereinafter as Choi.
Regarding claim 15, the combination of Han and MAO discloses the semiconductor device of claim 1, but the combination of Han and MAO fails to disclose wherein the vertical stack includes sixteen semiconductor dies.
Choi discloses a semiconductor device in Figs. 1 and 3 comprising a vertical stack of semiconductor dies (plurality of chips 100) wherein the vertical stack includes sixteen semiconductor dies.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the number of semiconductor dies in a vertical stack of Han to have 16 semiconductor dies as same as the number of semiconductor dies of the vertical stack of Choi because the disclosure of Han suggesting more than 5 dies can be stacked offset and having large number of dies on one stack would reduce the overall packaging and lowering manufacturing cost.
Allowable Subject Matter
Claims 2, 6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having:
Wherein the individual support structure includes a second bond wire attached to the first main surface of the substrate and having a diameter greater than a diameter of the first bond wires as recited in claim 1.
wherein the one or more support structures include another individual support structure and wherein the one or more another individual support structure is in direct physical contact with the two or more semiconductor dies of the vertical stack as recited in claim 6.
Wherein the individual support structure comprises a respective length of round wire having a first arched shape or a respective length of ribbon wire having a second arched shape; and wherein the respective length of round wire or the respective length of ribbon wire is in direct physical contact with the two or more semiconductor dies of the vertical stack as recited in claim 8.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CUONG B NGUYEN/Primary Examiner, Art Unit 2818