Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/02/2025 has been entered.
Response to Amendment
Request for continued examination ( RCE ) filed 10/2/2025 and amendment filed 9/2/2025 have been entered. Claims 1, 4 are amended. Claims 12 – 15, 24 – 28 are withdrawn. Claims 16 – 23 are canceled. Claims 1 – 11 remain pending in the application.
Claim Rejections - 35 USC § 112
Regarding Independent Claim 1 ( currently amended ), based on the discussion in the interview 7/30/2025 and the reasons explained on page 9, lines 15 – 20 in the remarks filed 9/2/2025, the applicant’s response is persuasive, therefore, 35 USC § 112 on claim 1 is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 ̶ 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hayashi ( Pub. No. JP 2008277393 A ), hereinafter Hayashi, in view of Cho ( Pub. No. US 20140084457 A1 ), hereinafter Cho.
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Regarding Independent Claim 1 ( Currently Amended ), Hayashi teaches a semiconductor package comprising:
a first chip substrate ( Hayashi, FIG. 3, wiring board 2; FIG. 12, semiconductor element 3 ) comprising a first surface and a second surface which are opposite to each other;
a through via ( Hayashi, FIG. 4, FIG. 6, 42; [0036], Through-hole conductor 42 ) passing through the first chip substrate ( Hayashi, FIG. 3, wiring board 2; FIG. 12, semiconductor element 3 );
an upper passivation layer ( Hayashi, FIG. 5, FIG. 8, 51; [0041], insulating layers 51 ) comprising a trench ( Hayashi, FIG. 5, FIG. 8, 51A; [0041], via holes 51A ) on the second surface of the first chip substrate ( Hayashi, FIG. 3, wiring board 2; FIG. 12, semiconductor element 3 ), the trench ( Hayashi, FIG. 5, FIG. 8, 51A; [0041], via holes 51A ) exposing at least a portion of the second surface of the first chip substrate ( Hayashi, FIG. 3, wiring board 2; FIG. 12, semiconductor element 3 );
an upper pad ( Hayashi, FIG. 3, 24, 25, 26; abstract, conductive layer 24, low-melting point metal layer 25, a bonding layer 26 ) electrically connected with the through via ( Hayashi, FIG. 4, FIG. 6, 42; [0036], Through-hole conductor 42 ) on the trench ( Hayashi, FIG. 5, FIG. 8, 51A; [0041], via holes 51A );
a second chip substrate ( Hayashi, FIG. 3, semiconductor element 3; FIG. 12, mounting structure 2 ) comprising a third surface opposite to the second surface and a fourth surface opposite to the third surface;
a lower pad ( Hayashi, FIG. 2, FIG. 3, 32; [0020], electrode pads 32 ) electrically connected with the second chip substrate ( Hayashi, FIG. 3, semiconductor element 3; FIG. 12, mounting structure 2 ) on the third surface of the second chip substrate ( Hayashi, FIG. 3, semiconductor element 3; FIG. 12, mounting structure 2 ); and
a connection bump ( Hayashi, FIG. 3, 30; [0020], bumps 30 ) electrically connecting the upper pad ( Hayashi, FIG. 3, 24, 25, 26; abstract, conductive layer 24, low-melting point metal layer 25, a bonding layer 26 ) with the lower pad ( Hayashi, FIG. 2, FIG. 3, 32; [0020], electrode pads 32 ), the connection bump ( Hayashi, FIG. 3, 30; [0020], bumps 30 ) contacting the lower pad ( Hayashi, FIG. 2, FIG. 3, 32; [0020], electrode pads 32 ),
wherein a width ( Hayashi, FIG. 3, W; [0020], width dimension W ) of the connection bump ( Hayashi, FIG. 3, 30; [0020], bumps 30 ) on the second surface of the first chip substrate ( Hayashi, FIG. 3, wiring board 2; FIG. 12, semiconductor element 3 ) increases ( Hayashi, FIG. 3, W2 > W1; [0023], the width dimension W1 at the bottom 22 is, for example, 10 µm to 50 µm, and the width dimension W2 at the opening 23 is, for example, 20 µm to 80 µm ) as the connection bump ( Hayashi, FIG. 3, 30; [0020], bumps 30 ) becomes farther away from the second surface of the first chip substrate ( Hayashi, FIG. 3, wiring board 2; FIG. 12, semiconductor element 3 ) in a vertical direction.
wherein the upper pad ( Hayashi, FIG. 3, 24, 25, 26; abstract, conductive layer 24, low-melting point metal layer 25, a bonding layer 26 ) is in contact with at least a portion of the upper passivation layer ( Hayashi, FIG. 5, FIG. 8, 51; [0041], insulating layers 51 ), at least a portion of the connection bump ( Hayashi, FIG. 3, 30; [0020], bumps 30 ).
Hayashi fails to teach wherein the upper pad is in contact with … and at least a portion of the through via, and the upper pad is formed of a single layer.
However, Cho teaches wherein the upper pad ( Cho, FIG. 10, 205; [0124], second pads 205 ) is in contact ( Cho, [0124], through-vias 207 ) with … and at least a portion of the through via ( Cho, [0124], through-vias 207 ), and the upper pad is formed of a single layer ( Cho, FIG. 10, 205; [0124], second pads 205 ).
Hayashi and Cho are considered to be analogous to the claimed invention because they are in the same field of semiconductor package. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hayashi ( semiconductor package ) to incorporate the teachings of Cho ( FIG. 10, 205 contact 207 ), to make the upper pad ( second pads 205 ) is in contact with at least a portion of the through via ( vias 207 ), and the upper pad (second pads 205 ) is formed of a single layer. Doing so would provide a specific design for the upper pad and through via, so that a specific semiconductor package can be implemented.
Regarding Claim 2 ( Original ), Hayashi and Cho teach the semiconductor package of claim 1, on which this claim is dependent, Hayashi further teaches:
wherein the upper pad ( Hayashi, FIG. 3, 24, 25, 26; abstract, conductive layer 24, low-melting point metal layer 25, a bonding layer 26 ) comprises a first portion ( Hayashi, FIG. 5, the bottom part of 52 ) extending along a bottom surface of the trench ( Hayashi, FIG. 5, FIG. 8, 51A; [0041], via holes 51A ), a second portion ( Hayashi, FIG. 5, the sidewall part of 52 ) extending along a sidewall of the trench ( Hayashi, FIG. 5, FIG. 8, 51A; [0041], via holes 51A ), and a third portion ( Hayashi, FIG. 5, the top part of 52 ) extending along at least a portion of an upper surface of the upper passivation layer ( Hayashi, FIG. 5, FIG. 8, 51; [0041], insulating layers 51 ).
Regarding Claim 3 ( Original ), Hayashi and Cho teach the semiconductor package of claim 2, on which this claim is dependent, Hayashi further teaches:
wherein the connection bump ( Hayashi, FIG. 3, 30; [0020], bumps 30 ) contacts at least a portion of the first portion ( Hayashi, FIG. 5, the bottom part of 52 ) and at least a portion of the second portion ( Hayashi, FIG. 5, the sidewall part of 52 ).
Regarding Claim 4 ( Currently Amended ), Hayashi and Cho teach the semiconductor package of claim 2, on which this claim is dependent, Hayashi further teaches:
wherein the connection bump ( Hayashi, FIG. 3, 30; [0020], bumps 30 ) comprises a first surface ( Hayashi, FIG. 3, top surface of 30, width W ) contacting the second surface of the first chip substrate ( Hayashi, FIG. 3, wiring board 2; FIG. 12, semiconductor element 3 ) and a second surface ( Hayashi, FIG. 3, bottom surface of 30 ) opposite to the first surface of the connection bump, and
wherein a width ( Hayashi, FIG. 3, the width of 30 on the bottom surface ) of the second surface ( Hayashi, FIG. 3, bottom surface of 30 ) of the connection bump ( Hayashi, FIG. 3, 30; [0020], bumps 30 ) is smaller than a width ( Hayashi, FIG. 3, W1; [0023], a width dimension W1 at the bottom 22 ) of the first portion ( Hayashi, FIG. 3, 22; [0023], the bottom 22 ).
Regarding Claim 5 ( Preciously presented ), Hayashi and Cho teach the semiconductor package of claim 1, on which this claim is dependent, Hayashi further teaches:
wherein a width ( Hayashi, FIG. 3, W; [0020], width dimension W ) of the trench ( Hayashi, FIG. 5, FIG. 8, 51A; [0041], via holes 51A ) on the second surface of the first chip substrate ( Hayashi, FIG. 3, wiring board 2; FIG. 12, semiconductor element 3 ) decreases ( Hayashi, FIG. 3, W2 > W1; [0023], the width dimension W1 at the bottom 22 is, for example, 10 µm to 50 µm, and the width dimension W2 at the opening 23 is, for example, 20 µm to 80 µm ) as the trench ( Hayashi, FIG. 5, FIG. 8, 51A; [0041], via holes 51A ) becomes farther away from the second chip substrate ( Hayashi, FIG. 3, semiconductor element 3; FIG. 12, mounting structure 2 ) in the vertical direction.
Regarding Claim 6 ( Original ), Hayashi and Cho teach the semiconductor package of claim 1, on which this claim is dependent, Hayashi further teaches:
wherein a material of the connection bump ( Hayashi, FIG. 3, 30; [0020], bumps 30 ) is different ( Hayashi, [0021], bump 30 may be any conductive material that has a melting point higher than the material constituting the low melting point metal layer 25 ) from a material of the upper pad ( Hayashi, FIG. 3, 24, 25, 26; abstract, conductive layer 24, low-melting point metal layer 25, a bonding layer 26 ).
Regarding Claim 7 ( Original ), Hayashi and Cho teach the semiconductor package as claimed in claim 1, on which this claim is dependent, Cho further teaches:
wherein a melting point of the connection bump ( Cho, [0105], solder plating layer 140 ) is lower ( Cho, [0105], The melting temperature of the solder plating layer 140 may be lower than that of the metal layer 131 ) than a melting point of the upper pad ( Cho, [0105], metal layer 131 ).
Regarding Claim 8 ( Original ), Hayashi and Cho teach the semiconductor package as claimed in claim 1, on which this claim is dependent , Cho further teaches:
wherein the connection bump ( Cho, [0105], Additionally, the solder plating layer 140 may further include an additive such as copper (Cu) … ) comprises the same material as a material of the upper pad ( Cho, [0083], the metal layer 131 may include copper (Cu) … ), and does not comprise tin (Sn).
Regarding Claim 9 ( Original ), Hayashi and Cho teach the semiconductor package as claimed in claim 1, on which this claim is dependent, Cho further teaches:
further comprising a seed layer ( Cho, [0082], seed pattern 126 ) between the connection bump ( Cho, [0082], solder layer 141 ) and the lower pad ( Cho, [0085], first pad 105 ).
Regarding Claim 10 ( Previously presented ), Hayashi and Cho teach all the limitation of claim 9 on which this claim depends. Hayashi and Cho further teach:
wherein a width ( Hayashi, FIG. 3, W; [0020], width dimension W ) of the seed layer ( Cho, [0082], seed pattern 126 ) on the second surface of the first chip substrate ( Hayashi, FIG. 3, wiring board 2; FIG. 12, semiconductor element 3 ) is reduced and then increased ( Cho, FIG. 1C, UR; [0087], Sidewalls of the patterns 121 and 126 and the layers 131 and 146, which are disposed under the solder layer 141, may have an undercut region UR which is laterally recessed from a sidewall of the solder layer 141 ) as the seed layer ( Cho, [0082], seed pattern 126 ) becomes farther away from the second surface of the first chip substrate ( Hayashi, FIG. 3, wiring board 2; FIG. 12, semiconductor element 3 ) in the vertical direction.
Regarding Claim 11 ( Previously presented ), Hayashi and Cho teach all the limitation of claim 9 on which this claim depends. Hayashi and Cho further teach:
wherein the seed layer comprises a first seed layer ( Cho, FIG. 1C, 126; [0082], seed pattern 126 ) on the lower pad ( Hayashi, FIG. 2, FIG. 3, 32; [0020], electrode pads 32 ), and a second seed layer ( Cho, FIG. 1C, 146; [0086], metal-solder compound layer 146 ) between the first seed layer ( Cho, [0082], seed pattern 126 ) and the connection bump ( Cho, [0082], solder layer 141 ), the second seed layer ( Cho, FIG. 1C, 146; [0086], metal-solder compound layer 146 ) comprising a material different ( Cho, [0086], metal-solder compound layer 146 may include copper (Cu)-tin (Sn)-silver (Ag) alloy ) from a material of the first seed layer ( Cho, [0084], seed pattern 126 may include copper (Cu) ).
Response to Arguments
Applicant's remarks filed 9/2/2025 have been fully considered but they are not persuasive.
Applicant’s remarks regarding Independent Claim 1 ( Currently Amended ): page 12, line 10 from bottom, cited “ Thus, Hayashi fails to disclose or suggest at least "wherein the upper pad is in contact with at least a portion of the upper passivation layer, at least a portion of the connection bump, and at least a portion of the through via, and the upper pad is formed of a single layer," as recited in claim 1. ”
Examiner’s response: please refer to claim 1 in Claim Rejections - 35 USC § 103 of this office action, cited “ However, Cho teaches wherein the upper pad ( Cho, FIG. 10, 205; [0124], second pads 205 ) is in contact ( Cho, [0124], through-vias 207 ) with … and at least a portion of the through via ( Cho, [0124], through-vias 207 ), and the upper pad is formed of a single layer ( Cho, FIG. 10, 205; [0124], second pads 205 ). ”.
Applicant’s remarks regarding Independent Claim 4 ( Currently Amended ): page 13, line 5, cited “ In Hayashi, as the lower surface of the bump 30 and the surface of the bonding layer 26 extending along a bottom of the trench are equal to each other, Hayashi fails to disclose or suggest the feature of claim 4. ”.
Examiner’s response: in claim 4, the final sentence “ a width of the first portion ” is not mapped by Hayashi’s “ the width of bonding layer 26 ”; it is mapped by Hayashi’s “ the width W1 at the bottom 22 ”, please refer to claim 4 in Claim Rejections - 35 USC § 103 of this office action, cited “ wherein a width ( Hayashi, FIG. 3, the width of 30 on the bottom surface ) of the second surface ( Hayashi, FIG. 3, bottom surface of 30 ) of the connection bump (Hayashi, FIG. 3, 30; [0020], bumps 30) is smaller than a width (Hayashi, FIG. 3, W1; [0023], a width dimension W1 at the bottom 22) of the first portion (Hayashi, FIG. 3, 22; [0023], the bottom 22) ”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817