CTFR 17/831,100 CTFR 99372 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-21-aia AIA Claim (s) 1, 3, 6, 12-13, 16, and 22-25 are rejected under 35 U.S.C. 103 as being unpatentable over Kothari (PGPub NO. 20210028087) in further view of Stecher (PGPub No. 20130280879) . Regarding claim 1, Kothari teaches an integrated circuit (IC) die, comprising: a substrate comprising a crystalline material (Fig. 1A and [0023] point to a semiconductor die 100 comprising a substrate 110 made of semiconductor material such as single crystal silicon or polycrystalline silicon.); a plurality of transistors on a first side of the substrate (Fig. 1A and [0024] point to an active device layer 112 which may comprise one or more transistors.); a first metallization structure on the first side of the substrate and coupled to one or more of the transistors, wherein the first metallization structure comprises a plurality of signal lines having a first minimum pitch (Fig. 4G point to an alternative embodiment comprising a substrate 410, first interconnect layers 440, and the active device layer 412 (one or more transistors). [0048] further points to the first interconnect layers 440 comprising conductive traces 424 and conductive vias 426, which together (first metallization structure; plurality of signal lines) may provide electrical coupling between the portions of the active device layer 412.); a second metallization structure on a second side of the substrate, opposite the first side, and coupled to one or more of the transistors, wherein the second metallization structure comprises a plurality of power rail lines having a second minimum pitch, larger than the first minimum pitch (Fig. 4G and [0054] point to second interconnect layers 440 comprising conductive traces 424 and conductive vias 426, which together (second metallization structure; plurality of power rail lines) may provide electrical routing to the bumps 430. It is considered obvious that power rail lines would use a larger pitch than signal lines due to power rail lines carrying much more current, which a larger pitch would help with by reducing resistance and/or coupling.); a first electrical isolation on the first side of the substrate, wherein the first metallization structure is embedded within the first electrical isolation (Fig. 4G points to the first interconnect layers 440 comprising ILD layers 422 (first electrical isolation).); a second electrical isolation on the first side of the substrate, wherein the second metallization structure is embedded within the second electrical isolation ( Id. points to the second interconnect layers 420 comprising ILD layers 422 (second electrical isolation).), and wherein: the first electrical isolation and the second electrical isolation both comprise silicon dioxide ([0026] points to an embodiment where the ILD material used comprises suitable dielectric materials such as, but not limited to, oxides of silicon (e.g., silicon dioxide).); and a plurality of interconnect interfaces coupled to the second metallization structure (Fig. 4G points to bumps 430.). Kothari fails to teach the second electrical isolation further comprises crystalline carbon or boron arsenide interspersed within the silicon dioxide, and the crystalline carbon or boron arsenide present within the second electrical isolation is absent from the first electrical isolation. Kothari in combination with Stecher teaches the second electrical isolation further comprises crystalline carbon or boron arsenide interspersed within the silicon dioxide ([0027] of Stecher points to a dielectric layer 2 comprising a base material, for instance a silicon oxide, which is doped with a dopant, for instance phosphorus (P), boron (B), silver (Ag), arsenic (As), argon (Ar), or a combination thereof.), and the crystalline carbon or boron arsenide present within the second electrical isolation is absent from the first electrical isolation ([0026] of Kothari points to an embodiment where the ILD material used comprises suitable dielectric materials such as, but not limited to, oxides of silicon (e.g., silicon dioxide).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Kothari and Stecher, such that the second electrical isolation further comprises additional material such as boron arsenide in order to create a doped material layer with specifically altered properties such as its wet and/or dry etching rate. Regarding claim 3, Stecher teaches wherein the second electrical isolation is mostly boron arsenide ([0027] points to a dielectric layer 2 comprising a base material, for instance a silicon oxide, which is doped with a dopant, for instance phosphorus (P), boron (B), silver (Ag), arsenic (As), argon (Ar), or a combination thereof that affects the wet and/or dry etching rate. Additionally, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the ratio of silicon dioxide to boron arsenide to be a result effective variable affecting properties such as the etch rate and/or thermal conductivity. Thus, it would have been obvious to modify the device of Stecher to have the ratio of boron arsenide within the claimed range in order to create a layer with specifically desired properties, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05(II)(B) and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff , 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc. , 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kothari and Stecher, such that the second electrical isolation is mostly boron arsenide in order to in order to create a doped material layer with specifically altered properties such as its wet and/or dry etching rate. Regarding claim 6, Stecher teaches wherein the second electrical isolation comprises predominantly silicon, oxygen, boron, and arsenic ([0027] points to a dielectric layer 2 comprising a base material, for instance a silicon oxide, which is doped with a dopant, for instance phosphorus (P), boron (B), silver (Ag), arsenic (As), argon (Ar), or a combination thereof that affects the wet and/or dry etching rate.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kothari and Stecher, such that the second electrical isolation comprises predominantly silicon, oxygen, boron, and arsenic in order to in order to create a doped material layer with specifically altered properties such as its wet and/or dry etching rate. Regarding claim 12, Kothari teaches a substrate (Fig. 2 points to an electronic system 250 comprising a package substrate 260.); a power supply ( Id. points to the package substrate 260 being electrically coupled to the board 267. It is considered obvious the board 267 includes or at least connects to a power supply.); and the IC die of claim 1 attached to the substrate and coupled to the power supply (see analysis of claim 1). Regarding claim 13, Kothari teaches the system of claim 12, further comprising a heat sink coupled to the IC die (Fig. 2 points to a heat sink 253.). Regarding claim 16, Kothari teaches a heat sink thermally coupled to the IC die, the IC die between the heat sink and the substrate (Fig. 2 points to a heat sink 253, the package substrate 260, and the semiconductor die 200 (IC die).), the IC die further comprising the first electrical isolation between the transistors and the heat sink (Fig. 4G points to an alternative single die 401 comprising the active device layer 412 (transistors) and the ILD layers 422 (first electrical isolation) located within the first interconnect layers 440.). Regarding claim 22, Kothari teaches wherein the second metallization structure comprises a plurality of metallization levels and wherein the metallization levels are embedded within multiple layers of the second electrical isolation (Fig. 4G points to the second interconnect layers 420 comprising conductive traces 424 and conductive vias 426 (second metallization structure) which are embedded in ILD layers 422 (second electrical isolation).). Regarding claim 23, Kothari in combination with Stecher teaches wherein the concentration of crystalline carbon or boron arsenide is higher in layers of the second electrical isolation adjacent to metallization levels that are to have higher current density (Fig. 4G of Kothari points to the second interconnect layers 420 comprising conductive traces 424 and conductive vias 426 (second metallization structure) which are embedded in ILD layers 422 (second electrical isolation). [0027] of Stecher further points to a dielectric layer 2 comprising a base material, for instance a silicon oxide, which is doped with a dopant, for instance phosphorus (P), boron (B), silver (Ag), arsenic (As), argon (Ar), or a combination thereof. It is considered obvious that one of ordinary skill in the art would position/form the boron arsenide in higher concentrations around areas of higher current density due to the well-known thermal conductivity of boron arsenide, which would be better suited to dissipating the higher concentrations of heat that would naturally occur along said current(s).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kothari and Stecher, such that the concentration of boron arsenide is higher in layers of the second electrical isolation with a higher current density in order to improve heat dissipation. Regarding claim 24, Kothari in combination with Stecher teaches wherein the concentration of crystalline carbon or boron arsenide is lower in layers of the second electrical isolation adjacent to metallization levels with tighter interconnect line pitches (Fig. 4G of Kothari points to the second interconnect layers 420 comprising conductive traces 424 and conductive vias 426 (second metallization structure) which are embedded in ILD layers 422 (second electrical isolation). [0027] of Stecher further points to a dielectric layer 2 comprising a base material, for instance a silicon oxide, which is doped with a dopant, for instance phosphorus (P), boron (B), silver (Ag), arsenic (As), argon (Ar), or a combination thereof. It is considered obvious that one of ordinary skill in the art would position/form the boron arsenide in lower concentrations around areas of tighter interconnect line pitches due to the lower current density that would occur from a tighter/smaller pitch.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kothari and Stecher, such that the concentration of boron arsenide is lower in layers of the second electrical isolation with a tighter interconnect line pitches in order to provide adequate levels of heat dissipation based on the local current density. Regarding claim 25, Stecher teaches wherein the second electrical isolation has a higher relative permittivity than the first electrical isolation ([0027] further points to a dielectric layer 2 (second electrical isolation) comprising a base material, for instance a silicon oxide, which is doped with a dopant, for instance phosphorus (P), boron (B), silver (Ag), arsenic (As), argon (Ar), or a combination thereof. Since it is well known that boron arsenide has a higher relative permittivity than silicon dioxide, it is considered obvious that a layer/electrical isolation comprising both materials would have a higher relative permittivity than one comprising only silicon dioxide.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kothari and Stecher, such that the second electrical isolation has a higher relative permittivity than the first electrical isolation in order to better handle local heat dissipation needs . 07-21-aia AIA Claim (s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kothari et al. in further view of Cotronakis (PGPub No. 20210375797) . Regarding claim 15, Cotronakis teaches a heat sink thermally coupled to the substrate, the heat sink coupled to the substrate on a side of the substrate distal from the IC die (Fig. 2 and [0037] point to an LGA package 20 comprising a substrate 22, and IC die 30 and a lower metal layers 46 and 48, which may also function as a heatsink or heatspreader in embodiments.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kothari et al. and Cotronakis, such that the heat sink is coupled to the substrate and away from the IC die in order to better manage the heat dissipation of both the IC die and the underlying substrate . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 7-9 allowed. 13-03 AIA The following is an examiner’s statement of reasons for allowance: Applicant’s amendments to previously rejected claims 7-9, overcome said rejections made by the examiner as well as attempts at finding new grounds for rejection via further analysis. A primary reason for allowance of the claims is the disclosure of the second electrical isolation comprising silicon dioxide and particles of crystalline carbon, which distinguishes the claim(s) over the prior art of record . Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments 07-38-02 AIA Applicant’s arguments, see Remarks , filed 01/30/2026 , with respect to the rejection(s) of claim(s) 1, 3, 6, 12-13, and 16 (and by extension any dependent claims) under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kothari in further view of Stecher (PGPub No. 20130280879) . Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICK CULLEN/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 17/831,100 Page 2 Art Unit: 2899 Application/Control Number: 17/831,100 Page 3 Art Unit: 2899 Application/Control Number: 17/831,100 Page 4 Art Unit: 2899 Application/Control Number: 17/831,100 Page 5 Art Unit: 2899 Application/Control Number: 17/831,100 Page 6 Art Unit: 2899 Application/Control Number: 17/831,100 Page 7 Art Unit: 2899 Application/Control Number: 17/831,100 Page 8 Art Unit: 2899 Application/Control Number: 17/831,100 Page 9 Art Unit: 2899 Application/Control Number: 17/831,100 Page 10 Art Unit: 2899 Application/Control Number: 17/831,100 Page 11 Art Unit: 2899 Application/Control Number: 17/831,100 Page 12 Art Unit: 2899
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