DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-5, 8, 9, 12-18, 22, and 25-28 are amended and previously presented.
Claim 6, 7, 10, 11, 19, 20, 23, and 24 are withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 6, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 18. Claim 18 recites “the first conductive structure further includes a third portion” in the claim language. Claim 18 depends upon independent claim 16 which also recites a third portion of the first conductive structure. It’s unclear to the examiner if “a third portion” of claim 18 is the same as that of claim 16 or a different third portion.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 5, 8, 9, 12, 13, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al (U.S. 2016/0005851), Liu et al (U.S. 2014/0302660), and Chang et al (U.S. 2017/0110569)
Regarding claim 1. Song et al discloses a semiconductor device (FIG. 3A to 3C, 16, 20; [0165]), comprising:
a first active pattern (FIG. 16, item AP) protruding above a substrate (FIG. 16, item 102), an upper portion (FIG. 16, item AF) of the first active pattern (FIG. 16, item AP) including a first channel region ([0096], i.e. Portions of the active patterns AP (e.g., portions of the active fins AF) that are disposed under and overlap the gate electrodes G1 and G2 may operate as channel regions) and a first source/drain region (FIG. 16, item S/D) connected to the first channel region (FIG. 16, item AF);
a device isolation pattern (FIG. 20, item ST3) on a sidewall ([0090], i.e. third device isolation layers ST3 extend in the x-direction, and may be disposed at both sides of each active pattern AP) of a lower portion (FIG. 20, item 100) of the first active pattern (FIG. 20, item AP);
a first gate electrode (FIG. 16, item G2 or G1) an the first channel region (FIG. 16, item AF) of the first active pattern (FIG. 16, item AP);
a first lower conductive structure (FIG. 16, item TS) electrically connected ([0154], i.e. conductive patterns TS may electrically connect the source/drain regions SD) to the first source/drain region (FIG. 16, item SD);
a first conductive structure (FIG. 15, item CC) on the first lower conductive structure (FIG. 16, item TS), the first conductive structure (FIG. 15, item CC) including a first portion (FIG. 16, item CB1) and a second portion (FIG. 16, item CA1) that are connected to each ([0102], i.e. connecting contact CC may include first sub-contacts CA1 disposed at each side of the first gate electrode G1 and a second sub-contact CB1 connecting the first sub-contacts CA1 to each other) other to constitute a single body (FIG. 16, item CC), the second portion (FIG. 16, item CA1) extending from the first portion (FIG. 16, item CB1) toward the first lower conductive structure (FIG. 16, item TS) and connected to the first lower conductive structure (FIG. 16, item TS),
wherein the first conductive structure (FIG. 16, item CC) further includes a third portion (FIG. 16, item third portion) extending ([0141], i.e. The second sub-contact CB1 may be in contact with the top surface of the first gate electrode G1) from first portion (FIG. 16, item first portion) toward the first gate electrode (FIG. 16, item G1) and connected to the first gate electrode (FIG. 16, item G1)
Song et al fails to explicitly disclose an interconnection line on the first conductive structure; and
a barrier pattern,
a via between the interconnection line and the first portion, and connecting the interconnection line and the first conductive structure,
and wherein a gap is formed between the third portion and the second portion, the gap being adjacent to the first portion and filled with an insulating layer that contacts a surface of the first portion.
wherein the first conductive structure further includes a vertically-extended portion protruding from a bottom of the second portion and covering an upper sidewall of the first lower conductive structure, wherein the vertically-extended portion is spaced apart from the first gate electrode, and wherein the barrier pattern comprises a first barrier portion between the second portion of the first conductive structure and the first lower conductive structure, a second barrier portion between the first gate electrode and the third portion of the first conductive structure, and a third barrier portion on a sidewall of the vertically-extended portion of the first conductive structure, and wherein the first barrier portion, the second barrier portion, and the third barrier portion of the barrier pattern are formed conformally and configured to cover the first portion, the second portion, the third portion, and the vertically-extended portion of the first conductive structure.
However, Liu et al teaches an interconnection line (FIG. 4, item 120) on the first conductive structure (FIG. 4, item 110); and
a via (FIG. 4, item 116A) between the interconnection line (FIG. 4, item 120) and the first portion (FIG. 4, item 110), and connecting ([0018], i.e. a first contact formed over the protection diode (and optional trench silicide layer), a second contact formed over the RMG transistor, wherein the first contact extends to connect directly with the second contact, and a top metal layer (M1) formed over the first contact and the second contact) the interconnection line (FIG. 120) and the first conductive structure (FIG. 4, item 110).
Since Both Song et al and Liu et al teach conductive patterns with metal silicide, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed in Song et al with the an interconnection line on the first conductive structure, and a via between the interconnection line and the first portion, and connecting the interconnection line and the first conductive structure as disclosed by Liu et al. The use of first contact formed over the protection diode (and optional trench silicide layer), a second contact formed over the RMG transistor, wherein the first contact extends to connect directly with the second contact, and a top metal layer (M1) formed over the first contact and the second contact in Liu et al provides for any charges accumulated during formation of the second contact and the set of vias will be discharged by the protection diode (Liu et al, Abstract).
Song et al and Liu et al fail to explicitly disclose
a barrier pattern,
and wherein a gap is formed between the third portion and the second portion, the gap being adjacent to the first portion and filled with an insulating layer that contacts a surface of the first portion.
wherein the first conductive structure further includes a vertically-extended portion protruding from a bottom of the second portion and covering an upper sidewall of the first lower conductive structure, wherein the vertically-extended portion is spaced apart from the first gate electrode, and wherein the barrier pattern comprises a first barrier portion between the second portion of the first conductive structure and the first lower conductive structure, a second barrier portion between the first gate electrode and the third portion of the first conductive structure, and a third barrier portion on a sidewall of the vertically-extended portion of the first conductive structure, and wherein the first barrier portion, the second barrier portion, and the third barrier portion of the barrier pattern are formed conformally and configured to cover the first portion, the second portion, the third portion, and the vertically-extended portion of the first conductive structure.
However, Chang et al teaches
a barrier pattern (FIG. 76, item 402),
and wherein a gap (FIG. 76, item 320) is formed between the third portion (FIG. 76, item 412 on left side of item 320) and the second portion (FIG. 76, item 412 on right side of item 320), the gap being (FIG. 76, item 320) adjacent to the first portion (FIG. 76, item 412 above item 320) and filled with an insulating layer ([0250]) that contacts a surface (FIG. 76, item 402 above item 320) of the first portion (FIG. 76, item 422 above item 320).
wherein the first conductive structure (FIG. 76, item 412) further includes a vertically-extended portion (FIG. 76, item 422b on right side of item 310) protruding from a bottom of the second portion (FIG. 76, item 412 on right side of item 320) and covering an upper sidewall (FIG. 76, item 160) of the first lower conductive structure (FIG. 76, right side item 250), wherein the vertically-extended portion (FIG. 76, item 422b) is spaced apart (FIG. 76, item 320) from the first gate electrode (FIG. 76, left side item 250), and wherein the barrier pattern (FIG. 76, item 402) comprises a first barrier portion (FIG. 76, item 402) between the second portion (FIG. 76, item 412 on right side of item 320) of the first conductive structure (FIG. 76, item 412) and the first lower conductive structure (FIG. 76, right side item 250), a second barrier portion (FIG. 76, item 402) between the first gate electrode (FIG. 76, left side item 250) and the third portion (FIG. 76, item 412 on left side of item 320) of the first conductive structure (FIG. 76, item 412), and a third barrier portion (FIG. 76, item 402) on a sidewall of the vertically-extended portion (FIG. 76, item 422b on right side of item 310) of the first conductive structure (FIG. 76, item 412), and wherein the first barrier portion (FIG. 76, item 402), the second barrier portion (FIG. 76, item 402), and the third barrier portion (FIG. 76, item 402) of the barrier pattern (FIG. 76, item 402) are formed conformally ([0187]) and configured ([0187]) to cover ([0187]) the first portion (FIG. 76, item 412 above item 320), the second portion (FIG. 76, item 412 on right side of item 320), the third portion (FIG. 76, item 412 on left side of item 320), and the vertically-extended portion (FIG. 76, item 422b on right side of item 310) of the first conductive structure (FIG. 76, item 412).
Since Song et al, Liu et al and Chang et al teach contact structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Song et al and Liu et al with the teachings of a barrier pattern, and wherein a gap is formed between the third portion and the second portion, the gap being adjacent to the first portion and filled with an insulating layer that contacts a surface of the first portion, wherein the first conductive structure further includes a vertically-extended portion protruding from a bottom of the second portion and covering an upper sidewall of the first lower conductive structure, wherein the vertically-extended portion is spaced apart from the first gate electrode, and wherein the barrier pattern comprises a first barrier portion between the second portion of the first conductive structure and the first lower conductive structure, a second barrier portion between the first gate electrode and the third portion of the first conductive structure, and a third barrier portion on a sidewall of the vertically-extended portion of the first conductive structure, and wherein the first barrier portion, the second barrier portion, and the third barrier portion of the barrier pattern are formed conformally and configured to cover the first portion, the second portion, the third portion, and the vertically-extended portion of the first conductive structure as disclosed by Chang et al. The use of the first portion of the bottom (e.g., bottom surface) of the second contact plug may be formed in the first insulating interlayer so as to be higher than the upper surface of the gate structure, the second portions of the bottom (e.g., bottom surface) of the second contact plug may be formed in the insulation layer so as to be lower than the upper surface of the gate structure, and the third portion of the bottom of the second contact plug may contact the upper surface of the gate structure in Chang et al provides for the lowest surface of the convex portion of the bottom of the second contact plug, may not contact the upper surface of the substrate, and thus the electrical failure due to the leakage current from the contact plug to the substrate may be prevented (Chang et al, [0252]).
Regarding claim 2. Song et al, Liu et al, and Chang et al discloses all the limitations of the semiconductor device of claim 1 above.
Song et al discloses the first conductive structure.
wherein the third portion (FIG. 16, item third portion) is provided ([0141], i.e. The second sub-contact CB1 may be in contact with the top surface of the first gate electrode G1; [0094], i.e. Gate electrodes G1 and G2 may be provided on the active patterns AP) on the first active pattern (FIG. 16, item AP).
PNG
media_image1.png
453
699
media_image1.png
Greyscale
Regarding claim 5. Song et al, Liu et al, and Chang et al discloses all the limitations of the semiconductor device of claim 1 above.
Song et al further discloses wherein the first conductive structure (FIG. 16, item CC) contains aluminum or tungsten ([0102], i.e. the first and second sub-contacts CA1 and CB1 may include tungsten).
Regarding claim 8. Song et al, Liu et al, and Chang et al discloses all the limitations of the semiconductor device of claim 1 above.
Song et al further discloses wherein the first conductive structure (FIG. 15, item CC) further includes a vertically-extended portion (FIG. 16, item CB1) covering an upper sidewall (FIG. 16, sidewall of item TS) of the first lower conductive structure (FIG. 16, item TS).
PNG
media_image2.png
492
629
media_image2.png
Greyscale
Regarding claim 9. Song et al, Liu et al, and Chang et al discloses all the limitations of the semiconductor device of claim 8 above.
Song et al further discloses wherein a bottom surface (FIG. 16, bottom surface of item CB1) of the vertically-extended portion (FIG. 16, item CB1) is lower (FIG. 16 shows a bottom surface of item CB1 is lower than a top surface of item TS) than a top surface (FIG. 16, top surface of item TS) of the first lower conductive structure (FIG. 16, item TS).
PNG
media_image3.png
564
614
media_image3.png
Greyscale
Regarding claim 12. Song et al, Liu et al, and Chang et al discloses all the limitations of the semiconductor device of claim 1 above.
Song et al further discloses wherein a top surface of the first lower conductive structure (FIG. 16, item TS) is higher than top surface ([0119], i.e. top surfaces of the connecting conductive patterns TS may be higher than top surfaces of the gate electrodes G1 and G2) of the first gate electrode (FIG. 16, item G2).
Regarding claim 13. Song et al, Liu et al, and Chang et al discloses all the limitations of the semiconductor device of claim 1 above.
Song et al further discloses wherein a bottom surface (FIG. 16, bottom of item CA1) of the second portion (FIG. 1, item CA1) is higher than a top surface (FIG. 16, top surface of item G2 or G1) of the first gate electrode (FIG. 16, item G2 or G1).
PNG
media_image4.png
439
878
media_image4.png
Greyscale
Regarding claim 15. Song et al, Liu et al, and Chang et al discloses all the limitations of the semiconductor device of claim 1 above.
Song et al further discloses wherein the first portion (FIG. 16, item CB1) has a flat plate structure ([0010], i.e. each of the first sub-contacts may have a bar shape extending in the first direction).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al (U.S. 2016/0005851), Liu et al (U.S. 2014/0302660) and Chang et al (U.S. 2017/0110569), as applied to claim 1 above, and further in view of Li et al (U.S. 2014/0103404).
Regarding claim 3. Song et al, Liu et al and Chang et al discloses all the limitations of the semiconductor device of claim 1 above.
Song et al further discloses further comprising:
a pair of gate spacers (FIG. 16, item GS) on opposite sidewalls of the first gate electrode (FIG. 16, item G1 or G2); and a gate insulating pattern (FIG. 16, item GI) between the first gate electrode and the first channel region (FIG. 16, item AF), wherein the gate insulating pattern (FIG. 16, item GI) includes: a horizontal portion (FIG. 16, item GI) between ([0116], i.e. A gate dielectric pattern G1 may be formed between the substrate 100 and each of the gate electrodes G1 and G2) a bottom surface (FIG. 16, bottom surface of item G1 or G2) of the first gate electrode (FIG. 16, item G1 or G2) and a top surface (FIG. 16, top surface of item AF) of the first channel region (FIG. 16, item AF);
Song et al fails to explicitly a pair of vertical portions (FIG. 1, item 51A/51B) between the opposite sidewalls of the first gate electrode (FIG. 1, item 27A/27B) and the pair of gate spacers (FIG. 1, item 52A/52B, respectively ([0031], i.e. the at least one gate spacer can include a first inner gate spacer 51A formed around the first disposable gate structure (29A, 27A), a first outer gate spacer 52A formed around the first inner gate spacer 51A, a second inner gate spacer 51B formed around the second disposable gate structure (29B, 27B), and a second outer gate spacer 52B formed around the second inner gate spacer 51B ).
However, Li et al teaches a pair of vertical portions between the opposite sidewalls of the first gate electrode and the pair of gate spacers, respectively.
Since Song et al, Liu et al, Chang et al and Li et al teach gate structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Song et al, Liu et al, Chang et al with the teachings of a pair of vertical portions between the opposite sidewalls of the first gate electrode and the pair of gate spacers, respectively as disclosed by Li et al. The use of the at least one gate spacer can include a first inner gate spacer formed around the first disposable gate structure, a first outer gate spacer formed around the first inner gate spacer, a second inner gate spacer formed around the second disposable gate structure, and a second outer gate spacer formed around the second inner gate spacer in Li et al provides for an inner dielectric spacer prevents an electrical short between the gate electrode and a contact structure that partially overlies the gate electrode by overlay variations during lithographic processes (Li et al, Abstract).
Regarding claim 4. Song et al, Liu et al, Chang et al, and Li et al discloses all the limitations of the semiconductor device of claim 3 above.
Song et al further discloses further comprising a gate capping pattern (FIG. 16, item GP) on a top surface ([0095], i.e. A capping pattern GP may be on each of the gate electrodes G1 and G2) of the first gate electrode (FIG. 16, item G2).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al (U.S. 2016/0005851), Liu et al (U.S. 2014/0302660) and Chang et al (U.S. 2017/0110569) as applied to claim 1 above, and further in view of Baek et al (U.S. 2013/0267088).
Regarding claim 14. Song et al, Liu et al, and Chang et al discloses all the limitations of the semiconductor device of claim 1 above.
Song et al further discloses the second portion and the first lower conductive structure.
Song et al further discloses wherein a width of the second portion is greater than a width of the first lower conductive structure.
However, Baek et al teaches wherein a width (FIG. 3, item W2) of the second portion (FIG. 3, item 57b) is greater ([0054], i.e. The upper conductive patterns 57b may have a width W2 greater than a width W1 of the lower conductive patterns 15a) than a width (FIG. 3, item W1) of the first lower conductive structure (FIG. 15a).
Since Song et al, Liu et al, Chang et al and Baek et al teach conductive structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor devices as disclosed to modify Song et al, Liu et al, Chang et al with the teachings of the wherein a width of the second portion is greater than a width of the first lower conductive structure as disclosed by Baek et al. The use of the upper conductive patterns may have a width greater than a width of the lower conductive patterns in Baek et al provides for an upper conductive patterns self-aligned with the lower conductive patterns (Baek et al, Abstract).
Claims 16, 18, 21, 22, 25, 26 and 28 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al (U.S. 2016/0005851), Liu et al (U.S. 2014/0302660), Kim et al (U.S. 2009/0212327) and Chang et al (U.S. 2017/0110569)
Regarding claim 16. Song et al discloses A semiconductor device (FIG. 3A to 3C, 16, 20; [0165]), comprising:
a substrate (FIG. 16, item 102);
wherein the first standard cell (FIG. 1, item C1) comprises:
a first fin-shaped structure (FIG. 16, item AP) including ([0096], i.e. Portions of the active patterns AP (e.g., portions of the active fins AF) that are disposed under and overlap the gate electrodes G1 and G2 may operate as channel regions) a first channel region (FIG. 16, item AF) and a first source/drain region (FIG. 16, item S/D) connected to the first channel region (FIG. 16, item AF);
a device isolation pattern (FIG. 20, item ST3) on a sidewall ([0090], i.e. third device isolation layers ST3 extend in the x-direction, and may be disposed at both sides of each active pattern AP) of a lower portion (FIG. 20, item 100) of the first fin-shaped structure (FIG. 20, item AP);
a first gate electrode (FIG. 16, item G2) on the first channel region (FIG. 16, item AF) of the first fin-shaped structure (FIG. 20, item AP); a first lower conductive structure (FIG. 16, item TS) electrically connected ([0154], i.e. conductive patterns TS may electrically connect the source/drain regions SD) to the first source/drain region (FIG. 16, item SD);
a first conductive structure (FIG. 15, item CC) on the first lower conductive structure (FIG. 16, item TS), the first conductive structure (FIG. 15, item CC) including a first portion (FIG. 16, item CB1) and a second portion (FIG. 16, item CA1) that are connected to each other ([0102], i.e. connecting contact CC may include first sub-contacts CA1 disposed at each side of the first gate electrode G1 and a second sub-contact CB1 connecting the first sub-contacts CA1 to each other) to constitute a single body (FIG. 16, item CC), the second portion (FIG. 16, item CA1) extending from the first portion (FIG. 16, item CB1) toward the first lower conductive structure (FIG. 16, item TS) and connected to the first lower conductive structure (FIG. 16, item TS).
wherein the first conductive structure (FIG. 15, item CC) further includes a vertically-extended portion (FIG. 16, item CB1) covering an upper sidewall (FIG. 16, sidewall of item TS) of the first lower conductive structure (FIG. 16, item TS),
a third portion (FIG. 16, item third portion) of the first conductive structure (FIG. 16, item CC) wherein the third portion (FIG. 16, item third portion) extends ([0141], i.e. The second sub-contact CB1 may be in contact with the top surface of the first gate electrode G1) from first portion (FIG. 16, item first portion) toward the first gate electrode (FIG. 16, item G1) and is connected to the first gate electrode (FIG. 16, item G1)
Song et al fails to explicitly disclose a first power interconnection line and a second power interconnection line; and a first standard cell between the first power interconnection line and the second power interconnection line,
an interconnection line on the first conductive structure; and
a via between the interconnection line and the first portion, and connecting the interconnection line and the first conductive structure,
a barrier pattern,
wherein the first conductive structure further includes a vertically-extended portion covering an upper sidewall of the first lower conductive structure, wherein the barrier pattern comprises a first barrier portion between the second portion of the first conductive structure and the first lower conductive structure, a second barrier portion between the first gate electrode and the third portion of the first conductive structure, and a third barrier portion on a sidewall of the vertically-extended portion of the first conductive structure, and wherein the vertically-extended portion is spaced apart from the first gate electrode, and wherein the first barrier portion, the second barrier portion, and the third barrier portion of the barrier pattern are formed conformally and configured to cover the first portion, the second portion, the third portion, and the vertically-extended portion of the first conductive structure.
However, Liu et al teaches an interconnection line (FIG. 4, item 120) on the first conductive structure (FIG. 4, item 110); and
a via (FIG. 4, item 116A) between the interconnection line (FIG. 4, item 120) and the first portion (FIG. 4, item 110), and connecting ([0018], i.e. a first contact formed over the protection diode (and optional trench silicide layer), a second contact formed over the RMG transistor, wherein the first contact extends to connect directly with the second contact, and a top metal layer (M1) formed over the first contact and the second contact) the interconnection line (FIG. 120) and the first conductive structure (FIG. 4, item 110).
Since Both Song et al and Liu et al teach conductive patterns with metal silicide, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Song et al with the teaches of the an interconnection line on the first conductive structure, and a via between the interconnection line and the first portion, and connecting the interconnection line and the first conductive structure as disclosed by Liu et al. The use of first contact formed over the protection diode (and optional trench silicide layer), a second contact formed over the RMG transistor, wherein the first contact extends to connect directly with the second contact, and a top metal layer (M1) formed over the first contact and the second contact in Liu et al provides for any charges accumulated during formation of the second contact and the set of vias will be discharged by the protection diode (Liu et al, Abstract).
Song et al and Liu et al fail to explicitly disclose a first power interconnection line and a second power interconnection line; and a first standard cell between the first power interconnection line and the second power interconnection line,
a barrier pattern wherein the first conductive structure further includes a vertically-extended portion covering an upper sidewall of the first lower conductive structure, wherein the barrier pattern comprises a first barrier portion between the second portion of the first conductive structure and the first lower conductive structure, a second barrier portion between the first gate electrode and the third portion of the first conductive structure, and a third barrier portion on a sidewall of the vertically-extended portion of the first conductive structure, and wherein the vertically-extended portion is spaced apart from the first gate electrode, and wherein the first barrier portion, the second barrier portion, and the third barrier portion of the barrier pattern are formed conformally and configured to cover the first portion, the second portion, the third portion, and the vertically-extended portion of the first conductive structure.
However, Kim et al (‘327) teaches a first power interconnection line (FIG. 1, item 10) and a second power interconnection line (FIG. 1, item 20);
and a standard cell (FIG. 1, item 40; [0038], i.e. the first standard cell 40 has a first cell height 15) between t(FIG. 1, shows item 40 is between item 10 and 20; [0068], i.e. a first standard cell of at least one cell having a first cell height and second standard cells of at least two cells having a second cell height different from the first cell height are arranged in contact with one another between first, second and third power rails) the first power interconnection line (FIG. 1, item 10) and the second power interconnection line (FIG. 1, item 20)
Since Song et al, Liu et al and Kim et al (‘327) teach interconnections, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Son et al and Liu et al with the teachings of a first power interconnection line and a second power interconnection line and a standard cell overlapped by the first power interconnection line and the second power interconnection line as disclosed by Kim et al (‘327). The use of a first standard cell of at least one cell having a first cell height and second standard cells of at least two cells having a second cell height different from the first cell height are arranged in contact with one another between first, second and third power rails in Kim et al (‘327) provides for improved routability in a highly integrated cell architecture (Kim et al (‘327), [0068]).
Song et al, Liu et al, and Kim et al (‘327) fail to explicitly disclose A barrier pattern wherein the first conductive structure further includes a vertically-extended portion covering an upper sidewall of the first lower conductive structure, wherein the barrier pattern comprises a first barrier portion between the second portion of the first conductive structure and the first lower conductive structure, a second barrier portion between the first gate electrode and the third portion of the first conductive structure, and a third barrier portion on a sidewall of the vertically-extended portion of the first conductive structure, and wherein the vertically-extended portion is spaced apart from the first gate electrode, wherein the first barrier portion, the second barrier portion, and the third barrier portion of the barrier pattern are formed conformally and configured to cover the first portion, the second portion, the third portion, and the vertically-extended portion of the first conductive structure.
However, Chang et al teaches A barrier pattern (FIG. 76, item 402), wherein the first conductive structure (FIG. 76, item 412) further includes a vertically-extended portion (FIG. 76, item 422b on right side of item 310) covering an upper sidewall (FIG. 76, upper sidewall of item 160) of the first lower conductive structure (FIG. 76, item 160),
wherein the barrier pattern (FIG. 76, item 402) comprises a first barrier portion (FIG. 76, item 402) between the second portion (FIG. 76, item 412 on right side of item 320) of the first conductive structure (FIG. 76, item 412) and the first lower conductive structure (FIG. 76, right side item 250), a second barrier portion (FIG. 76, item 402) between the first gate electrode (FIG. 76, left side item 250) and the third portion (FIG. 76, item 422 on left side of item 320) of the first conductive structure (FIG. 76, item 412), and a third barrier portion (FIG. 76, item 402) on a sidewall (FIG. 76, item 422b) of the vertically-extended portion (FIG. 76, item 422b on right side of item 310) of the first conductive structure (FIG. 76, right side item 250), and wherein the vertically-extended portion (FIG. 76, item 422b on right side of item 310) is spaced apart (FIG. 76, item 320) from the first gate electrode (FIG. 76, left side item 250), wherein the first barrier portion (FIG. 76, item 402), the second barrier portion (FIG. 76, item 402), and the third barrier portion (FIG. 76, item 402) of the barrier pattern (FIG. 76, item 402) are formed conformally ([0187]) and configured ([0187]) to cover ([0187]) the first portion (FIG. 76, item 412 above item 320), the second portion (FIG. 76, item 412 on right side of item 320), the third portion (FIG. 76, item 412 on left side of item 320), and the vertically-extended portion (FIG. 76, item 422b on right side of item 310) of the first conductive structure (FIG. 76, item 412).
Since Song et al, Liu et al, Kim et al (‘327) and Chang et al teach conductive structure, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor structure as disclosed to modify Song et al, Liu et al, and Kim et al (‘327) with the teachings of A barrier pattern wherein the first conductive structure further includes a vertically-extended portion covering an upper sidewall of the first lower conductive structure, wherein the barrier pattern comprises a first barrier portion between the second portion of the first conductive structure and the first lower conductive structure, a second barrier portion between the first gate electrode and the third portion of the first conductive structure, and a third barrier portion on a sidewall of the vertically-extended portion of the first conductive structure, and wherein the vertically-extended portion is spaced apart from the first gate electrode, wherein the first barrier portion, the second barrier portion, and the third barrier portion of the barrier pattern are formed conformally and configured to cover the first portion, the second portion, the third portion, and the vertically-extended portion of the first conductive structure as disclosed by Chang et al. The use of the first portion of the bottom (e.g., bottom surface) of the second contact plug may be formed in the first insulating interlayer so as to be higher than the upper surface of the gate structure, the second portions of the bottom (e.g., bottom surface) of the second contact plug may be formed in the insulation layer so as to be lower than the upper surface of the gate structure, and the third portion of the bottom of the second contact plug may contact the upper surface of the gate structure in Chang et al provides for the lowest surface of the convex portion of the bottom of the second contact plug, may not contact the upper surface of the substrate, and thus the electrical failure due to the leakage current from the contact plug to the substrate may be prevented (Chang et al, [0252]).
Regarding claim 18. Song et al, Liu et al, Kim et al (‘327), and Chang et al discloses all the limitations of the semiconductor device of claim 16 above.
Song et al further discloses wherein the first conductive structure (FIG. 16, item CC) further includes a third portion (FIG. 16, item third portion) extending ([0141], i.e. The second sub-contact CB1 may be in contact with the top surface of the first gate electrode G1) from first portion (FIG. 16, item first portion) toward the first gate electrode (FIG. 16, item G1) and connected to the first gate electrode (FIG. 16, item G1), and wherein the third portion (FIG. 16, item third portion) is provided ([0141], i.e. The second sub-contact CB1 may be in contact with the top surface of the first gate electrode G1; [0094], i.e. Gate electrodes G1 and G2 may be provided on the active patterns AP) on the first active pattern (FIG. 16, item AP).
PNG
media_image1.png
453
699
media_image1.png
Greyscale
Regarding claim 22. Song et al, Liu et al, Kim et al (‘327), and Chang et al discloses all the limitations of the semiconductor device of claim 16 above.
Chang et al further discloses wherein a bottom surface (FIG. 76, bottom surface of item 422b) of the vertically-extended portion (FIG. 76, item 422b) is lower ([0250]) than a top surface (FIG. 76, top surface of item 160) of the first lower conductive structure (FIG. 76, item 160).
Regarding claim 25. Song et al, Liu et al, Kim et al (‘327), and Chang et al discloses all the limitations of the semiconductor device of claim 16 above.
Song et al further discloses wherein a top surface of the first lower conductive structure (FIG. 16, item TS) is higher than top surface ([0119], i.e. top surfaces of the connecting conductive patterns TS may be higher than top surfaces of the gate electrodes G1 and G2) of the first gate electrode (FIG. 16, item G2).
Regarding claim 26. Song et al, Liu et al, Kim et al (‘327), and Chang et al discloses all the limitations of the semiconductor device of claim 16 above.
Song et al further discloses wherein a bottom surface (FIG. 16, bottom of item CA1) of the second portion (FIG. 1, item CA1) is higher than a top surface (FIG. 16, top surface of item G2 or G1) of the first gate electrode (FIG. 16, item G2 or G1).
PNG
media_image4.png
439
878
media_image4.png
Greyscale
Regarding claim 28. Song et al, Liu et al, Kim et al (‘327), and Chang et al discloses all the limitations of the semiconductor device of claim 16 above.
Song et al further discloses wherein the first portion (FIG. 16, item CB1) has a flat plate structure ([0010], i.e. each of the first sub-contacts may have a bar shape extending in the first direction).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al (U.S. 2016/0005851), Liu et al (U.S. 2014/0302660), Kim et al (U.S. 2009/0212327) and Chang et al (U.S. 2017/0110569), as applied to claim 16 above, and further in view of Lu et al (U.S. 2014/0183647)
Regarding claim 17. Song et al, Liu et al, Kim et al (‘327) and Chang et al discloses all the limitations of the semiconductor device of claim 16 above.
Song et al further discloses further comprising: a second standard cell (FIG. 1, item C2) and a dummy electrode (FIG. 1, item G1; [0101], i.e. the first gate electrode may be a dummy gate electrode)
Kim et al (‘327) a second standard cell (FIG. 1, item 50) between the first power interconnection line (FIG. 1, item 10) and the second power interconnection line (FIG. 1, item 20);
Song et al and Kim et al (‘327) fail to explicitly disclose the dummy gate electrode on a boundary between the first second standard cell and the second standard cell, wherein the first portion extends from the first standard cell to the second standard cell across the dummy gate electrode.
However, Lu et al teaches the dummy gate electrode (FIG. 3, item 116; [0027], i.e. separate upper and lower portions of the dummy gate strip 116; [0022], i.e. drain regions 114b and 120b of cell 100 are disposed to the left of the dummy gate strip 116, and source regions 114a and 120a of cell 130 are disposed to the right of the dummy gate strip 116) on a boundary between the first standard cell (FIG. 3, item 100) and the second standard cell (FIG. 3, item 130), wherein the first portion (FIG. 3, item Poly Metal VDD) extends from the first standard cell (FIG. 3, item 100) to the second standard cell (FIG. 3, item 130) across the dummy gate electrode (FIG. 3, item 116).
Since Both Song et al and Lu et al teach standard cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed in Song et al with the dummy gate electrode on a boundary between the first second standard cell and the second standard cell, wherein the first portion extends from the first standard cell to the second standard cell across the dummy gate electrode as disclosed by Lu et al. The use of drain regions of cell 100 are disposed to the left of the dummy gate strip, and source regions of cell 130 are disposed to the right of the dummy gate strip in Lu et al provides for improved performance and reduced process variation as a result of a long, continuous OD region in comparison with a shorter, discrete OD region (Lu et al, [0022]).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al (U.S. 2016/0005851), Liu et al (U.S. 2014/0302660), Kim et al (U.S. 2009/0212327) and Chang et al (U.S. 2017/0110569) as applied to claim 16 above, and further in view of Baek et al (U.S. 2013/0267088).
Regarding claim 27. Song et al, Liu et al, Kim et al (‘327) and Chang et al discloses all the limitations of the semiconductor device of claim 16 above.
Song et al further discloses the second portion and the first lower conductive structure.
Song et al further discloses wherein a width of the second portion is greater than a width of the first lower conductive structure.
However, Baek et al teaches wherein a width (FIG. 3, item W2) of the second portion (FIG. 3, item 57b) is greater ([0054], i.e. The upper conductive patterns 57b may have a width W2 greater than a width W1 of the lower conductive patterns 15a) than a width (FIG. 3, item W1) of the first lower conductive structure (FIG. 15a).
Since Both Song et al and Baek et al teach conductive structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor devices as disclosed in Song et al with the wherein a width of the second portion is greater than a width of the first lower conductive structure as disclosed by Baek et al. The use of the upper conductive patterns may have a width greater than a width of the lower conductive patterns in Baek et al provides for an upper conductive patterns self-aligned with the lower conductive patterns (Baek et al, Abstract).
Response to Arguments
Applicant's arguments filed December 24, 2025 have been fully considered but they are not persuasive.
Regarding 103 rejection of claims 1, 2, 5, 8, 9, 12, 13, and 15 and 103 rejection of claims 16, 18, 21, 22, 25, 26, and 28.
On page 12 of applicant’s remarks, applicant appears to argue that Song, Liu, Yu, Kim 327, Kim 817 fails to disclose the barrier pattern which enclosed the first conductive structure and the vertically extended portion.
Examiner respectfully points out that Chang et al teaches applicant’s amended claim limitation for claims 1 and 16. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Madhavan et al (U.S. 2020/0105672) discloses Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication.
Maki (U.S. 2015/0076612) discloses semiconductor device.
Liaw (U.S. 8,952,547) discloses semiconductor device with contact structures with first/second contacts formed in first/second dielectric layers and methods of forming same.
Kim et al (U.S. 2014/0367825) discloses semiconductor devices including empty spaces and methods of forming the same.
Cho et al (U.S. 2011/0183512) discloses method of forming semiconductor device having contact plug.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
Prosecution Insights