DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US Pub no. 2011/0042797 A1)
Regarding claim 19, Park et al discloses A semiconductor package comprising:
an under bump interconnection layer(105a/105b/110)[0079]; an electronic device (150)mounted on the under bump interconnection layer(105a/105b/110)[0079]; and a solder bump (310)disposed on the under bump interconnection layer (105a/105b/110)and horizontally spaced apart from the electronic device(150)[0125] fig. 19, wherein the under bump interconnection layer(105a/105b/110) comprises: conductive patterns(105a/105b) connected to the electronic device (150)and the solder bump(310); and a passivation layer (110)covering the conductive patterns(105a/105b), wherein the passivation layer (110)includes a plurality of trenches (part of 110b-see fig. 2c)disposed between the electronic device (150)and the solder bump,(301) wherein the electronic device(150) is spaced apart from the solder bump (301)by a first distance(fig. 2b/fig. 19), wherein the plurality of trenches(part of 110b -fig. 2c) is located within a second distance from the solder bump(301) fig. 2b-2c/fig. 19, and the second distance is half of the first distance(the start of region B is half way, therefore, part of 110b is half the distance fig. 2b/2c/fig. 19).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-9 & 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen US Pub no 2017/0194226 A1) in view of Park (US Pub no. 2011/0042797 A1).
Regarding claim 1, Chen et al discloses a semiconductor package (fig. 10) comprising: a redistribution substrate (819)having a first surface and a second surface which are opposite to each other[0087]; a semiconductor chip(807) mounted on the first surface of the redistribution substrate(819) fig. 10[0060]; an under bump interconnection layer (110/821)on the second surface of the redistribution substrate(819)[0090] fig. 10; an electronic device(203) mounted on the under bump interconnection layer(110) fig. 10; and a solder bump (201)disposed on the under bump interconnection layer (110/821)and horizontally spaced apart from the electronic device(203)[0054][0090] fig. 10, wherein the under bump interconnection layer (110)comprises: conductive patterns (821)respectively connected to the electronic device(203) and the solder bump[0091][0031]; and a passivation layer(801) covering the conductive patterns(821)[0091].
Chen et al discloses wherein the passivation layer(801) includes a trench (829) but fails to teach wherein the passivation layer includes a plurality of trenches disposed between the electronic device and the solder bump, wherein the plurality of trenches includes: a first trench closest to the solder bump among the plurality of trenches; and a second trench farthest from the solder bump among the plurality of trenches, and
wherein the second trench is closer to the solder bump than it is to the electronic
device, and the first trench is disposed between the solder bump and the second trench.
However, Park et al teaches a semiconductor package structure where the insulating layer 110 includes a plurality of trenches (110b)disposed between the electronic device(150) and the solder bump(310)[0080]fig. 2c/fig.19, wherein the plurality of trenches(110b/110a) includes: a first trench closest to the solder bump(310) among the plurality of trenches(110b/110a); and a second trench(trench closest to region A) farthest from the solder bump (310-fig. 19)among the plurality of trenches(110b)(examiner notes solder bump 310 illustrated in fig. 19 resides on second connection terminal 105b disposed in second region B[0125]), and
wherein the second trench is closer to the solder bump(310) than it is to the electronic
device(150) fig. 2b/2c, and the first trench(closest to 105b in region B) is disposed between the solder bump (310)and the second trench(trench closest to region A) fig.2b/ 2c , fig. 19. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Chen et al with the teachings of Park et al to prevent underfill from flowing out from a semiconductor chip and to thereby reduce a size of the semiconductor package .
Regarding claim 2, Chen et al discloses wherein a trench (829) extends from a first surface of a passivation layer(801) into the passivation layer and toward a second surface of the passivation layer(801)facing the redistribution substrate (819)fig. 10 but fails to teach a plurality of trenches .
However, Park et al teaches a semiconductor package structure including a plurality of trenches (110b)disposed between the electronic device(150) and the solder bump(310)[0029] fig.2b/ 2c , fig. 19. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Chen et al with the teachings of Park et al to prevent underfill from flowing out from a semiconductor chip and to thereby reduce a size of the semiconductor package.
Regarding claim 3, Chen et al discloses further comprising: an underfill layer (205) between the under bump interconnection layer (110/821)and the electronic device(203)[0098] but fails wherein the underfill layer extends onto the first surface of the passivation layer and fills at least a portion of the plurality of trenches.
However, Park et al discloses wherein the underfill layer(160) extends onto the first surface of an insulation layer (110) and fills at least a portion of the plurality of trenches(110a of 110a & 110b)[0079]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Chen et al with the teachings of Park et al to prevent underfill from flowing out from a semiconductor chip and to thereby reduce a size of the semiconductor package.
Regarding claim 5, Park e al discloses wherein the electronic device (150)is spaced apart from the solder bump (301)by a first distance fig. 2b/fig. 19, wherein the plurality of trenches(110a/110b) is located within a second distance from the solder bump(301), and the second distance is half of the first distance(in portion ’P’ the trench portions of 110b start at half of the distance of the distance) fig 2b /2c .
Regarding claim 6, Park et al teaches wherein each trench of the plurality of trenches(110b/110a) has a maximum width in a direction parallel to a top surface of the
passivation layer(110)[0085][0087][0095] but fails to teach wherein the width of each of the plurality of trenches is a width in a range from 25µm to 100µm.It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to achieve a width in a range from 25µm to 100µm through routine experimentation to optimize the width to influence the blockage of the underfill. [W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding claim 7, Park et al discloses wherein a distance between a pair of adjacent trenches(110a/110b) of the plurality of trenches fig. 2c but fails to teach is in a range from 25µm to 100µm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to achieve a width in a range from 25µm to 100µm through routine experimentation to overflow prevention. [W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) .
Regarding claim 8, Park et al discloses wherein the solder bump is one of a plurality of solder bumps(310) (fig. 19), wherein the solder bumps(310) are arranged to surround the electronic device(150) when viewed in a plan view(fig. 19/fig.1/fig. 14), and wherein the plurality of trenches(110a/110B) is disposed between the plurality of solder bumps(310) and the electronic device(150) (fig. 19/fig.1/fig. 14).
Regarding claim 9, Park et al discloses wherein the electronic device(150) has a first side surface and a second side surface, which are opposite to each other in a first direction parallel to a top surface of the passivation layer(110), wherein the plurality of trenches(110a/110b) includes: a first group of trenches (110a)disposed between the
first side surface of the electronic device(150) and corresponding solder bumps(310) of the plurality of solder bumps(310); and a second group of trenches(110b) disposed between the second side surface of the electronic device(150) and corresponding solder bumps(310) of the plurality of solder bumps, and wherein each of the first group of trenches (110a)and the second group of trenches (110B)has a line shape extending in a second direction which is parallel to the top surface of the passivation layer(110)
and intersects the first direction fig. 1,2b,2c, fig. 19.
Regarding claim 11, Park et al discloses wherein each of the plurality of trenches(110a/110b) has a ring shape(located region A &B) surrounding the electronic device(150), when viewed in a plan view(fig. 14 or fig. 1)
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen US Pub no 2017/0194226 A1) in view of Park (US Pub no. 2011/0042797 A1) as applied to claim 9 and further in view of Chou (US Pub no. 2016/0315067 A1)
Regarding claim 10, Chen et al as modified by Park et al discloses all the claim limitations of claim 9 but fails to teach wherein the electronic device has a third side surface and a fourth side surface, which are opposite to each other in the second direction, wherein the plurality of trenches includes: a third group of trenches disposed
between the third side surface of the electronic device and corresponding solder bumps of the plurality of solder bumps; and a fourth group of trenches disposed between the fourth side surface of the electronic device and corresponding solder bumps of the plurality of solder bumps, and wherein the third group of trenches and the fourth group of trenches have line shapes extending in the first direction.
However, Chou et al wherein the electronic device(140)
has a third side surface and a fourth side surface fig. 2 or [0032], which are opposite to each other in the second direction fig. 2 or [0032], wherein the plurality of trenches(186a/186b) includes: a third group of trenches disposed between the third side surface of the electronic device(140) and corresponding solder bumps (130)of
the plurality of solder bumps; and a fourth group of trenches(186a/186b) disposed between the fourth side surface of the electronic device(140) and corresponding solder bumps(130) of the plurality of solder bumps, and wherein the third group of trenches (186a/186b)and the fourth group of trenches(186a/186b) have line shapes extending in the first direction fig. 2 or [0032](Examiner notes that the blocking structure 120 which are formed by elements (186a/186b) can be discrete structures therefore each side of the electronic device will have plurality of trenches). Since using discrete structures to form a third and fourth group of trenches is one of finite solutions to prevent underfill from flowing towards the conductive bump as taught by Chou et al, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to try in Chen et al & Park et al since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense (KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007))
Claim(s) 14 & 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen US Pub no 2017/0194226 A1) in view of Park (US Pub no. 2011/0042797 A1) as applied to claim 1 and further in view of Wu (US Pub no. 2021/0098421 A1).
Regarding claim 14, Chen et al as modified by Park et al discloses all the claim limitations of claim 1 but fails to teach redistribution substrate comprises: a first redistribution layer adjacent to the first surface of the redistribution substrate; a second redistribution layer adjacent to the second surface of the redistribution substrate; and a core substrate between the first redistribution layer and the second redistribution layer, wherein the core substrate electrically connects the first redistribution layer and the second redistribution layer to each other.
However, Wu et al discloses redistribution substrate comprises: a first redistribution layer adjacent to the first surface of the redistribution substrate; a second redistribution layer adjacent to the second surface of the redistribution substrate; and a core substrate between the first redistribution layer and the second redistribution layer, wherein the core substrate electrically connects the first redistribution layer and the second redistribution layer to each other. the redistribution substrate(T1) comprises: a first redistribution layer (110)adjacent to the first surface of the redistribution substrate(T1); a second redistribution layer (150)adjacent to the second surface of the redistribution substrate(T1); and a core substrate (140)between the first redistribution layer(110) and the second redistribution layer(150), wherein the core substrate(140) electrically connects the first redistribution layer(110) and the second redistribution layer(150) to each other[0049]. It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Chen et al & Park et al with the teachings of Wu et al to improve integration of the device.
Regarding claim 15, Chen et al as modified by Park et al discloses wherein the semiconductor chip is electrically connected to the conductive patterns in the under bump interconnection layer but fails to teach wherein the semiconductor chip is electrically connected to first redistribution patterns in the first redistribution layer, and
wherein the conductive patterns in the under bump interconnection layer are electrically connected to second redistribution patterns in the second redistribution layer.
Wu et al discloses wherein the semiconductor chip(130) is electrically connected to first redistribution patterns(112) in the first redistribution layer(110), and wherein the conductive patterns (152t) in the under bump interconnection layer (upper part of 150)[0036]are electrically connected to second redistribution patterns(152) in the second redistribution layer(150-lower part)[0033]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Chen et al & Park et al with the teachings of Wu et al to improve integration of the device
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou (US Pub no. 2016/0315067 A1) in view of Park (US Pub no. 2011/0042797 A1).
Regarding claim 16, Chou et al discloses a semiconductor package (fig.1/fig. 2)comprising: an under bump interconnection layer(170); an electronic device (140)mounted on the under bump interconnection layer(170); and a plurality of solder bumps (130)arranged to surround the electronic device (140)on the under bump interconnection layer(170)[0026], wherein the under bump interconnection layer(170) comprises: conductive patterns (170)respectively connected to the electronic device (140)and the plurality of solder bumps(130)([0024]-electrically connected); and a passivation layer (180)covering the conductive patterns(170), wherein the electronic device(140) has a first side surface and a second side surface, which are opposite to each other in a first direction parallel to a top surface of the passivation layer(180), wherein the passivation layer includes: a first group of trenches(186a/186b) disposed between the first side surface of the electronic device (140)and corresponding solder bumps(130) of the plurality of solder bumps(130)[0029]; and a second group of trenches(186a/186b) disposed between the second side surface of the electronic device(140) and corresponding solder bumps (130)of the plurality of solder bumps, and wherein each trench(168a/168b) of the first group of trenches and the second group of trenches(186a/186b) has a line shape extending in a second direction which is parallel to the top surface of the passivation layer(160) and intersects the first direction fig. 1/fig. 2.
Chou et al fails to teach wherein the electronic device is spaced apart from the first solder bumps by a first distance, and wherein the first group of trenches is located within a second distance from the first solder bumps, and the second distance is half of the first distance.
However Park et al teaches wherein tan electronic device (150) is spaced apart from the first solder bumps(301) by a first distance fig. 19/ fig. 2b/fig. 2c, and wherein the first group of trenches(110b) is located within a second distance from the first solder bumps(301), and the second distance is half of the first distance(in portion ’P’ the trench portions of 110b start at half of the distance of the distance) fig 2b /2c. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Chou et al with the teachings of Park et al to prevent underfill from flowing out from a semiconductor chip and to thereby reduce a size of the semiconductor package.
Regarding claim 17, Chou et al discloses wherein the electronic device(140) has a third side surface and a fourth side surface fig. 2 or [0032], which are opposite to each other in the second direction fig. 2 or [0032], wherein the passivation layer(180) includes: a third group of trenches(186a/186b) disposed between the third side surface of the electronic device(140) and corresponding solder bumps(130) of the plurality of solder bumps; and a fourth group of trenches disposed between the fourth side surface of the electronic device and corresponding solder bumps of the plurality of solder bumps(130), and wherein each trench(186a/186b) of the third group of trenches and the fourth group of trenches has a line shape extending in the first direction fig. 2 or [0032](Examiner notes that the blocking structure 120 which are formed by elements (186a/186b) can be discrete structures therefore each side of the electronic device will have plurality of trenches).
Regarding claim 18, Chou et al discloses wherein one trench(186a or 186b) of the first group of trenches(186a/186b), one trench (186a or 186b) of the second group of trenches, one trench (186a or 186b) of the third group of trenches and one trench (186a or 186b) of the fourth group of trenches are connected to each other to constitute a continuous ring shape surrounding the first to fourth side surfaces of the electronic device fig.2 or [0032].
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US Pub no. 2011/0042797 A1).
Regarding claim 20, Park et al discloses all the claim limitations of claim 19 and further teaches wherein each trench of the plurality of trenches(110b/110a) has a maximum width in a direction parallel to a top surface of the passivation layer(110)[0085][0087][0095] but fails to teach wherein the width of each of the plurality of trenches is a width in a range from 25µm to 100µm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to achieve a width in a range from 25µm to 100µm through routine experimentation to optimize the width to influence the blockage of the underfill. [W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Conclusion
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/LATANYA N CRAWFORD EASON/ Primary Examiner, Art Unit 2813
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