DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, claims 1-8 in the reply filed on 12/08/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 03/22/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hasse et al. (US 2014/0075748 A1).
Pertaining to claim 1, Hasse et al. discloses An apparatus (see paragraph [0030]) comprising: a circuit board (see paragraph [0031], lines 14-18) comprising a plurality of layers (604, 606 and 965, see figs. 6 and 9) and at least one conductive connection (see paragraph [0033]), wherein: the at least one conductive connection is connected to a layer of the plurality of layers; at least one layer of the plurality of layers (604, 606 and 965) comprises a conductive material (see paragraph [0035], the at least two layers of the plurality of layers comprise conductive material that extend in an axis towards the at least one conductive connection (810, see fig. 8B) but do not overlap with the at least one layer of the plurality of layers comprising the conductive material (see figs. 8-9).
Pertaining to claim 2, Hasse et al. discloses, wherein the at least one conductive connection (see paragraph [0033]) comprises at least one gold finger (810, see fig. 8B).
Pertaining to claim 3, Hasse et al. discloses, wherein the conductive material comprises signal plane (see paragraph [0039]), lines 3-7).
Pertaining to claim 4, Hasse et al. discloses, wherein the conductive material comprises one or more of: copper (see paragraph [0035]).
Pertaining to claim 5, Hasse et al. discloses, comprising at least one surface mounted (SMT) connector coupled to the at least one conductive connection (see paragraph [0044], lines 12-15).
Pertaining to claim 6, Hasse et al. discloses, wherein the circuit board comprises a dual in- line memory module (DIMM) (see paragraph [0044], lines 12-15).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Hasse et al. (US 2014/0075748 A1) in view of Galbi et al. (US 2020/0125495 A1).
Pertaining to claim 7, Hasse et al. discloses all claimed limitations except, wherein an arrangement of the at least one conductive connection is consistent with Joint Electronic Device Engineering Council Double Data Rate version 5 (DDR5).
However, Galbi et al. teaches wherein an arrangement of the at least one conductive connection is consistent with Joint Electronic Device Engineering Council Double Data Rate version 5 (DDR5), (see paragraph [0012]).
Therefore, At the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to provide wherein an arrangement of the at least one conductive connection is consistent with Joint Electronic Device Engineering Council Double Data Rate version 5 (DDR5) in the device of Hasse et al. in order to improved power efficiency, enhanced signal integrity, and higher reliability, driven by 1.1V operation and on-DIMM Power Management Integrated Circuits (PMIC).
Pertaining to claim 8, Hasse et al. discloses all claimed limitations except, further comprising a first device coupled to the circuit board, wherein the first device comprises a surface mounted (SMT) connector of a motherboard, a motherboard, (see paragraph [0044], lines 12-15).
But, Hasse et al. does not explicitly teach one or more of: central processing unit (CPU), XPU, accelerator, and/or graphics processing unit (GPU).
However, Galbi et al. teaches one or more of: central processing unit (CPU), XPU, accelerator, and/or graphics processing unit (GPU), (see paragraph [0064]
Therefore, At the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to provide one or more of: central processing unit (CPU), XPU, accelerator, and/or graphics processing unit (GPU) in the device of Hasse et al. in order to improved power efficiency, enhanced signal integrity, and higher reliability, driven by 1.1V operation and on-DIMM Power Management Integrated Circuits (PMIC) and generate graphics information.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Takata (US 20230047382 A1), Liao et al. (US 20200403330 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDARGIE M AYCHILLHUM whose telephone number is (571)270-1607. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANDARGIE M AYCHILLHUM/Primary Examiner, Art Unit 2848
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