Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/24/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2 and 4-12 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claim 1 recites “the common thickness range providing a desired electrical performance to the die stack”. The specification only says in para. 0003 that a memory die with too little a thickness can degrade prematurely and leak applied power supply current. There is no indication of at what thickness this begins to occur. Furthermore. there is no indication of what is meant by die thickness: if it is an average or a lowest value. There is also no mention of die thickness uniformity or what happens with dies having thicknesses that are considered large. It is mentioned that grinding processes can cause variations of thickness across the wafer but one could reasonably expect variations between different die as well as variations along the same die. The meets and bounds of the thicknesses and the performance of the die are not clearly established, such that one of ordinary skill in the art would not be able to form the claimed semiconductor device.
Claims 2 and 4-12 are rejected based on their dependency on claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2 and 4-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites each semiconductor die in the die stack has a thickness within a common thickness range defined by a thickness category of a known thickness die (KTD) map. The meets and bounds of the range in the KTD are not clear, rendering the limitation indefinite. Furthermore, a KTD is an abstract idea, not a manufacture or a process, and choosing die in the KTD map for a desired electrical performance merely implies a die stack with a desired electrical performance.
The claim further recites the common thickness range providing a desired electrical performance to the die stack. The claim fails to establish a reference or a range as to what is the desired performance. The meets and bounds of the electrical performance are not clear.
Claims 2 and 4-12 are rejected based on their dependency on claim 1.
Claims 13-15 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the “semiconductor dies having silicon substrate layers of substantially the same thickness based on a known die thickness (KTD) map of silicon substrate layer thicknesses and based on an overall desired thickness of the die stack; wherein the plurality of semiconductor dies are selected using the KTD map, the KTD map including thicknesses of the plurality of semiconductor dies”. The meets and bounds of the range in the KTD are not clear, rendering the limitation indefinite. Furthermore, a KTD is an abstract idea, not a manufacture or a process, and choosing die in the KTD map for a desired height merely implies a die stack with a desired height.
Claims 14-15 and 17 are rejected based on their dependency on claim 13.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the die stack is configured to include semiconductor dies comprising silicon substrate layers that are within 1.0 microns of each other. Meanwhile, claim 13 recites the die stack configured to include semiconductor dies having silicon substrate layers of substantially the same thickness. It appears contradictory so claim the die have substantially similar thicknesses but to also be as much as 1 micron different in thickness.
Claim 15 is rejected based on its dependency on claim 14.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites a thickness within a common thickness range defined by a thickness category of a known thickness die (KTD) map. The meets and bounds of the range in the KTD are not clear, rendering the limitation indefinite. Furthermore, a KTD is an abstract idea, not a manufacture or a process, and choosing die in the KTD map for a desired electrical performance merely implies a die stack with a desired electrical performance.
Response to Arguments
Applicant's arguments filed 2/6/2026 have been fully considered but they are not persuasive. Applicant alleges that Han fails to teach or render obvious wherein each semiconductor die in the die stack has a thickness within a common thickness range defined by a thickness category of a known thickness die (KTD) map, the common thickness range providing a desired electrical performance to the die stack. The claims are directed to a semiconductor device comprising a die stack, which is a product. The means of forming the product hold no patentable weight unless they impart a structural characteristic to the product, as asserted in MPEP 2113. In the case of the KTD map, it only serves to say where the die of substantially similar thicknesses came from: that the selected die are within a common thickness range. Han teaches that the die have a same thickness and they are stacked to form a semiconductor device as claimed. This is understood as the die in Han being within a common thickness range. The final stack is understood to have a performance as desired by Han. The previous rejections to the claims are sustained.
Claim Rejections - 35 USC § 102/103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AlA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a}(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 4-6 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Han US 20190259743 A1 (hereinafter referred to as Han).
Regarding claim 1, Han teaches
A semiconductor device (“first discrete semiconductor package 11” para. 0055 FIG. 8), comprising:
a substrate (“base die 100D” made from “base die wafer 100”, para. 0054-0055 FIG. 7-8); and
a die stack (“first stack structure 208” para. 0055) mounted on the substrate, the die stack comprising a plurality of semiconductor dies (“core dies 200” para. 0055), each semiconductor die in the die stack has a thickness within a common thickness range defined by a thickness category of a known thickness die (KTD) map, (from “core dies 200 may be semiconductor dies having substantially the same size. For example, each of the core dies 200 may have the same thickness T2” in para. 0035, the examiner understands that the thicknesses of different “core dies 200” are known and those with the substantially same thickness are chosen), the common thickness range providing a desired electrical performance to the die stack (since “core dies 200” have integrated circuitry and perform DRAM functions as stated in para. 0035-0036, it is understood they contribute to the performance of the “first stack structure 208” as desired).
However, Han fails to teach a common thickness range defined by a thickness category of a known thickness die (KTD) map, the common thickness range providing a desired electrical performance to the die stack.
Nevertheless, the language, term, or phrase "a common thickness range defined by a thickness category of a known thickness die (KTD) map, the common thickness range providing a desired electrical performance to the die stack" is directed towards the process of making “A semiconductor device comprising: a substrate and a die stack mounted on the substrate, the die stack comprising a plurality of semiconductor dies, wherein each semiconductor die in the die stack has a thickness within a common thickness range”. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "a common thickness range defined by a thickness category of a known thickness die (KTD) map, the common thickness range providing a desired electrical performance to the die stack" only requires a die stack with dies having similar thickness, which does not distinguish the invention from Han, who teaches the structure as claimed.
Regarding claim 4, Han teaches the semiconductor device of claim 1 but fails to teach wherein the KTD map categorizes thicknesses of semiconductor dies of the second plurality of semiconductor dies by categorizing the second plurality of semiconductor dies into binning categories comprising at least binning categories 1, 2 and 3.
Nevertheless, the language, term, or phrase "wherein the KTD map categorizes thicknesses of semiconductor dies of the second plurality of semiconductor dies by categorizing the second plurality of semiconductor dies into binning categories comprising at least binning categories 1, 2 and 3” is directed towards the process of making “the semiconductor device of claim 1”. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "wherein the KTD map categorizes thicknesses of semiconductor dies of the second plurality of semiconductor dies by categorizing the second plurality of semiconductor dies into binning categories comprising at least binning categories 1, 2 and 3" only requires a die stack with dies having similar thickness, which does not distinguish the invention from Han, who teaches the structure as claimed.
Regarding claim 5, Han teaches the semiconductor device of claim 1 but fails to teach wherein the first plurality of semiconductor dies are all selected from binning category 1.
Nevertheless, the language, term, or phrase “wherein the first plurality of semiconductor dies are all selected from binning category 1” is directed towards the process of making “the semiconductor device of claim 1”. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language " wherein the first plurality of semiconductor dies are all selected from binning category 1" only requires a die stack with dies having similar thickness, which does not distinguish the invention from Han, who teaches the structure as claimed.
Regarding claim 6, Han teaches the semiconductor device of claim 1 but fails to teach wherein the first plurality of semiconductor dies are all selected from binning categories 1 and 2.
Nevertheless, the language, term, or phrase “wherein the first plurality of semiconductor dies are all selected from binning categories 1 and 2” is directed towards the process of making “the semiconductor device of claim 1”. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language " wherein the first plurality of semiconductor dies are all selected from binning categories 1 and 2" only requires a die stack with dies having similar thickness, which does not distinguish the invention from Han, who teaches the structure as claimed.
Regarding claim 8, Han teaches the semiconductor device of claim 1 but fails to teach wherein the first plurality of semiconductor dies are all selected from semiconductor dies of the second plurality of semiconductor dies having layers above a predefined thickness.
Nevertheless, the language, term, or phrase “wherein the first plurality of semiconductor dies are all selected from semiconductor dies of the second plurality of semiconductor dies having layers above a predefined thickness” is directed towards the process of making “the semiconductor device of claim 1”. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "wherein the first plurality of semiconductor dies are all selected from semiconductor dies of the second plurality of semiconductor dies having layers above a predefined thickness" only requires a die stack with dies having similar thickness, which does not distinguish the invention from Han, who teaches the structure as claimed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Han as applied to claim 1 above, in view of Jo et al. CN 104637901 A (hereinafter referred to as Jo).
Regarding claim 2, Han teaches the semiconductor device of claim 1 but fails to teach wherein the plurality of semiconductor dies comprise silicon substrate layers over which integrated circuit layers are formed, and wherein the silicon substrate layers of the plurality of semiconductor dies are configured to have substantially the same thickness silicon substrate layers based on a known thickness map of the silicon substrate layer thicknesses of the plurality of semiconductor dies.
Nevertheless, Jo teaches
wherein the plurality of semiconductor dies (“first to fourth semiconductor chips (100, 200, 300, 400)” [0063] FIG. 1A) comprise silicon substrate layers (“first substrate 101”, “second substrate 201”, third substrate 301”, and “fourth substrate 401” are silicon wafer material, [0066-0071]) over which integrated circuit layers are formed (on each silicon wafer, “first integrated circuit 103”, “second integrated circuit 203”, “third integrated circuit 303”, and “fourth integrated circuit 403” are formed [0066-0071]), and wherein the silicon substrate layers of the plurality of semiconductor dies are configured to have substantially the same thickness silicon substrate layers based on a known thickness map of the silicon substrate layer thicknesses of the plurality of semiconductor dies (since “first to fourth semiconductor chips (100, 200, 300 and 400) may have the same thickness” and can be the same chips such as memory chips [0064 and 0073], the circuitry on them and thickness of their silicon wafer base are understood to be substantially the same.)
Han and Jo teach stacked chip structures. The chips in Jo comprise integrated circuitry formed on silicon wafers. Silicon is a known semiconductor material widely used in chip manufacturing for its versatility and ease of use. Jo teaches that different thinning and texturing processes can be done to the silicon wafers (see [0110]). If “first to fourth semiconductor chips (100, 200, 300, 400)” are the same type of memory chip and are the same thickness, it is understood that the thickness of the circuitry and the base silicon wafer material are the same for each chip. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the silicon wafer substrate of each semiconductor chip in Jo has the same thickness if each chip is the same and of same total thickness. The processes for achieving this with silicon as the substrate material are well known.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Han with the silicon substrate layers taught in Jo. Silicon is a widely used wafer material upon which circuitry can be made. When the semiconductor dies of the same kind are of the same thickness, their silicon substrate layers are of the same thickness.
Regarding claim 7, Han teaches the semiconductor device of claim 1 but fails to teach wherein the second plurality of semiconductor dies comprise silicon substrate layers on which are formed integrated circuit layers, and wherein the KTD map includes thicknesses of the silicon substrate layers of the second plurality of semiconductor dies from the wafer.
Nevertheless, Jo teaches
wherein the second plurality of semiconductor dies (“first to fourth semiconductor chips (100, 200, 300, 400)” [0063] FIG. 1A) comprise silicon substrate layers (“first substrate 101”, “second substrate 201”, third substrate 301”, and “fourth substrate 401” are silicon wafer material, [0066-0071]) on which are formed integrated circuit layers (on each silicon wafer, “first integrated circuit 103”, “second integrated circuit 203”, “third integrated circuit 303”, and “fourth integrated circuit 403” are formed [0066-0071]), and wherein the KTD map includes thicknesses of the silicon substrate layers of the second plurality of semiconductor dies from the wafer (since “first to fourth semiconductor chips (100, 200, 300 and 400) may have the same thickness” and can be the same chips such as memory chips [0064 and 0073], the circuitry on them and thickness of their silicon wafer base are understood to be known).
Han and Jo teach stacked chip structures. The chips in Jo comprise integrated circuitry formed on silicon wafers. Silicon is a known semiconductor material widely used in chip manufacturing for its versatility and ease of use. If “first to fourth semiconductor chips (100, 200, 300, 400)” are the same type of memory chip and are the same thickness, it is understood that the thickness of the circuitry and the base silicon wafer material are the same for each chip. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the silicon wafer substrate of each semiconductor chip in Jo has the same thickness if each chip is the same and of same total thickness.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Han with the silicon substrate layers taught in Jo. Silicon is a widely used wafer material upon which circuitry can be made. Semiconductor dies with silicon substrate layers can be made of the thickness.
Regarding claim 8, Han, modified by Jo, teach the semiconductor device of claim 7 but fails to teach wherein the first plurality of semiconductor dies are all selected based on from semiconductor dies of the second plurality of semiconductor dies having silicon substrate layers above a predefined thickness.
Nevertheless, the language, term, or phrase “wherein the first plurality of semiconductor dies are all selected based on from semiconductor dies of the second plurality of semiconductor dies having silicon substrate layers above a predefined thickness” is directed towards the process of making “the semiconductor device of claim 7”. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "wherein the first plurality of semiconductor dies are all selected based on from semiconductor dies of the second plurality of semiconductor dies having silicon substrate layers above a predefined thickness" only requires a die stack with dies having a particular thickness, which does not distinguish the invention from Han, who teaches the structure as claimed.
Claims 9, 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Han as applied to claim 1 above, in view of Shimizu et al. US 20160276312 A1 (hereinafter referred to as Shimizu).
Regarding claim 9, Han teaches the semiconductor device of claim 1 but fails to teach wherein the first plurality of semiconductor dies comprise one of eight memory dies and sixteen memory dies.
Nevertheless, Shimizu teaches
wherein the first plurality of semiconductor dies (“second semiconductor chips 70a to 70h” para. 0021 FIG. 3) comprise one of eight memory dies and sixteen memory dies (there are eight “second semiconductor chips 70” but any number may be used, para. 0027).
Han and Shimizu teach stacks of memory chips (“second semiconductor chips 70a to 70h” are memory chips, para. 0027). The stack in Han teaches four chips while Shimizu teaches eight, though any number of “second semiconductor chips 70” is usable. The examiner understands that a greater number of “second memory chips 70” can store more data than a smaller number of “second memory chips 70”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the storage capacity of a memory chip stack is proportional to the number of memory chips it contains, each memory chip being of the same capacity
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Han with the memory stack taught in Shimizu. A stack comprising a greater number of semiconductor dies is capable of greater functions. In the case of memory semiconductor dies, more dies allow for more total memory storage.
Regarding claim 11, Han teaches the semiconductor device of claim 1, further comprising a controller die for controlling data transfer to and from the first plurality of semiconductor dies.
Nevertheless, Shimizu teaches
further comprising a controller die (“first semiconductor chip 30” is a memory controller chip, para. 0022) for controlling data transfer to and from the first plurality of semiconductor dies (the examiner understands a memory controller controls memory, such that “first semiconductor chip 30” controls “second semiconductor chips 70” through “wiring substrate 10”, para. 0063).
Han and Shimizu teach memory devices including memory stacks. The device in Shimizu includes a “first semiconductor chip 30” as a memory controller. It is understood that the exchange of data and commands through “wiring substrate 10” are directed towards the memory chips “second semiconductor chips 70”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a memory controller can control the storage of data in the “second semiconductor chips 70”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Han with the controller die taught in Shimizu. The controller die can control the storage and transfer of data in the stack of first plurality of semiconductor dies.
Regarding claim 12, Han, modified by Shimizu, teach the semiconductor device of claim 11, further comprising a molding compound (“sealing resin layer 90” para. 0016 FIG. 3) for encapsulating the die stack and the controller die (“sealing resin layer 90” encapsulates “first semiconductor chip 30” and “the second semiconductor chips 70”, para. 0031).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Han as applied to claim 1 above, in view of Tuckerman et al. US 5804004 A (hereinafter referred to as Tuckerman).
Han teaches the semiconductor device of claim 1 but fails to teach further comprising bond wires electrically coupling the first plurality of semiconductor dies to each other and the substrate.
Nevertheless, Tuckerman teaches
further comprising bond wires (“wire leads 189 and 190” col 3 line 62-63 FIG. 4A and 4B) electrically coupling the first plurality of semiconductor dies to each other and the substrate semiconductor dies to each other and the substrate (“chip 150a” is connected to “bond pads 180”, “chip 150b” is connected to “bond pads 189”, and “chip 150c” is connected to “bond pads 200”, col 3 lines 14 - 15, 30-31, 33-34 FIG. 4A-4B. “Chips 150a-150c” can be interconnected using the “engineering change pads 210”, col 3 lines 41-46 FIG. 4B).
Han and Tuckerman teach stacks of chips. The stack of “chips 150-150c” in Tuckerman are wirebonding to bond pads on “silicon circuit board 160” (col 3 line 7). In this manner, the chips can be staggered on the stack to reduce chip to chip spacing and wire removal can be employed if a chip becomes defective (col 3 lines 34-39). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that using wires bonded to pads on peripheral ends of the chips allows for more compact chip arrangements and for disconnection of individual chips from the stack if they become defective.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Han with the bond wires taught in Tuckerman. The stack height is reduced and semiconductor dies can be individually disconnected without affecting other die connections.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as unpatentable over Han US 20190259743 A1 (hereinafter referred to as Han), in view of Shimizu et al. US 20160276312 A1 (hereinafter referred to as Shimizu).
Regarding claim 13, Han teaches
A semiconductor device (“first discrete semiconductor package 11” para. 0055 FIG. 8), comprising:
a substrate (“base die 100D” made from “base die wafer 100”, para. 0054-0055 FIG. 7-8); and
a die stack (“first stack structure 208” para. 0055) mounted on the substrate, the die stack comprising a first plurality of semiconductor dies (“core dies 200” para. 0055);
However, Han fails to teach the first plurality of semiconductor dies each having a silicon substrate layer over which integrated circuit layers are formed, the die stack configured to include semiconductor dies having silicon substrate layers of substantially the same thickness based on a known die thickness (KTD) map of silicon substrate layer thicknesses and based on an overall desired thickness of the die stack; wherein the plurality of semiconductor dies are selected using the KTD map, the KTD map including thicknesses of the plurality of semiconductor dies, as well as the thicknesses of the silicon substrate layers of the plurality of semiconductor dies.
Nevertheless, Jo teaches
the first plurality of semiconductor dies (“first to fourth semiconductor chips (100, 200, 300, 400)” [0063] FIG. 1A) each having a silicon substrate layer (“first substrate 101”, “second substrate 201”, third substrate 301”, and “fourth substrate 401” are silicon wafer material, [0066-0071]) over which integrated circuit layers are formed (on each silicon wafer, “first integrated circuit 103”, “second integrated circuit 203”, “third integrated circuit 303”, and “fourth integrated circuit 403” are formed [0066-0071]), the die stack configured to include semiconductor dies having silicon substrate layers of substantially the same thickness and based on an overall desired thickness of the die stack (since “first to fourth semiconductor chips (100, 200, 300 and 400) may have the same thickness” and can be the same chips such as memory chips [0064 and 0073], the circuitry on them and thickness of their silicon wafer base are understood to be substantially the same.)
Han and Jo teach stacked chip structures. The chips in Jo comprise integrated circuitry formed on silicon wafers. Silicon is a known semiconductor material widely used in chip manufacturing for its versatility and ease of use. Jo teaches that different thinning and texturing processes can be done to the silicon wafers (see [0110]). If “first to fourth semiconductor chips (100, 200, 300, 400)” are the same type of memory chip and are the same thickness, it is understood that the thickness of the circuitry and the base silicon wafer material are the same for each chip. The “core dies 200” in Han have the same thickness and are also the same type of memory chip (Han para. 0035). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the silicon wafer substrate of each semiconductor chip in Jo has the same thickness if each chip is the same and of same total thickness. The processes for achieving this with silicon as the substrate material are well known.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Han with the silicon substrate layers taught in Jo. Silicon is a widely used wafer material upon which circuitry can be made. When the semiconductor dies of the same kind are of the same thickness, their silicon substrate layers are of the same thickness.
However, Han, modified by Jo, fail to teach wherein the plurality of semiconductor dies are selected using the KTD map, the KTD map including thicknesses of the plurality of semiconductor dies, as well as the thicknesses of the silicon substrate layers of the plurality of semiconductor dies.
Nevertheless, the language, term, or phrase “wherein the plurality of semiconductor dies are selected using the KTD map, the KTD map including thicknesses of the plurality of semiconductor dies, as well as the thicknesses of the silicon substrate layers of the plurality of semiconductor dies” is directed towards the process of making “a die stack mounted on the substrate”. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language " wherein the plurality of semiconductor dies are selected using the KTD map, the KTD map including thicknesses of the plurality of semiconductor dies, as well as the thicknesses of the silicon substrate layers of the plurality of semiconductor dies" only requires a die stack with dies having a particular thickness, which does not distinguish the invention from Han, who teaches the structure as claimed.
Regarding claim 14, Han, modified by Shimizu, teach the semiconductor device of claim 13, wherein the die stack is configured to include semiconductor dies comprising silicon substrate layers that are within 1.0 microns of each other (since “core dies 200” in Han are the same kind, have the same circuitry, and “each of the core dies 200 may have the same thickness T2”, para. 0035, it is understood the silicon wafer material as taught in Shimizu is substantially the same across each die).
Regarding claim 17, Han, modified by Shimizu, teach the semiconductor device of claim 13, wherein the first plurality of semiconductor dies all have substantially the same thicknesses (“each of the core dies 200 may have the same thickness T2”, para. 0035).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Han, modified by Shimizu, as applied to claim 14 above, in view of Lin et al. US 20120193785 A1 (hereinafter referred to as Lin).
Han, modified by Shimizu, teach the semiconductor device of claim 14 but fail to teach wherein the die stack is configured to include semiconductor dies comprising silicon substrate layers that are between 7.0 microns and 8.0 microns.
Nevertheless, Lin teaches
wherein the die stack (“stacked chips in the multichip package” para. 0046 FIG. 1) is configured to include semiconductor dies comprising silicon substrate layers that are between 7.0 microns and 8.0 microns (“semiconductor substrate 2 of each of the stacked chips in the multichip package may be a silicon substrate having a suitable thickness” such as between 1 and 10 micrometers, para. 0046).
Han, modified by Shimizu, and Lin teach semiconductor devices comprising stacked chips. The chip stack in Lin features “semiconductor substrates 2” of each memory chip having a same thickness between 1 and 10 microns (para. 0056). The thinner the chips, the thinner the overall semiconductor device or the greater the storage capacity of the device, depending on the individual chip capabilities. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a stack of chips having silicon substrates of 1-10micron thickness can achieve a package with greater storage density.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Han and Shimizu with the silicon substrate thickness taught in Lin. The silicon substrate thickness affects the overall stack height. Thinner substrates lead to more densely packed memory chips.
Claim 21 is rejected under 35 U.S.C. 103 as unpatentable over Han US 20190259743 A1 (hereinafter referred to as Han), in view of Lin et al. US 20120193785 A1 (hereinafter referred to as Lin).
Han teaches
A semiconductor device (“first discrete semiconductor package 11” para. 0055 FIG. 8), comprising:
a substrate (“base die 100D” made from “base die wafer 100”, para. 0054-0055 FIG. 7-8); and
a die stack (“first stack structure 208” para. 0055) mounted on the substrate, the die stack comprising a plurality of semiconductor dies (“core dies 200” para. 0055),
However, Han fails to teach wherein each semiconductor die in the die stack comprises a silicon substrate layer over which integrated circuit layers are formed, wherein each semiconductor die in the die stack has at least one of: i) a thickness within a common thickness range defined by a thickness category of a known thickness die (KTD) map, and ii) semiconductor dies comprising silicon substrate layers of at least 7 microns based on a KTD map of the silicon substrate layers.
Nevertheless, Lin teaches
wherein each semiconductor die in the die stack (“stacked chips in the multichip package” para. 0046 FIG. 1) comprises a silicon substrate layer over which integrated circuit layers are formed (each “semiconductor substrate 2” is a silicon substrate that includes “integrated circuit (IC) devices 7”, para. 0044-0046)
semiconductor dies comprising silicon substrate layers of at least 7 microns (“semiconductor substrate 2” of each of the stacked chips in the multichip package may be a thickness such as between 1 and 10 micrometers, para. 0046).
Han and Lin teach semiconductor devices comprising stacked chips. The chip stack in Lin features “semiconductor substrates 2” of each memory chip having a same thickness between 1 and 10 microns (para. 0056). The thinner the chips, the thinner the overall semiconductor device or the greater the storage capacity of the device, depending on the individual chip capabilities. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a stack of chips having silicon substrates of 1-10micron thickness can achieve a package with greater storage density.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Han with the silicon substrate thickness taught in Lin. The silicon substrate thickness affects the overall stack height. Thinner substrates lead to more densely packed memory chips.
However, Han, modified by Lin, fails to teach a thickness within a common thickness range defined by a thickness category of a known thickness die (KTD) map, and ii) semiconductor dies comprising silicon substrate layers of at least 7 microns based on a KTD map of the silicon substrate layers.
Nevertheless, the language, term, or phrase “a thickness within a common thickness range defined by a thickness category of a known thickness die (KTD) map, and ii) semiconductor dies comprising silicon substrate layers of at least 7 microns based on a KTD map of the silicon substrate layers” is directed towards the process of making “a die stack mounted on the substrate”. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language " a thickness within a common thickness range defined by a thickness category of a known thickness die (KTD) map, and ii) semiconductor dies comprising silicon substrate layers of at least 7 microns based on a KTD map of the silicon substrate layers" only requires a die stack with dies having a particular thickness, which does not distinguish the invention from Han, who teaches the structure as claimed.
Conclusion
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/ERIC MANUEL MULERO FLORES/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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