DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claim(s) 16, 21, and 30 filed on 9/27/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 17-70, 22-29, 31-32, and 34-36 have been considered. Claim(s) 1-15, and 33 are canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 8-9, filed 07/14/2026, with respect to the rejection(s) of claim(s) 16 under 35 U.C.C. 102 and 16-32, and 34-36 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of HUANG, ZHANG, and CHANG.
Regarding Claim 16. The Applicant argues that the references fails to disclose or suggest the amended features recites, “a method, comprising: forming a second dielectric layer over the metal-insulator metal capacitor, wherein the second dielectric layer extends on sidewalls of the portion of the first insulator layer, the portion of the second insulator layer, and the bottom plate”. The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, HUANG as modified by ZHANG, wherein ZHANG further teaches the claimed limitation as exemplified in the drawing, Figure 3, as detailed in the claim rejection below.
Regarding Claims 17-20: The dependent claims 17-20 follow similar arguments as Claim 16, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Regarding Claim 21. The Applicant argues that the references fails to disclose or suggest the amended features recites, “a method, comprising: depositing a conductive layer over the etch stop layer; patterning the conductive layer to form a bottom conductor plate over the first lower contact feature and on the etch stop layer”. The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, HUANG as modified by ZHANG and CHANG, wherein CHANG further teaches the claimed limitation as exemplified in the drawing, sequentially, Figures 1, 3, and 5 and [Col. 6, Lines 30-33], as detailed in the claim rejection below.
Regarding Claims 22-29: The dependent claims 22-29 follow similar arguments as Claim 21, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Regarding Claim 30. The Applicant argues that the references fails to disclose or suggest the amended features recites, “a method, comprising: after the removing of the portion of the first insulation layer, performing a first etching process to form a first opening, and a second opening each extending through the second dielectric layer and metal-insulator-metal capacitor, wherein the performing of the first etching process further forms a third opening spaced apart from each layer of the metal-insulator-metal capacitor, wherein each of the first opening and the second opening exposes a portion of a top surface of the etch stop layer”. The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, HUANG as modified by ZHANG, wherein ZHANG further teaches the claimed limitation as exemplified in the drawing, Figures 2, as detailed in the claim rejection below.
Regarding Claims 31-32, and 34-36: The dependent claims 31-32, and 34-36 follow similar arguments as Claim 30, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 16, 30, 34-and 35, is/are rejected under 35 U.S.C. 103 as being unpatentable over Chih-Fan Huang et al, (hereinafter HUANG), US 20210013301 A1, in view of Xunyuan Zhang et al, (hereinafter ZHANG), US 20190013269 A1.
Regarding Claim 16, HUANG teaches a method (Fig. 1J, method for forming the MIM capacitor structure, 500A, [0065]), comprising:
providing a workpiece (Fig. 1J, 200, substrate) comprising:
a first dielectric layer (Fig. 1J, 210, dielectric layers); and
a first lower contact feature (Fig. 1J, 214, metal material), a second lower contact feature (Fig. 1J, 214, metal material), and a third lower contact feature (Fig. 1J, 214, metal material) in the first dielectric layer (Fig. 1J, 210, dielectric layers);
depositing an etch stop layer (Fig. 1J, 216) on the first dielectric layer (Fig. 1J, 210, dielectric layers);
forming a metal-insulator-metal capacitor (Fig. 1J, 500A, MIM capacitor structure) over the etch stop layer (Fig. 1J, 216), the metal-insulator- metal capacitor (Fig. 1J, 500A, MIM capacitor structure) comprising: a bottom plate (Fig. 1J, 220, bottom electrode layer) over the etch stop layer (Fig. 1J, 216), a first insulator layer (Fig. 1J, 230, dielectric layer) over the bottom plate (Fig. 1J, 220, bottom electrode layer), a middle plate (Fig. 1J, 232, middle electrode layer) over the first insulator layer (Fig. 1J, 230, dielectric layer), a second insulator layer (Fig. 1J, 240, dielectric layer) over the middle plate (Fig. 1J, 232, middle electrode layer), and a top plate (Fig. 1J, 242, top electrode layer) over the second insulator layer (Fig. 1J, 240, dielectric layer), wherein a portion (annotated Figure 1J) of the second insulator layer (Fig. 1J, 240, dielectric layer) extends on a portion (annotated Figure 1J) of the first insulator layer (Fig. 1J, 230, dielectric layer);
forming a first contact via (Fig. 1J, 250A, RDL structures) penetrating multiple layers (annotated Figure 1J) of the metal-insulator-metal capacitor (Fig. 1J, 500A, MIM capacitor structure) to electrically couple (annotated Figure 1J) to the first lower contact feature (Fig. 1J, 214, metal material); and
forming a second contact via (Fig. 1J, 250A, RDL structures) penetrating multiple layers (annotated Figure 1J) of the metal-insulator-metal capacitor (Fig. 1J, 500A, MIM capacitor structure) to electrically couple (annotated Figure 1J) to the second lower contact feature (Fig. 1J, 214, metal material).
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HUANG does not explicitly disclose a method, comprising: forming a second dielectric layer over the metal-insulator-metal capacitor, wherein the second dielectric layer extends on sidewalls of the portion of the first insulator layer, the portion of the second insulator layer.
ZHANG teaches a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]), comprising: forming a second dielectric layer (Fig. 3, 36, dielectric layer) over the metal-insulator-metal capacitor (annotated Figure 3), wherein the second dielectric layer (Fig. 3, 36, dielectric layer) extends on sidewalls of the portion (annotated Figure 3) of the first insulator layer (Fig. 3, 24, dielectric layer), the portion of the second insulator layer (Fig. 3, 28, dielectric layer), and the bottom plate (Fig. 3, 22, conductive materials layer).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUANG to incorporate the teachings of ZHANG such that a method comprising: forming a second dielectric layer over the metal-insulator-metal capacitor, wherein the second dielectric layer extends on sidewalls of the portion of the first insulator layer, the portion of the second insulator layer, and the bottom plate, so that the same sidewall (31) as an outer perimeter or boundary with the area equal to the product of the common length (L) and the common width (W) and further overlap within the dielectric layer (36) and used to pattern the trenches (38, 40, and 42), and therefore, the electrodes and capacitor dielectrics have the same area and the same footprint projected on to top surface of the dielectric layer (20) (ZHANG, [0017-0018]).
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Regarding Claim 30, HUANG teaches a method (Fig. 1J, method for forming the MIM capacitor structure, 500A, [0065]), comprising:
forming a first lower contact feature (Fig. 1J, 214, metal material), a second lower contact feature (Fig. 1J, 214, metal material), and a third lower contact feature (Fig. 1J, 214, metal material) in a first dielectric layer (Fig. 1J, 210, dielectric layers),
depositing an etch stop (Fig. 1J, 216) over the first dielectric layer (Fig. 1J, 210, dielectric layers);
forming a metal-insulator-metal capacitor (Fig. 1J, 500A, MIM capacitor structure) over the etch stop layer (Fig. 1J, 216), the metal-insulator- metal capacitor (Fig. 1J, 500A, MIM capacitor structure) comprising: a bottom conductor plate (Fig. 1J, 220, bottom electrode layer), a first insulator layer (Fig. 1J, 230, dielectric layer) over the bottom conductor plate (Fig. 1J, 220, bottom electrode layer) and a laterally adjacent (annotated Fig. 1J) to the bottom conductor plate (Fig. 1J, 220, bottom electrode layer), a middle conductor plate (Fig. 1J, 232, middle electrode layer) over the first insulator layer (Fig. 1J, 230, dielectric layer), a second insulator layer (Fig. 1J, 240, dielectric layer) over the middle conductor plate (Fig. 1J, 232, middle electrode layer), and a top conductor plate (Fig. 1J, 242, top electrode layer) over the second insulator layer (Fig. 1J, 240, dielectric layer).
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forming a second dielectric layer (Fig. 1J, 246, dielectric layer) over the metal-insulator-metal capacitor (Fig. 1J, 500A, MIM capacitor structure; 220-230-232-240-242 MIM stack);
forming a first contact via (Fig. 1J, 250A, RDL structures) in the vertically extended first opening (Fig. 1J, 264A) to contact the first lower contact feature (Fig. 1J, 214, metal material);
forming a second contact (Fig. 1J, 250A, RDL structures) via in the vertically extended second opening (Fig. 1J, 264B) to contact the second lower contact feature (Fig. 1J, 214, metal material).
HUANG does not explicitly disclose, a method comprising: after the forming of the metal-insulator-metal capacitor, removing a portion of the first insulation layer, thereby exposing a sidewall surface of the bottom conductor plate; after the removing of the portion of the first insulation layer, performing a first etching process to form a first opening and a second opening each extending through the second dielectric layer and the metal-insulator-metal capacitor wherein the performing of the first etching process further forms a third opening spaced apart from each layer of the metal-insulator-metal capacitor, wherein each of the first opening and the second opening exposes a portion of a top surface of the etch stop layer; performing a second etching process to vertically extend the first opening, the second opening, thereby exposing the first lower contact feature, the second lower contact feature, and the third lower contact feature, respectively; forming a first contact via in the vertically extended first opening to contact the first lower contact feature; forming a second contact via in the vertically extended second opening to contact the second lower contact feature.
ZHANG teaches in Figures 3-6, a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]) comprising:
after the forming of the metal-insulator-metal capacitor (Fig. 1, 22, 24, 26, 28, 30, MIM capacitor stack 32, [0011]), removing a portion of the first insulation layer (Fig. 2, 24, layers may be patterned to shape the capacitor dielectrics of the MIM capacitor, 32, [0015]), thereby exposing a sidewall surface (annotated Figure 2) of the bottom conductor plate (Fig. 2, 22, layers).
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after the removing of the portion of the first insulation layer (Fig. 2, 24, layers may be patterned to shape the capacitor dielectrics of the MIM capacitor, 32, [0015]), performing a first etching process (patterned with lithography and etching processes, [0018-0022]) to form a first opening (Fig. 3, 42, trenches) and a second opening (Fig. 3, 40, trenches) each extending through the second dielectric layer (Fig. 3, 36, dielectric layer) and the metal-insulator-metal capacitor (Figs. 1-3, 22, 24, 26, 28, 30, MIM capacitor stack 32, [0011]) wherein the performing of the first etching process (patterned with lithography and etching processes, [0018-0022]) further forms a third opening (Fig. 3, 38, trenches) spaced apart from each layer of the metal-insulator-metal capacitor (Figs. 1-3, 22, 24, 26, 28, 30, MIM capacitor stack 32, [0011]), wherein each of the first opening (Fig. 4, 42, trenches) and the second opening (Fig. 4, 40, trenches) exposes a portion of a top surface of the etch stop layer (not shown the trench only up to the top layer of capping layer 18, but it is obvious to etch up to the top surface and the Figure 4 shows penetration of the caping layer further);
performing a second etching process (patterned with lithography and etching processes, [0018-0022]) to vertically extend the first opening (Fig. 3, 42, trenches), the second opening (Fig. 3, 40, trenches), and the third opening (Fig. 3, 38, trenches), thereby exposing the first lower contact feature (Fig. 4, 14, conductive wiring features), the second lower contact feature (Fig. 4, 14, conductive wiring features), and the third lower contact feature (Fig. 5, 14, conductive wiring features), respectively;
forming a first contact via (Fig. 7, 62/68, conductive wiring features/conductive vias [0026]) in the vertically extended first opening (Fig. 6, 42, trenches) to contact the first lower contact feature (Fig. 7, 14, conductive wiring features);
forming a second contact via (Fig. 7, 62/66, conductive wiring features/conductive vias [0026]) in the vertically extended second opening (Fig. 6, 40, trenches) to contact the second lower contact feature (Fig. 7, 14, conductive wiring features).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUANG to incorporate the teachings of ZHANG such that a method comprising: after the removing of the portion of the first insulation layer, performing a first etching process to form a first opening a and a second opening each extending through the second dielectric layer and the metal-insulator-metal capacitor, wherein the performing of the first etching process further forms a third opening spaced apart from each layer of the metal-insulator-metal capacitor, wherein each of the first opening and the second opening exposes a portion of a top surface of the etch stop layer; performing a second etching process to vertically extend the first opening, the second opening, and the third opening, thereby exposing the first lower contact feature, the second lower contact feature, and the third lower contact feature, respectively; forming a first contact via in the vertically extended first opening to contact the first lower contact feature; forming a second contact via in the vertically extended second opening to contact the second lower contact feature. The aforementioned arrangement of MIM capacitor structure with a first electrode, a second electrode and a third electrode, further includes a conductive via in a via opening extending vertically through the layer stack, for the formation of a semiconductor structure that includes metal-insulator-metal (MIM) capacitor (ZHANG, [0001-0005]). Additionally, the above arrangement enables each of the patterned/etched layers (22, 24, 26, 28, 30) can be etched using single etch mask, 34 so that the electrodes and capacitor dielectrics have the same area and the same footprint projected onto the top surface of the dielectric layer, 20 (ZHANG, [0017]).
Regarding Claim 34, HUANG as modified by ZHANG, teaches the method of claim 30.
ZHANG teaches the method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]), further comprising:
Removing a portion of the second insulation layer (Fig. 2, 28, layers), that extends from the second lower contact feature (Fig. 2, 14, conductive wiring feature) to the third lower contact feature (Fig. 2, 14, conductive wiring feature).
HUANG further teaches the method (Fig. 1J, method for forming the MIM capacitor structure, 500A, [0065]), further comprising:
wherein the portion (annotated Figure 1H) of the second insulator layer (Fig. 1H, 240, dielectric layer) extends on the portion (annotated Figure 1H) of the first insulator layer (Fig. 1H, 230, dielectric layer);
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Regarding Claim 35, HUANG as modified by ZHANG, teaches the method of claim 34.
ZHANG further teaches the method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]), further comprising:
forming a third contact via (Fig. 7, 62/64, conductive wiring features/conductive vias [0026]) in the vertically extended third opening (Fig. 6, 46, via opening, [0018-0022]) to contact the third lower contact feature (Figs. 6-7, 14, conductive wiring features; annotated Figure 7), wherein the third contact via (Fig. 7, 64, [0026]) is physically spaced apart (annotated Figure 7) from the first insulation (Fig. 7, 24, [0013]) layer and the second insulation layer (Fig. 7, 28, [0013]) by the second dielectric layer (Fig. 7, 36, [0018]).
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Claim(s) 17-26, 29, and 31-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUANG in view of ZHANG as applied to Claims 16, 30, and 34-35 above, and further in view of Yao-Wen Chang, (hereinafter CHANG), US 10290701 B1.
Regarding Claim 17, HUANG as modified by ZHANG teaches the method of claim 16.
HUANG further teaches a method (Fig. 1J, method for forming the MIM capacitor structure, 500A, [0065]), wherein the forming of the metal-insulator-metal capacitor (Fig. 1J, 500A, MIM capacitor structure) comprises:
depositing the first insulator layer (Fig. 1J, 230, dielectric layer) over the workpiece (Fig. 1J, 200, substrate);
forming the middle plate (Fig. 1J, 232, middle electrode layer) over the first insulator layer (Fig. 1J, 230, dielectric layer), the middle plate (Fig. 1J, 232, middle electrode layer) being vertically overlapped (annotated Figure 1J) with the first lower contact feature (Fig. 1J, 214, metal material);
depositing the second insulator layer (Fig. 1J, 240, dielectric layer) over the workpiece (Fig. 1J, 200, substrate); and
forming the top plate (Fig. 1J, 242, top electrode layer) over the second insulator layer (Fig. 1J, 240, dielectric layer), the top plate (Fig. 1J, 242, top electrode layer) being vertically overlapped (annotated Fig. 1J) with the second lower contact feature (Fig. 1J, 214, metal material).
HUANG as modified by ZHANG does not explicitly disclose the method, wherein the forming of the metal-insulator-metal capacitor comprises: depositing a first conductive layer on the etch stop layer; patterning the first conductive layer to form a conductive feature over the first lower contact feature and the bottom plate over the second lower contact feature.
CHANG teaches a method (Fig. 1, 10), wherein the forming of the metal-insulator-metal capacitor comprises:
depositing (Fig. 1, 102, [Col. 5, Lines 47-50]) a first conductive layer (Fig. 3, 310/310a) on the etch stop layer (Fig. 3, 308, protection layer);
patterning (Fig. 1, 104, [Col. 6 Lines, 30-33]) the first conductive layer to form a conductive feature (Fig. 3, 310/310a) over the first lower contact feature (Fig. 5, 304, conductive layer) and the bottom plate (Fig. 5, 312, bottom electrode) over the second lower contact feature (Fig. 5, 304, conductive layer)
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUANG as modified by ZHANG to incorporate the teachings of CHANG such that a method, wherein the forming of the metal-insulator-metal capacitor comprises: depositing a first conductive layer on the etch stop layer; patterning the first conductive layer to form a conductive feature over the first lower contact feature and the bottom plate over the second lower contact feature., so that the smoother and uniform conductive layer is formed and patterned for obtaining a uniform and smoother bottom plate electrode for a MIM capacitor structure (CHANG, [Col. 6, Lines 2-5; and 25-30].
Regarding Claim 18, HUANG as modified by ZHANG and CHANG teaches the method of claim 17.
ZHANG further teaches a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]), wherein the forming of the first contact via (Fig. 7, 62/68, conductive wiring features/conductive vias [0026]) and the second contact via (Fig. 7, 62/66, conductive wiring features/conductive vias [0026]) comprises:
performing a first etching process (patterned with lithography and etching processes, [0018-0022]) to form a first via opening (Fig. 6, 54, via opening, [0018-0022]) extending through both the middle plate (Fig. 6, 26, patterned layer, [0016]) and the conductive feature (Fig. 2, 32, patterned layers, [0020]) and stop on the etch stop layer (annotated Figure 6; not shown the trench only up to the top layer of capping layer 18, but it is obvious to etch up to the top surface and the Figure 4 shows penetration of the caping layer further), and a second via opening (Fig. 6, 48, via opening, [0018-0022]) extending through both the top plate (Fig. 6, 30, patterned layer, [0016]) and the bottom plate (Fig. 6, 22, patterned layer, [0016]) and stop on the etch stop layer (annotated Figure 6; not shown the trench only up to the top layer of capping layer 18, but it is obvious to etch up to the top surface and the Figure 4 shows penetration of the caping layer further);
performing a second etching process (patterned with lithography and etching processes, [0018-0022]) to extend the first via opening (Fig. 6, 54, via opening, [0018-0022]) and the second via opening (Fig. 6, 48, via opening, [0018-0022]), thereby exposing the first lower contact feature and the second lower contact feature (Fig. 6, 14, conductive wiring features; annotated Figure 6);
forming the first contact via (Fig. 7, 62/68, conductive wiring features/conductive vias [0026]) in the extended first via opening (Fig. 6, 54, via opening, [0018-0022]); and
forming the second contact via (Fig. 7, 62/66, conductive wiring features/conductive vias [0026]) in the extended second via opening (Fig. 6, 48, via opening, [0018-0022]).
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Regarding Claim 19, HUANG as modified by ZHANG and CHANG teaches the method of claim 18.
ZHANG further teaches in Figures 3-6, a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]), wherein the workpiece (Fig. 1, BEOL Interconnect structure, [0010]) further comprises a third lower contact feature (Figs. 6-7, 14, conductive wiring features; annotated Figure 7) formed in the first dielectric layer (Fig. 1, 20, dielectric layer, [0010]) and spaced apart from the second lower contact feature (Figs. 6-7, 14, conductive wiring features; annotated Figure 7) along a first direction (annotated Figure 7), wherein the top plate (Fig. 2, 30, patterned layer, [0011]) is not vertically overlapped (annotated Figure 7) with the third lower contact feature (Figs. 6-7, 14, conductive wiring features; annotated Figure 7).
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Regarding Claim 20, HUANG as modified by ZHANG and CHANG teaches the method of claim 19.
ZHANG further teaches in Figures 3-6, a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]), after the forming of the metal-insulator-metal capacitor (Fig. 1, 22, 24, 26, 28, 30, MIM capacitor stack, [0011]) and before the forming of the second dielectric layer (Fig. 2, no formation of 36, dielectric layer), performing an etching process ([0015]) to remove portions of the second insulator layer (Fig. 2, 28) and the first insulator layer (Fig. 2, 24) over the third lower contact feature (Fig. 2, 14, conductive wiring feature).
forming a third contact via (Fig. 7, 62/64, conductive wiring features/conductive vias) penetrating the second dielectric layer (Fig. 7, 36, dielectric layer) to contact the third lower contact feature (Fig. 7, 14, conductive wiring feature).
Regarding Claim 21, HUANG teaches a method (Fig. 1J, method for forming the MIM capacitor structure, 500A, [0065]), comprising:
forming a first lower contact feature (Fig. 1J, 214, metal material), a second lower contact feature (Fig. 1J, 214, metal material), and a third lower contact feature (Fig. 1J, 214, metal material) in a dielectric layer (Fig. 1J, 210, dielectric layers);
depositing an etch stop layer (Fig. 1J, 216) on the first lower contact feature (Fig. 1J, 214, metal material), the second lower contact feature (Fig. 1J, 214, metal material), and the third lower contact feature (Fig. 1J, 214, metal material);
after the forming of the bottom conductor plate (Fig. 1J, 220, bottom electrode layer), conformally depositing a first insulation layer (Fig. 1J, 230, dielectric layer) over the first dielectric layer (Fig. 1J, 210, dielectric layers);
forming a middle conductor plate (Fig. 1J, 232, middle electrode layer) over the first insulation layer (Fig. 1J, 230, dielectric layer) and the second lower contact feature (Fig. 1J, 240, dielectric layer);
after the forming of the middle conductor plate (Fig. 1J, 232, middle electrode layer), conformally depositing a second insulation layer (Fig. 1J, 240, dielectric layer) over the first dielectric layer (Fig. 1J, 210, dielectric layers);
forming a top conductor plate (Fig. 1J, 242, top electrode layer) over the second insulation layer (Fig. 1J, 240, dielectric layer) and the first lower contact feature (Fig. 1J, 214, metal material).
HUANG does not explicitly disclose, a method comprising: performing an etching process to remove portions of the first insulation layer and the second insulation layer extended over the third contact feature; after the forming of the bottom conductor plate, the middle conductor plate, and the top conductor plate, performing an etching process to remove portions of the first insulation layer and the second insulation layer extended over the third lower contact feature; and after the performing of the etching process, forming a second dielectric layer over the etch stop layer and the top conductor plate.
ZHANG teaches in Figures 1-2, a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]) comprising:
performing an etching process (Fig. 2, 34, a single etch mask patterning, [0015-0017]) to remove portions (unmasked regions of layers 22/24/26/28/30 are removed with a n etching process, [0015]) of the first insulation layer (Fig. 2, 24, patterned dielectric layer, [0016]) and the second insulation layer (Fig. 2, 28, patterned dielectric layer, [0016]) extended over the third contact feature (Fig. 2, 14, conductive wiring feature; annotated Figure 2).
after the forming of the bottom conductor plate (Fig. 1, 22), the middle conductor plate (Fig. 1, 26), and the top conductor plate (Fig. 1, 30), performing an etching process ([0015]) to remove portions of the first insulation layer (Fig. 2, 24) and the second insulation layer (Fig. 2, 28) extended over the third lower contact feature (Fig. 2, 14, conductive wiring feature); and
after the performing of the etching process ([0015]), forming a second dielectric layer (Fig. 3, 36) over the etch stop layer (Fig. 3, 18, capping layer) and the top conductor plate (Fig. 1, 30).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUANG to incorporate the teachings of ZHANG such that a method comprising: performing an etching process to remove portions of the first insulation layer and the second insulation layer extended over the third contact feature; after the forming of the bottom conductor plate, the middle conductor plate, and the top conductor plate, performing an etching process to remove portions of the first insulation layer and the second insulation layer extended over the third lower contact feature; and after the performing of the etching process, forming a second dielectric layer over the etch stop layer and the top conductor plate. The above arrangement enables each of the patterned/etched layers (22, 24, 26, 28, 30) can be etched using single etch mask, 34 so that the electrodes and capacitor dielectrics have the same area and the same footprint projected onto the top surface of the dielectric layer, 20 (ZHANG, [0017]).
HUANG as modified by ZHANG does not explicitly disclose, a method comprising: depositing a conductive layer over the etch stop layer; patterning the conductive layer to form a bottom conductor plate over the first lower contact feature.
CHANG teaches a method (Fig. 1, 10), comprising:
depositing (Fig. 1, 102, [Col. 5, Lines 47-50]) a conductive layer (Fig. 3, 310/310a, first conductive layer) over the etch stop layer (Fig. 3, 308, protection layer);
patterning (Fig. 1, 104, [Col. 6 Lines, 30-33]) the conductive layer (Fig. 3, 310/310a, first conductive layer) to form a bottom conductor plate (Fig. 5, 312, bottom electrode) over the first lower contact feature (Fig. 5, 304, conductive layer);
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUANG as modified by ZHANG to incorporate the teachings of CHANG such that a method comprising: depositing a conductive layer over the etch stop layer; patterning the conductive layer to form a bottom conductor plate over the first lower contact feature, so that the smoother and uniform conductive layer is formed and patterned for obtaining a uniform and smoother bottom plate electrode for a MIM capacitor structure (CHANG, [Col. 6, Lines 2-5; and 25-30].
Regarding Claim 22, HUANG as modified by ZHANG and CHANG teaches the method of claim 21.
ZHANG further teaches in Figures 2, and 3, the method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]), wherein, after the performing of the etching process (Fig. 2, 34, single etch mask, [0017]), sidewall surfaces (Fig. 2, 31, same sidewall, [0017]) of the first insulation layer (Fig. 2, 24) and the second insulation layer (Fig. 2, 28) are vertically aligned (Fig. 2A, arrow pointing up) with a sidewall surface of the bottom conductor plate (Fig. 2, 22, conductive material layer, [0012]).
Regarding Claim 23, HUANG as modified by ZHANG and CHANG teaches the method of claim 21.
HUANG further teaches the method (Fig. 1J, method for forming the MIM capacitor structure, 500A, [0065]), wherein an entirety of a top surface (Fig. 1H, 244) of the top conductor plate (Fig. 1H, 242, top electrode layer) is above a topmost surface (annotated Figure 1H) of the second insulation layer (Fig. 1J, 240, dielectric layer).
Regarding Claim 24, HUANG as modified by ZHANG and CHANG teaches the method of claim 21.
HUANG further teaches the method (Fig. 1J, method for forming the MIM capacitor structure, 500A, [0065]), wherein a distance between (annotated Figure 1H) the first lower contact feature (Fig. 1H, 214, metal material) and the third lower contact feature (Fig. 1H, 214, metal material) is greater than a distance between (annotated Figure 1H) the bottom conductor plate (Fig. 1H, 220, bottom electrode layer) and the third lower contact feature (Fig. 1H, 214, metal material).
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Regarding Claim 25, HUANG as modified by ZHANG and CHANG teaches the method of claim 23.
ZHANG further teaches a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007], wherein the etching process (patterned with lithography and etching processes, [0018-0022]) is a first etching process, and the method further comprises:
performing a second etching process (patterned with lithography and etching processes, [0018-0022]) to form a first via opening (Fig. 6, 54, via opening, [0018-0022]) and a second via opening (Fig. 6, 48, via opening, [0018-0022]) each extending through the second dielectric layer (Fig. 3, 36, [0018]), the first via opening and the second via opening each exposing the etch stop layer (Fig. 3, 18, caping layer, [0018]; annotated Figure 6; not shown the trench only up to the top layer of capping layer 18, but it is obvious to etch up to the top surface and the Figure 4 shows penetration of the caping layer further);
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performing a third etching process (patterned with lithography and etching processes, [0018-0022]) to remove portions of the etch stop layer (Fig. 3, 18, caping layer, [0018]) exposed by the first via opening (Fig. 6, 54, via opening, [0018-0022]) and the second via opening (Fig. 6, 48, via opening, [0018-0022]), thereby exposing the first lower contact feature and the second lower contact feature, respectively (Fig. 6, 14, conductive wiring features; annotated Figure 6; and
forming a first via (Fig. 8, 68, conductive via) and a second via (Fig. 8, 66, conductive via) in the first via opening (Fig. 6, 54, via opening) and the second via opening (Fig. 6, 48, via opening), respectively.
Regarding Claim 26, HUANG as modified by ZHANG and CHANG teaches the method of claim 25.
ZHANG further teaches a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007], comprising:
forming a third via (Fig. 8, 64, conductive via) extending through the second dielectric layer (Fig. 8, 36, dielectric layer) and the etch stop layer (Fig. 8, 18, capping layer) to physically contact the third lower contact feature (Fig. 6, 14, conductive wiring features; annotated Figure 6).
Regarding Claim 29, HUANG as modified by ZHANG, and CHANG teaches the method of claim 25.
CHANG further teaches a method (Fig. 1, 10), the method, further comprising:
forming a dummy conductor plate (Fig. 4A, 310, first conductive layer) during the forming of the bottom conductor plate (Figs. 4A/13, 312, bottom electrode; Fig. 5, the first conductive layer, 310 is then patterned to form a bottom electrode, 312, [Col. 6, Lines 30-33]), wherein the second via (Fig. 13, via opening where the conductor, 380 is placed) further extends through the dummy conductor plate (Figs. Fig. 4A, 310, first conductive layer, [Col. 9, Lines 30-35]).
Regarding Claim 31, HUANG as modified by ZHANG, teaches the method of claim 30.
HUANG as modified by ZHANG, teaches the method, further comprising: during the forming of the metal-insulator-metal capacitor, forming a dummy conductor plate physically isolated from the bottom conductor plate, wherein the dummy conductor plate and the bottom conductor plate are formed simultaneously.
CHANG further teaches the method (Fig. 1, 10), the method, further comprising:
during the forming of the metal-insulator-metal capacitor (Fig. 2, 20), forming a dummy conductor plate (Fig. 4A, 310, first conductive layer) physically isolated from the bottom conductor plate (Figs. 4A/13, 312, bottom electrode; Fig. 5, the first conductive layer, 310 is then patterned to form a bottom electrode, 312, [Col. 6, Lines 30-33]), wherein the dummy conductor plate (Fig. 4A, 310, first conductive layer) and the bottom conductor plate (Figs. 4A/13, 312, bottom electrode; Fig. 5, the first conductive layer, 310 is then patterned to form a bottom electrode, 312, [Col. 6, Lines 30-33]) are formed (Fig. 1, 104, operation) simultaneously.
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUANG as modified by ZHANG to incorporate the teachings of CHANG such that the method, further comprising: during the forming of the metal-insulator-metal capacitor, forming a dummy conductor plate physically isolated from the bottom conductor plate, wherein the dummy conductor plate and the bottom conductor plate are formed simultaneously, so that the conductive layer underneath the bottom electrode provide a smoother and even surface for further depositing first dielectric layer and other layers to form a metal-insulator-metal capacitor on a semiconductor device (CHANG, [Col. 6, Lines 55-57]).
Regarding Claim 32, HUANG as modified by ZHANG, and CHANG teaches the method of claim 31.
CHANG further teaches the method (Fig. 1, 10), wherein the first via (Fig. 13, via opening where the conductor, 380 is placed) extends through the dummy conductor plate (Fig. 4A, 310, first conductive layer).
Claim(s) 27-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUANG in view of ZHANG and CHANG as applied to claims 17-26, 29 and 31-32 above, and further in view of Jinho Park et al, (hereinafter PARK), US 20200350248 A1.
Regarding Claim 27, HUANG as modified by ZHANG and CHANG teaches the method of claim 26.
HUANG as modified by ZHANG and CHANG does not explicitly disclose the method, wherein, in a top view, the third lower contact feature extends lengthwise along a first direction, the third lower contact feature is disposed laterally adjacent to the first lower contact feature along a second direction that is substantially perpendicular to the first direction.
PARK teaches the method ([0046]), wherein, in a top view (Fig. 1), the third lower contact feature (Figs. 1/7G, CP3/117, third contact plug/lower wiring layer) extends lengthwise along a first direction (annotated Figure 1), the third lower contact feature (Figs. 1/7, CP3/117, third contact plug/lower wiring layer) is disposed laterally adjacent to the first lower contact feature (Figs. 1/7G, CP1/113, first contact plug/lower wiring layer) along a second direction (annotated Figure 1) that is substantially perpendicular (annotated Figure 1) to the first direction (annotated Figure 1).
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Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUANG as modified by ZHANG and CHANG to incorporate the teachings of PARK such that the method, wherein, in a top view, the third lower contact feature extends lengthwise along a first direction, the third lower contact feature is disposed laterally adjacent to the first lower contact feature along a second direction that is substantially perpendicular to the first direction, so that a metal-insulator-metal (MIM) capacitor may be effectively used in a semiconductor device instead of a metal-insulator-semiconductor (MIS) capacitor for dynamic random access memory (DRAM) applications (PARK, [0003-0004]).
Regarding Claim 28, HUANG as modified by ZHANG, CHANG, and PARK teaches the method of claim 27.
PARK further teaches a method ([0046]), wherein, in the top view (Fig. 1), a length of the first lower contact feature (Figs. 1/7G, CP1/113, first contact plug/lower wiring layer) is less than (annotated Figure 1) a length of the third lower contact feature (Figs. 1/7G, CP3/117, third contact plug/lower wiring layer).
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Claim(s) 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUANG in view of ZHANG as applied to claims 16, 30, 34-35 above, and further in view of PARK as applied to claims 27-28 above.
Regarding Claim 36, HUANG as modified by ZHANG, teaches the method of claim 34.
HUANG as modified by ZHANG and CHANG does not explicitly disclose the method, wherein, in a top view, the second lower contact feature and the third lower contact feature extend lengthwise along different directions.
PARK further teaches in Figure 7G, a method ([0046]), wherein, in a top view (Fig. 1), the second lower contact feature (Figs. 1/7G, CP2/115, second contact plug/lower wiring layer) and the third lower contact feature (Figs. 1/7, CP3/117, third contact plug/lower wiring layer) extend lengthwise along different directions (annotated Figure 1).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUANG as modified by ZHANG to incorporate the teachings of PARK such that the method, wherein, in a top view, the second lower contact feature and the third lower contact feature extend lengthwise along different directions, so that a metal-insulator-metal (MIM) capacitor may be effectively used in a semiconductor device instead of a metal-insulator-semiconductor (MIS) capacitor for dynamic random access memory (DRAM) applications (PARK, [0003-0004]).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20140159200 A1 – Figure 16
STATEMENT OF RELEVANCE – A cross-sectional view depicting a process flow for manufacturing stacked MIM capacitor structure.
US 20200035779 A1 – Figure 2
STATEMENT OF RELEVANCE – A flow chart of a method for forming an MIM structure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
