Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
In view of Applicant’s remarks and amendments to the claims, The Examiner withdraws the double patenting rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 20 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
This is because claim 20 recites the limitations:
“a first drain contact extending within the first drain region”
And
“a second drain contact extending within the second drain region”
These limitations are already included in claim 18 upon which claim 20 depends. These limitations fail to further limit the invention.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
This is because claim 20 recites the limitations:
“a first drain contact extending within the first drain region”
And
“a second drain contact extending within the second drain region”
It is not clear to the Examiner which “first drain” and which “second drain” Applicant is referring to. Applicant has introduced, “a first drain” and “a second drain” in claim 18 and the Examiner does not see any additional first drains or second drains in the Applicant’s specification or drawings. The Examiner believes Applicant forgot to remove the limitations from claim 20 which are now incorporated in claim 18 as the claim language is identical. For this reason, the Examiner interprets these elements as the same ones referenced in claim 18.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, and 14-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al US 20210265348 A1 in view of Ellis-Monaghan US 20120074502 A1. Xie et al and Ellis-Monaghan et al will be referenced to as Xie and Ellis-Monaghan henceforth.
Regarding Claim 1,
Xie teaches:
“An integrated circuit structure: (annotated FIG. 9 #1), comprising:
a vertical stack of devices ([0025]: An SFET may be a stack of a NFET on a PFET.) comprising a first device (PFET), and a second device above the first device (NFET),
wherein the first device comprises (i) a first source region (source/drain region 302, [0079]), (ii) a first drain region (annotated FIG. 9 #1), (iii) a first body comprising semiconductor material (semiconductor layers 108: The first body comprises 108 in the PFET.) laterally extending from the first source region to the first drain region (annotated FIG. 9 #1), (iv) a first source contact (first wrap-around contact 902, [0079]) coupled to the first source region (annotated FIG. 9 #1: 902 is in direct contact with the source and drain regions), the first source contact comprising a first conductive material ([0079]: 902 may be made of tungsten or cobalt.), and (v) a first drain contact (annotated FIG. 9 #1) coupled to the first drain region (annotated FIG. 9 #1: the drain contact is directly in contact with the drain region.), the first drain contact comprising the first conductive material (annotated FIG. 9 #1: The drain contact is 902.), and
wherein the second device comprises (i) a second source region (source and drain region 502, [0080], annotated FIG. 9 #1), (ii) a second drain region (annotated FIG. 9 #1), (iii) a second body comprising semiconductor material (semiconductor layers 108: The second body comprises 108 in the NFET.) laterally extending from the second source region to the second drain region (annotated FIG. 9 #1), (iv) a second source contact (second wrap-around contact 904, [0079], annotated FIG. 9 #1) coupled to the second source region (annotated FIG. 9 #1: 904 is in electric contact with 108 in the NFET.), (v) a second drain contact coupled to the second drain region (annotated FIG. 9 #1),”
Xie doesn’t substantially teach:
“the second source contact comprising a second conductive material, the second drain contact comprising the second conductive material, wherein the first conductive material is only a single metal that is elementally different from any metal of the second conductive material, or the first conductive material is a metal alloy that is elementally different from the second conductive material. ”
However, Ellis-Monaghan teaches:
“the second source contact comprising a second conductive material (Ellis-Monaghan: [0033], [0036-0037], FIG. 10, the NFET contact 120 (leftmost) may be made of a different metal than tungsten. 120 may be made of molybdenum silicide.), the second drain contact comprising the second conductive material (Ellis-Monaghan: [0033], [0036-0037], FIG. 10, the NFET contact 120 (rightmost) may be made of a different metal than tungsten. 120 may be made of molybdenum silicide.), ”
Xie and Ellis-Monaghan together teach:
“wherein the first conductive material is only a single metal that is elementally different from any metal of the second conductive material, or the first conductive material is a metal alloy that is elementally different from (Xie/Ellis-Monaghan: Xie: [0079]: the first conductive material may be tungsten or cobalt.; Ellis-Monaghan: [0033], [0036-0037], FIG. 10: The second conductive material may be MoS.) (Xie/Ellis-Monaghan: tungsten and cobalt are elementally different from molybdenum silicide.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Xie is modifiable in view of Ellis-Monaghan.
This is because imparting compressive stress to a channel of a PFET is advantageous for PFET devices. Further, imparting tensile stress to a channel of a NFET is advantageous for NFET devices. (Ellis-Monaghan: [0003]). These stresses are advantageous for their respective devices because these stresses improve the carrier mobility of the devices which in turn makes these devices more energy efficient.
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Annotated FIG. 9 #1
Regarding Claim 3,
Xie/Ellis-Monaghan teaches:
“The integrated circuit of claim 1, wherein the first device is a p-channel metal- oxide semiconductor (PMOS) device (Xie: [0025], annotated FIG. 9 #1: A PFET is a kind of PMOS.) and the first conductive material comprises one or both of tungsten and cobalt (Xie: [0079]: the first conductive material may be tungsten or cobalt.).”
Regarding Claim 4,
Xie/Ellis-Monaghan teaches:
“The integrated circuit of claim 1, wherein the second device is a n-channel metal-oxide semiconductor (NMOS) device (Xie: NFET, annotated FIG. 9 #1: A NFET is a kind of NMOS.) and the second conductive material comprises molybdenum (Ellis-Monaghan: [0033], [0036-0037], FIG. 10, the NFET contact 120 may be made of a different metal than tungsten. 120 may be made of molybdenum silicide.).”
Regarding Claim 5,
Xie/Ellis-Monaghan teaches:
“The integrated circuit of claim 1, wherein one of the first or second conductive material comprises one or both of tungsten and cobalt, (Xie: ([0079]: 902 may be made of tungsten or cobalt. Tungsten or cobalt are the first conductive material.), and wherein the other of the first or second conductive material comprises molybdenum (Ellis-Monaghan: [0033], [0036-0037], FIG. 10, the NFET contact 120 may be made of a different metal than tungsten. 120 may be made of molybdenum silicide. Molybdenum silicide is the second conductive material.).”
Regarding Claim 6,
Xie/Ellis-Monaghan teaches:
“The integrated circuit of claim 1, wherein the first conductive material induces one of compressive strain or tensile strain on the first body of the first device (Ellis-Monaghan: [0029], [0033], [0036-0037], FIG. 10: Tungsten imparts a compressive stress on the silicon in the PFET.), and the second conductive material induces the other of compressive strain or tensile strain on the second body of the second device (Ellis-Monaghan: [0029], [0033], [0036-0037], FIG. 10: MoS imparts a tensile stress on the NFET.)”
Regarding Claim 7,
Xie/Ellis-Monaghan teaches:
“The integrated circuit of claim 1, wherein the first conductive material induces compressive strain on the first body of the first device (Ellis-Monaghan: [0029], [0033], [0036-0037], FIG. 10: Tungsten imparts a compressive stress on the silicon in the PFET.), and the second conductive material induces tensile strain on the second body of the second device (Ellis-Monaghan: [0029], [0033], [0036-0037], FIG. 10: MoS imparts a tensile stress on the NFET.).”
Regarding Claim 14,
Xie/Ellis-Monaghan teaches:
“An integrated circuit structure comprising (Xie: annotated FIG. 9 #1):
a first transistor device (Xie: PFET) comprising a first source or drain contact (Xie: first wrap-around contact 902, [0079]: a first source contact.) coupled to a first source or drain region (Xie: source/drain region 302, [0079]: a first source region.) and a second source or drain contact (Xie: annotated FIG. 9 #1: a first drain contact.) coupled to a second source or drain region (Xie: annotated FIG. 9 #1: a first drain region.), the first source or drain contact and the second source or drain contact each comprising one or both of tungsten and cobalt and not comprising molybdenum (Xie: [0079]: a first source contact and a first drain contact are part of 902 which may be made of tungsten or cobalt.); and
a second transistor device (Xie: NFET) comprising a third source or drain contact (Xie: second wrap-around contact 904, [0079], annotated FIG. 9 #1: a second source contact.) coupled to a third source or drain region (Xie: source and drain region 502, [0080], annotated FIG. 9 #1: a second source region.) and a fourth source or drain contact (annotated FIG. 9 #1: a second drain contact.) coupled to a fourth source or drain region (Xie: annotated FIG. 9 #1: a second drain region.), the third source or drain contact comprising molybdenum and not comprising tungsten or cobalt (Ellis-Monaghan: [0033], [0036-0037], FIG. 10, the NFET contact 120 (rightmost) may be made of a different metal than tungsten. 120 may be made of molybdenum silicide. MoS is not tungsten or carbon.), wherein the first device and the second device are arranged in a vertical device stack (Xie: FIG. 9).”
Regarding Claim 15,
Xie/Ellis-Monaghan teaches:
“The integrated circuit structure of claim 14, wherein the second device is above the first device in the vertical device stack (Xie: FIG. 9).”
Regarding Claim 17,
Xie/Ellis-Monaghan teaches:
“The integrated circuit of claim 14, wherein the first transistor device is a p-type MOS (PMOS) device (Xie: [0025], annotated FIG. 9 #1: a PFET is a kind of PMOS.), and the second transistor device is an n-type MOS (NMOS) device (Xie: [0025] annotated FIG. 9 #1: a NFET is a kind of NMOS).”
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Xie/Ellish-Monaghan as applied to claims 1, 3-7, and 14-15 and 17 above, and further in view of Hussain et al (US 20140008606 A1). Hussain et al will be referenced to as Hussain henceforth.
Regarding Claim 8,
Xie/Ellis-Monaghan teaches:
“The integrated circuit of claim 1,”
Xie/Ellis-Monaghan doesn’t substantially teach:
“wherein a lateral distance between the first source contact and the first body is in the range of 3-12 nm (nanometers), and wherein a lateral distance between the second source contact and the second body is in the range of 3-12 nm.”
However, Hussain teaches:
“wherein a lateral distance between the first source contact and the first body is in the range of 3-12 nm (nanometers) (Hussain: annotated FIG. 2B #1: The figure is to scale and the measurement is from the center of the channel to the center of the source contact. One of ordinary skill in the art would consider this distance between a S/D contact and a channel layer when constructing their device.), and wherein a lateral distance between the second source contact and the second body is in the range of 3-12 nm (Hussain: annotated FIG. 2B #1: The figure is to scale and the measurement is from the center of the channel to the center of the source contact. One of ordinary skill in the art would consider this distance between a S/D contact and a channel layer when constructing their device.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Xie/Ellis-Monaghan is modifiable in view of Hussain. This is because Xie/Ellis-Monaghan does not explicitly teach the claimed range. However, Hussain teaches a lateral distance between the source contact and the center of the channel to be 10nm. This lies within the claimed range and by MPEP 2144.05. I a prima facie case of obviousness exists.
Claims 9-11, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie/Ellis-Monaghan as applied to claims 1, 3-7, and 14-15 and 17 above, and further in view of Xie #2 et al US 20230307296 A1. Xie #2 et al will be referenced to as Xie #2 henceforth.
Regarding Claim 9,
Xie/Ellis-Monaghan teaches:
“The integrated circuit of claim 1,”
Xie/Ellis-Monaghan doesn’t substantially teach:
“wherein the first source contact extends within the first source region, and wherein first drain contact extends within the first drain region.”
However, Xie #2 teaches:
“wherein the first source contact extends within the first source region (Xie #2: region 441a, [0031], FIG. 5N), and wherein first drain contact extends within the first drain region (Xie #2: region 441b, [0033], FIG. 5N).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Xie/Ellis-Monaghan is modifiable in view of Xie #2.
This is because Xie/Ellis-Monaghan teaches S/D regions laterally surrounded by an S/D contact. Xie/Ellis-Monaghan doesn’t substantively teach S/D regions which are continuously connected along a short side of a nanosheet. Xie #2 teaches S/D regions laterally surrounded by an S/D contact. Xie #2 further teaches S/D regions which are continuously connected along a short side of a nanosheet. Because both Xie/Ellis-Monaghan and Xie #2 have S/D regions laterally surrounded by an S/D contact, one of ordinary skill in the art would have deemed it obvious to substitute the S/D regions laterally surrounded by an S/D contact of Xie/Ellis-Monaghan for S/D regions which are continuously connected along a short side of a nanosheet of Xie #2for the predictable result of S/D regions with a compressive or tensile stress which increase carrier mobility and therefore the energy efficiency of the device.
Regarding Claim 10,
Xie/Ellis-Monaghan/Xie #2 teaches:
“The integrated circuit of claim 1,wherein the first source contact extends within and through the first source region (Xie #2: region 441a, [0031], FIG. 5N), such that a bottom surface of the first source contact and a bottom surface of the first source region are coplanar (Xie #2: FIG. 5N).”
Regarding Claim 11,
Xie/Ellis-Monaghan/Xie #2 teaches:
“The integrated circuit of claim 1, further comprising:
an isolation region (Xie: isolation dielectric 402, [0059], FIG. 9) between the first source region and the second source region (Xie: annotated FIG. 9 #1) , wherein the first source contact extends within and through the first source region (Xie #2: FIG. 5N), such that a bottom surface of the first source contact is in contact with the isolation region (Xie #2: FIG. 5N).”
Regarding Claim 18,
Xie/Ellis-Monaghan/Xie #2 teaches:
“An integrated circuit structure, comprising (Xie: annotated FIG. 9 #1):
a first device (Xie: PFET) comprising (i) a first source region (Xie: source/drain region 302, [0079]: a first source region.), (ii) a first drain region (Xie: annotated FIG. 9 #1: a first drain region.), (iii) a first nanoribbon (semiconductor layers 108: The first body comprises 108 in the PFET.) laterally extending from the first source region to the first drain region (Xie: annotated FIG. 9 #1), [[and]] (iv) a first source contact (Xie: a first wrap-around contact 902, [0079]: a first source contact) extending within the first source region (Xie #2: region 441a, [0031], FIG. 5N), region, and (v) a first drain contact (Xie: annotated FIG. 9 #1: a first drain contact.) extending within the first drain region (Xie #2: region 441b, [0033], FIG. 5N); and
a second device (Xie: NFET, [0025], annotated FIG. 9 #1) comprising (i) a second source region (Xie: source and drain region 502, [0080], annotated FIG. 9 #1: a second source region.), (ii) a second drain region (Xie: annotated FIG. 9 #1: a second drain region.), (iii) a second nanoribbon laterally extending from the second source region to the second drain region (semiconductor layers 108: The second body comprises 108 in the NFET.), and (iv) a second source contact (Xie: second wrap-around contact 904, [0079], annotated FIG. 9 #1: a second source contact.) extending within the second source region (Xie/Xie #2: one of ordinary skill in the art would recognize that upon the combination of Xie and Xie #2, Xie would have continuous source and drain regions. Therefore, the second source contact and the second drain contact would extend within the second source region and the second drain region respectively.) and (v) a second drain contact extending within the second drain region (Xie/Xie #2: one of ordinary skill in the art would recognize that upon the combination of Xie and Xie #2, Xie would have continuous source and drain regions. Therefore, the second source contact and the second drain contact would extend within the second source region and the second drain region respectively.), wherein the first device and the second device are arranged in a vertical device stack (Xie: annotated FIG. 9 #1), wherein the first source contact and the first drain contact comprise a first conductive material that induces compressive strain within the first nanoribbon (Ellis-Monaghan: [0029], [0033], [0036-0037], FIG. 10: Tungsten imparts a compressive strain on the PFET.), and the second source contact and the second drain contact comprise a second conductive material that induces tensile strain within the second nanoribbon, (Ellis-Monaghan: [0033], [0036-0037], FIG. 10, MoS may impart a tensile strain on the NFET.) wherein the first conductive material is only a single metal that is elementally different from any metal of the second conductive material, or the first conductive material is a metal alloy that is elementally different from the second conductive material (Ellis-Monaghan: [0029], [0033], [0036-0037], FIG. 10: The first metal may be tungsten. The second conductive material may be molybdenum silicide (MoS). Tungsten is elementally different from any metal of MoS.).”
Regarding Claim 20,
Xie/Ellis-Monaghan/Xie #2 teaches:
“The integrated circuit of claim 18, wherein:
the first device further comprises a first drain contact extending within the first drain region (Xie #2: region 441b, [0033], FIG. 5N);
the second device further comprises a second drain contact extending within the second drain region (Xie/Xie #2: one of ordinary skill in the art would recognize that upon the combination of Xie and Xie #2, Xie would have continuous source and drain regions. Therefore, the second source contact and the second drain contact would extend within the second source region and the second drain region respectively.); and
the first drain contact induces compressive strain within the first body (Xie/Ellis-Monaghan: Xie: the first drain contact is made of tungsten.; Ellis-Monaghan: [0029], [0033], [0036-0037], FIG. 10: Tungsten imparts a compressive strain on the PFET.), and the second drain contact induces tensile strain within the second body (Ellis-Monaghan: [0033], [0036-0037], FIG. 10, MoS may impart a tensile strain on the NFET.).”
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Xie/Ellis-Monaghan as applied to claims above, and further in view of Shiraki (US 20210249401 A1).
Regarding Claim 12,
Xie/Ellis-Monaghan/Xie #2 teaches:
“The integrated circuit structure of claim 11,”
Xie/Ellis-Monaghan doesn’t substantially teach:
“wherein a bottom surface of the first source contact is in contact with a top surface of the second source contact.”
However, Shiraki teaches:
“wherein a bottom surface of the first source contact is in contact with a top surface of the second source contact (Shiraki: local interconnect 388 and 386 ,[0037], FIGs. 11-14.).”
It would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Xie/Ellis-Monaghan is modifiable in view of Shiraki.
This is because one of ordinary skill in the art would recognize that contacting a surface of the first source or drain contact with a surface of the second source or drain makes it possible for power to flow into an NFET and PFET while minimizing the amount of metal used for each contact. One of ordinary skill in the art would find minimizing the amount of metal used to be beneficial for reducing the cost of a semiconductor device.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Xie/Ellis-Monaghan as applied to claims 1, 3-7, and 14-15 and 17---- above, and further in view of Shiraki.
Regarding Claim 16,
Xie/Ellis-Monaghan teaches:
“The integrated circuit structure of claim 14,”
Xie/Ellis-Monaghan doesn’t substantially teach:
“wherein a surface of the first source or drain contact is in contact with a surface of the second source or drain contact”
However, Shiraki teaches:
“wherein a surface of the first source or drain contact is in contact with a surface of the second source or drain contact (Shiraki: local interconnect 388 and 386 ,[0037], FIGs. 11-14.)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Xie/Ellis-Monaghan is modifiable in view of Shiraki.
This is because one of ordinary skill in the art would recognize that contacting a surface of the first source or drain contact with a surface of the second source or drain makes it possible for power to flow into an NFET and PFET while minimizing the amount of metal used for each contact. One of ordinary skill in the art would find minimizing the amount of metal used to be beneficial for reducing the cost of a semiconductor device.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Xie/Ellis-Monaghan/Xie #2 as applied to claims 9-11, 18 and 20 above, and further in view of Hussain
Regarding Claim 19,
Xie/Ellis-Monaghan/Xie #2 teaches:
“The integrated circuit of claim 18,”
Xie/Ellis-Monaghan/Xie #2 doesn’t substantially teach:
“wherein a lateral distance between the first source contact and the first body is in the range of 3-12 nm (nanometers), and wherein a lateral distance between the second source contact and the second body is in the range of 3-12 nm.”
However, Hussain teaches:
“wherein a lateral distance between the first source contact and the first body is in the range of 3-12 nm (nanometers) (Hussain: annotated FIG. 2B #1: The figure is to scale and the measurement is from the center of the channel to the center of the source contact. One of ordinary skill in the art would consider this distance between a S/D contact and a channel layer when constructing their device.), and wherein a lateral distance between the second source contact and the second body is in the range of 3-12 nm (Hussain: annotated FIG. 2B #1: The figure is to scale and the measurement is from the center of the channel to the center of the source contact. One of ordinary skill in the art would consider this distance between a S/D contact and a channel layer when constructing their device.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Xie/Ellis-Monaghan/Xie #2 is modifiable in view of Hussain.
This is because Xie/Ellis-Monaghan/Xie #2 does not explicitly teach the claimed range. However, Hussain teaches a lateral distance between the source contact and the center of the channel to be 10nm. This lies within the claimed range and by MPEP 2144.05. I a prima facie case of obviousness exists.
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Allowable Subject Matter
Claims 13 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 13,
Xie/Ellis-Monaghan/Hussain/Shiraki/Xie #2 fails to explicitly teach :
“wherein a bottom surface of the first drain contact is in contact with a top surface of the second drain contact”
In view of the rest of the limitations of claim 13.
Xie/Ellis-Monaghan/Hussain/Shiraki/Xie #2 fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record. Shiraki shows two source regions contacting each other in FIG. 14 and an isolation layer in FIG. 11. However, Shiraki does not show two drain regions contacting each other.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Xie/Ellis-Monaghan/Hussain/Shiraki/Xie #2 to reach all of the limitations of the claim.
Regarding Claim 21,
Xie/Ellis-Monaghan/Hussain/Shiraki/Xie #2 fails to explicitly teach :
“wherein the first conductive material consists of tungsten or cobalt, and the second conductive material consists of molybdenum.”
In view of the rest of the limitations of claim 1.
Xie/Ellis-Monaghan/Hussain/Shiraki/Xie #2 fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record. Namely the prior art of record doesn’t teaches using tungsten, molybdenum, or cobalt for both the PMOS and NMOS S/D contacts, but not specifically S/D contacts consisting of tungsten or cobalt for a PMOS and S/D contacts consisting molybdenum for a NMOS.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Xie/Ellis-Monaghan/Hussain/Shiraki/Xie #2 to reach all of the limitations of the claim.
Response to Arguments
Applicant’s amendments to the Claims have overcome the Examiner’s 102(a)(1) and 103 rejections.
Applicant’s arguments, with respect to the rejection(s) of claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Xie, Ellis-Monaghan, and Xie #2 .
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812