Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 7 - 12, and 17 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over US20220075916A1 (Zhang) in view of US20070157133A1 (Cheng).
In regards to claim 1 (Zhang) shows:
A method for semiconductor device simulation comprising: Zhang [0050] teaches a method for semiconductor device simulation.
receiving a device structure; Zhang [0027] teaches receiving a device structure for a microelectronic device that undergoes lithography and plasma process steps.
generating a device structure mesh of a first resolution for the device structure; Zhang [0052] teaches generating a device structure mesh at a first grid size, where the grid size is the degree of mesh refinement or grid resolution.
simulating electrical behavior of the device structure using the device structure mesh; and Zhang [0050] teaches simulating on-wafer electrical performance of the device structure by applying lithography and plasma process models during microelectronics fabrication.
Zhang differs from the claimed invention in that it does not explicitly disclose adaptively adjusting the device structure mesh during the simulating of the electrical behavior of the device structure, wherein the adaptively adjusting the device structure mesh includes performing a multi-level restriction-prolongation (MLRP) process that includes at least one restriction-prolongation cycle; wherein a restriction process of the restriction-prolongation cycle manipulates the device structure mesh to decrease the first resolution to a second resolution; and a prolongation process of the restriction-prolongation cycle manipulates the device structure mesh of the second resolution to increase the second resolution to a third resolution.
Cheng teaches adaptively adjusting the device structure mesh during the simulating of the electrical behavior of the device structure, wherein the adaptively adjusting the device structure mesh includes performing a multi-level restriction-prolongation (MLRP) process that includes at least one restriction-prolongation cycle; Cheng [0023] and [0043] teach a multi-level restriction-prolongation process having at least one restriction-prolongation cycle, in which residual errors are propagated from a fine grid to successively coarser grids through restriction mapping and solutions are propagated back through interpolation mapping in a single cycle, repeated until the solution converges.
Cheng teaches wherein a restriction process of the restriction-prolongation cycle manipulates the device structure mesh to decrease the first resolution to a second resolution; Cheng [0023] and [0024] teach a restriction process that maps the mesh from one grid level to a coarser grid level having fewer nodes, decreasing the first resolution to a second resolution.
Cheng teaches and a prolongation process of the restriction-prolongation cycle manipulates the device structure mesh of the second resolution to increase the second resolution to a third resolution. Cheng [0024] and [0043] teach a prolongation process that maps the mesh by interpolation from a coarser grid level back to a finer grid level, increasing the second resolution to a third resolution.
It would have been obvious to one of ordinary skill in the art to combine Zhang and Cheng to accelerate convergence of the semiconductor device simulation by correcting low-frequency error on successively coarser grids, with a reasonable expectation of success as both references address mesh-based simulation of a semiconductor structure.
In regards to claim 2 (Zhang) does not show: wherein the third resolution is within a given range of the first resolution;
Cheng teaches wherein the third resolution is within a given range of the first resolution. Cheng [0043] teaches that the interpolation returns the solution from the coarsest grid back to the original finest grid, such that the third resolution is within a given range of the first resolution.
It would have been obvious to one of ordinary skill in the art to combine Zhang and Cheng to accelerate convergence of the semiconductor device simulation by correcting low-frequency error on successively coarser grids, with a reasonable expectation of success as both references address mesh-based simulation of a semiconductor structure.
In regards to claim 4 (Zhang) shows the method of claim 1:
further comprising parallelizing the MLRP process on a hardware accelerator of a semiconductor device simulation system. Zhang [0046] teaches parallelizing the process on a hardware accelerator of the semiconductor device simulation system using single or multiple computer systems and parallel processors.
In regards to claim 7 (Zhang) shows the method of claim 1:
further comprising solving a system matrix for the adjusted device structure mesh after performing the MLRP process. Zhang [0071] and [0072] teach solving a system matrix for the adjusted device structure mesh in an iterative fashion after adjusting the mesh.
In regards to claim 8 (Zhang) does not show: solving a system matrix for the adjusted device structure mesh after performing the restriction process;
Cheng teaches solving a system matrix for the adjusted device structure mesh after performing the restriction process. Cheng [0024] and [0026] teach solving the system matrix at each coarser grid level after performing the restriction process.
It would have been obvious to one of ordinary skill in the art to combine Zhang and Cheng to accelerate convergence of the semiconductor device simulation by correcting low-frequency error on successively coarser grids, with a reasonable expectation of success as both references address mesh-based simulation of a semiconductor structure.
In regards to claim 9 (Zhang) does not show: solving a system matrix for the adjusted device structure mesh after performing the prolongation process;
Cheng teaches solving a system matrix for the adjusted device structure mesh after performing the prolongation process. Cheng [0026] and [0043] teach solving the system matrix at each finer grid level after performing the prolongation process.
It would have been obvious to one of ordinary skill in the art to combine Zhang and Cheng to accelerate convergence of the semiconductor device simulation by correcting low-frequency error on successively coarser grids, with a reasonable expectation of success as both references address mesh-based simulation of a semiconductor structure.
In regards to claim 10 (Zhang) shows the method of claim 1:
further comprising modifying the device structure based on the simulated electrical behavior. Zhang [0088] and [0089] teach modifying the device structure based on the simulated electrical behavior.
In regards to claim 11 (Zhang) shows:
A semiconductor device simulation system comprising: Zhang [0033] and [0050] teach a semiconductor device simulation system.
a central processing unit (CPU) connected to a memory; Zhang [0033] teaches a central processing unit connected to a memory.
a hardware accelerator connected to the CPU and the memory; and Zhang [0046] teaches a hardware accelerator connected to the CPU and the memory.
wherein the CPU, the hardware accelerator, and the memory are configured to perform a set of operations to simulate electrical behavior of a semiconductor device, wherein the set of operations include: generating a fine-grid device structure mesh for a device structure, Zhang [0050] and [0052] teach the CPU, the hardware accelerator, and the memory configured to perform operations that simulate electrical behavior of a semiconductor device, including generating a fine-grid device structure mesh for a device structure.
solving a system matrix corresponding with fine-grid device structure mesh, Zhang [0072] teaches solving a system matrix corresponding with the fine-grid device structure mesh.
wherein the restricting and the prolongating are at least partially parallelized on the hardware accelerator, Zhang [0046] teaches that the operations are at least partially parallelized on the hardware accelerator.
Zhang differs from the claimed invention in that it does not explicitly disclose if a solution provided by solving the system matrix is not converged: restricting and prolongating the fine-grid mesh at least once; such that the fine-grid device structure mesh is manipulated into a coarse-grid device structure mesh during the restricting and the coarse-grid device structure mesh is manipulated into a restricted, fine-grid device structure mesh during the prolongating; and solving a system matrix corresponding with the restricted and prolongated fine-grid device structure mesh.
Cheng teaches if a solution provided by solving the system matrix is not converged: restricting and prolongating the fine-grid mesh at least once, Cheng [0043] teaches that, if a solution provided by solving the system matrix is not converged, restricting and prolongating the fine-grid mesh at least once by iterating the multigrid cycle until the residual error falls below a threshold.
Cheng teaches such that the fine-grid device structure mesh is manipulated into a coarse-grid device structure mesh during the restricting and the coarse-grid device structure mesh is manipulated into a restricted, fine-grid device structure mesh during the prolongating, Cheng [0024] teaches that the fine-grid mesh is manipulated into a coarse-grid mesh during the restriction and the coarse-grid mesh is manipulated into a restricted, fine-grid mesh during the interpolation.
Cheng teaches solving a system matrix corresponding with the restricted and prolongated fine-grid device structure mesh. Cheng [0024] and [0026] teach solving a system matrix corresponding with the restricted and prolongated fine-grid mesh at each grid level.
It would have been obvious to one of ordinary skill in the art to combine Zhang and Cheng to accelerate convergence of the semiconductor device simulation by correcting low-frequency error on successively coarser grids, with a reasonable expectation of success as both references address mesh-based simulation of a semiconductor structure.
In regards to claim 12 (Zhang) shows the semiconductor device simulation system of claim 11:
wherein the restricting and the prolongating are performed partially by the CPU. Zhang [0046] teaches that operations are performed partially by the CPU.
In regards to claim 17 (Zhang) shows the semiconductor device simulation system of claim 11:
wherein the CPU, the hardware accelerator, and the memory are provided by at least one CPU chip, at least one GPU chip, and at least one memory chip, respectively, of a three-dimensional, multichip package. Zhang [0046] and [0047] teach providing the CPU, the hardware accelerator, and the memory as at least one CPU chip, at least one GPU chip, and at least one memory chip of a three-dimensional multichip package.
In regards to claim 18 (Zhang) shows:
A non-transitory computer-readable storage medium storing instructions and causing a computer to perform a method for simulating electrical behavior of a semiconductor device, the method comprising: Zhang [0047] teaches a non-transitory computer-readable storage medium storing instructions that cause a computer to perform a method for simulating electrical behavior of a semiconductor device.
generating a device structure mesh for a device structure; Zhang [0052] teaches generating a device structure mesh for a device structure.
solving a system matrix corresponding with device structure mesh; and Zhang [0072] teaches solving a system matrix corresponding with the device structure mesh.
assigning the restricting and the prolongating to parallel processing threads of a hardware accelerator of the computer, Zhang [0046] teaches assigning the operations to parallel processing threads of a hardware accelerator of the computer.
Zhang differs from the claimed invention in that it does not explicitly disclose if a solution provided by solving the system matrix is not converged: restricting and prolongating the device structure mesh at least once, wherein the restricting includes a fine-to-coarse resolution adjustment to the device structure mesh and the prolongating includes a coarse-to-fine resolution adjustment to the device structure mesh; and solving a system matrix corresponding with the restricted and prolongated device structure mesh.
Cheng teaches if a solution provided by solving the system matrix is not converged: restricting and prolongating the device structure mesh at least once, wherein the restricting includes a fine-to-coarse resolution adjustment to the device structure mesh and the prolongating includes a coarse-to-fine resolution adjustment to the device structure mesh, Cheng [0024] teaches that, if a solution is not converged, restricting and prolongating the mesh at least once, where the restriction is a fine-to-coarse resolution adjustment and the interpolation is a coarse-to-fine resolution adjustment to the mesh.
Cheng teaches solving a system matrix corresponding with the restricted and prolongated device structure mesh. Cheng [0024] and [0026] teach solving a system matrix corresponding with the restricted and prolongated device structure mesh.
It would have been obvious to one of ordinary skill in the art to combine Zhang and Cheng to accelerate convergence of the semiconductor device simulation by correcting low-frequency error on successively coarser grids, with a reasonable expectation of success as both references address mesh-based simulation of a semiconductor structure.
In regards to claim 19 (Zhang) shows the non-transitory computer-readable storage medium of claim 18:
wherein the method further comprises assigning a portion of the restricting and the prolongating to a central processing unit of the computer. Zhang [0046] teaches assigning a portion of the operations to a central processing unit of the computer.
In regards to claim 20 (Zhang) does not show: wherein the method further comprises performing more than one cycle of the restricting and the prolongating;
Cheng teaches wherein the method further comprises performing more than one cycle of the restricting and the prolongating. Cheng [0043] teaches performing more than one cycle of the restriction and the prolongation by iterating the multigrid cycle several times until the solution converges.
It would have been obvious to one of ordinary skill in the art to combine Zhang and Cheng to accelerate convergence of the semiconductor device simulation by correcting low-frequency error on successively coarser grids, with a reasonable expectation of success as both references address mesh-based simulation of a semiconductor structure.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Cheng, and further in view of US20020042698A1 (Meuris).
In regards to claim 3 (Zhang modified by Cheng) does not show: refining the device structure mesh of the first resolution before simulating the electrical behavior of the device structure using the mesh; and wherein the refining includes manipulating a region of the device structure mesh to change the first resolution to a fourth resolution different than the first resolution;
Meuris teaches further comprising refining the device structure mesh of the first resolution before simulating the electrical behavior of the device structure using the mesh; Meuris [0110] and [0329] teach refining the device structure mesh of the first resolution before simulating the electrical behavior of the device structure using the mesh.
Meuris teaches wherein the refining includes manipulating a region of the device structure mesh to change the first resolution to a fourth resolution different than the first resolution. Meuris [0336] through [0340] teach that the refining includes manipulating a region of the mesh to change the first resolution to a fourth resolution different than the first resolution.
It would have been obvious to one of ordinary skill in the art to further combine Zhang and Cheng with Meuris to refine a region of the mesh before simulation, with a reasonable expectation of success as the references address mesh-based semiconductor device simulation.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Cheng, and further in view of US20140052965A1 (Sarel).
In regards to claim 5 (Zhang modified by Cheng) does not show: performing the MLRP process on a graphics processing unit (GPU) when the first resolution of the device structure mesh is greater than or equal to a threshold resolution; and performing the MLRP process on a central processing unit when the first resolution of the device structure mesh is less than the threshold resolution;
Sarel teaches performing the MLRP process on a graphics processing unit (GPU) when the first resolution of the device structure mesh is greater than or equal to a threshold resolution; Sarel [0035] teaches performing the process on a graphics processing unit when a value is greater than or equal to a threshold, by sending the work to the GPU when the GPU budget is greater than the threshold T.
Sarel teaches and performing the MLRP process on a central processing unit when the first resolution of the device structure mesh is less than the threshold resolution. Sarel [0035] and [0046] teach performing the process on a central processing unit when the value is less than the threshold, by sending the work to the CPU when the budget is less than the threshold T.
It would have been obvious to one of ordinary skill in the art to further combine Zhang and Cheng with Sarel to route the process to a graphics processing unit or a central processing unit based on a threshold, with a reasonable expectation of success as the references address distributing computation across parallel processing hardware.
Claims 6, 13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Cheng, and further in view of US20210056446A1 (Dally).
In regards to claim 6 (Zhang modified by Cheng) does not show: performing the MLRP process on arithmetic logic units having different accuracies;
Dally teaches further comprising performing the MLRP process on arithmetic logic units having different accuracies. Dally [0108] teaches performing the process on arithmetic logic units having different accuracies, including single-precision, double-precision, and integer arithmetic logic units within the processing cores.
It would have been obvious to one of ordinary skill in the art to further combine Zhang and Cheng with Dally to perform the process on a hardware accelerator having arithmetic logic units of different precisions organized as a cluster of graphics processing units, with a reasonable expectation of success as the references address parallel hardware acceleration of mesh-based computation.
In regards to claim 13 (Zhang modified by Cheng) does not show: wherein the hardware accelerator includes arithmetic logic units having different precisions and the restricting and prolongating are parallelized on the arithmetic logic units having different precisions;
Dally teaches wherein the hardware accelerator includes arithmetic logic units having different precisions and the restricting and prolongating are parallelized on the arithmetic logic units having different precisions. Dally [0108] and [0093] teach a hardware accelerator that includes arithmetic logic units having different precisions, such as single-precision and double-precision floating point units, on which the operations are parallelized.
It would have been obvious to one of ordinary skill in the art to further combine Zhang and Cheng with Dally to perform the process on a hardware accelerator having arithmetic logic units of different precisions organized as a cluster of graphics processing units, with a reasonable expectation of success as the references address parallel hardware acceleration of mesh-based computation.
In regards to claim 16 (Zhang modified by Cheng) does not show: wherein the hardware accelerator is a cluster of graphic processing units (GPUs);
Dally teaches wherein the hardware accelerator is a cluster of graphic processing units (GPUs). Dally [0079] and [0121] teach a hardware accelerator that is a cluster of graphics processing units, in which multiple parallel processing units are combined with a CPU by a high-speed interconnect.
It would have been obvious to one of ordinary skill in the art to further combine Zhang and Cheng with Dally to perform the process on a hardware accelerator having arithmetic logic units of different precisions organized as a cluster of graphics processing units, with a reasonable expectation of success as the references address parallel hardware acceleration of mesh-based computation.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Cheng, and further in view of US20070047810A1 (Grady).
In regards to claim 14 (Zhang modified by Cheng) does not show: wherein the restricting and prolongating the fine-grid device structure mesh at least once includes generating the coarse-grid device structure mesh by aggregating mesh elements of the fine-grid device structure mesh; solving a system matrix corresponding with the coarse-grid device structure mesh; and generating the restricted, fine-grid device structure mesh by interpolating mesh elements of the coarse-grid device structure mesh;
Grady teaches generating the coarse-grid device structure mesh by aggregating mesh elements of the fine-grid device structure mesh; Grady [0046] teaches generating the coarse-grid device structure mesh by aggregating mesh elements of the fine-grid device structure mesh.
Grady teaches solving a system matrix corresponding with the coarse-grid device structure mesh; and Grady [0046] teaches solving a system matrix corresponding with the coarse-grid device structure mesh.
Grady teaches generating the restricted, fine-grid device structure mesh by interpolating mesh elements of the coarse-grid device structure mesh. Grady [0054] teaches generating the restricted, fine-grid device structure mesh by interpolating mesh elements of the coarse-grid device structure mesh.
It would have been obvious to one of ordinary skill in the art to further combine Zhang and Cheng with Grady to implement the coarse-grid mesh using aggregation and interpolation operators, with a reasonable expectation of success as the references address multi-level mesh manipulation for simulation.
In regards to claim 15 (Zhang modified by Cheng) does not show: if an error associated with the solving the system matrix corresponding with the first coarse-grid device structure mesh is within an error tolerance, generating the restricted and prolongated fine-grid device structure mesh by interpolating first mesh elements of the first coarse-grid device structure mesh; and if the error associated with the solving the system matrix corresponding with the first coarse-grid device structure mesh is not within the error tolerance, generating a second coarse-grid device structure mesh by aggregating first mesh elements of the first coarse-grid device structure mesh and generating the restricted and prolongated fine-grid device structure mesh by interpolating second mesh elements of the second coarse-grid device structure mesh;
Grady teaches if an error associated with the solving the system matrix corresponding with the first coarse-grid device structure mesh is within an error tolerance, generating the restricted and prolongated fine-grid device structure mesh by interpolating first mesh elements of the first coarse-grid device structure mesh; and Grady [0046] and [0054] teach that, if an error associated with solving the system matrix for the first coarse-grid device structure mesh is within an error tolerance, generating the restricted and prolongated fine-grid device structure mesh by interpolating first mesh elements of the first coarse-grid device structure mesh.
Grady teaches if the error associated with the solving the system matrix corresponding with the first coarse-grid device structure mesh is not within the error tolerance, generating a second coarse-grid device structure mesh by aggregating first mesh elements of the first coarse-grid device structure mesh and generating the restricted and prolongated fine-grid device structure mesh by interpolating second mesh elements of the second coarse-grid device structure mesh. Grady [0046] and [0054] teach that, if the error is not within the error tolerance, generating a second coarse-grid device structure mesh by aggregating first mesh elements of the first coarse-grid device structure mesh and generating the restricted and prolongated fine-grid device structure mesh by interpolating second mesh elements of the second coarse-grid device structure mesh.
It would have been obvious to one of ordinary skill in the art to further combine Zhang and Cheng with Grady to implement the coarse-grid mesh using aggregation and interpolation operators, with a reasonable expectation of success as the references address multi-level mesh manipulation for simulation.
Response to Arguments
Applicant's arguments filed on January 20, 2026 have been fully considered but are not persuasive for the reasons set forth below.
Applicant argues that Choi is non-analogous art directed to fluid flow simulation. This rejection withdraws Choi and relies on Cheng, which is directed to circuit network analysis of an on-chip semiconductor network using an algebraic multigrid method. Cheng is in the same field of endeavor as the claimed semiconductor device simulation and is reasonably pertinent to the problem of accelerating a mesh-based simulation of a semiconductor structure. The non-analogous-art argument is therefore moot.
Applicant argues that Zhang already solves the computational-efficiency problem and that combining Zhang with a multigrid reference is impermissible hindsight. The rationale for the combination is drawn from Cheng, not from Applicant's disclosure. Zhang teaches a one-way resolution-enhancement model, while Cheng teaches a multi-level restriction-prolongation cycle that corrects low-frequency error on successively coarser grids to accelerate convergence. A person of ordinary skill in the art would combine these teachings to obtain the acceleration that Zhang alone does not provide.
Applicant argues that the cited art fails to teach the multi-level restriction-prolongation limitations. Cheng [0023], [0024], and [0043] teach a restriction process that maps the mesh from a fine grid to a coarser grid and a prolongation process that maps the mesh by interpolation from a coarser grid back to a finer grid, iterated as a restriction-prolongation cycle until the solution converges. These teachings meet the multi-level restriction-prolongation limitations as claimed. The rejections are maintained.
Conclusion
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/ANWER AHMED ALAWDI/
Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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