DETAILED ACTION
This Office Action is responsive to the Applicant’s communication filed 6 August 2026. In view of this communication, claims 1-13 and 15-25 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 12-13 and 15-22 were withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4 August 2025.
Response to Arguments
Applicant’s arguments, see the Remarks, filed 6 August 2026f, with respect to the rejection(s) of claim(s) 1-11 and 23-25 under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ma et al.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-7, 23, and 25 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ma et al. (US 2011/0147059 A1), hereinafter referred to as Ma et al.
Regarding claim 1, Ma et al. teaches a package substrate, comprising:
a core (150) (Fig. 1B and paragraph 32: core layer 150), comprising:
a first sub-core layer (1057a) (Figs. 10E-10G and paragraphs 93-95: first glass layer 1057a);
a second sub-core layer (1057b) (Figs. 10E-10G and paragraphs 93-95: second glass layer 1057b coupled to glass layer 1057a);
a via (1065) through the first sub-core layer (1057a) and the second sub-core layer (1057b) (Figs. 10E-10G and paragraphs 93-94: thru-holes 1065 formed in first and second glass layers 1057a, 1057b), wherein the via (1065) is a single structure continuous through the first sub-core layer (1057a) and the second sub-core layer (1057b) (Fig. 1B and paragraph 39: the via extends continuously through core layers) and comprises a first portion having a first hourglass shape in the first sub-core layer (1057a) and a second portion having a second hourglass shape in the second sub-core layer (1057b) (see Figs. 10E-10G and paragraphs 93-94), the first hourglass shape and the second hourglass shape completely filled with a conductive material in a cross-sectional perspective filled (paragraph 35: the thru-holes are filled by conductive material), the first hourglass shape having a top width the same as a bottom width, and the second hourglass shape having a top width the same as a bottom width (see Figs. 10E-10F and paragraphs 93-94: the top 1091 of one through hole 1065 corresponds to the bottom 1093 of the thru-hole 1065 above it, such that they are of the same diameter);
a front-side buildup layer (130) over the core (150) (Fig. 1B and paragraph 39); and
a backside buildup layer (140) under the core (150) (Fig. 1B and paragraph 39).
Regarding claim 2, Ma et al. teaches the package substrate of claim 1, further comprising: an adhesive (1058) between the first sub-core layer (1057a) and the second sub-core layer (1057b) (Figs. 10E-10G and paragraphs 93-97: bonding layer 1058).
Regarding claim 4, Ma et al. teaches the package substrate of claim 1, wherein a thickness of the first sub-core layer (1057a) and a thickness of the second sub-core layer (1057b) are substantially similar (paragraph 40: the glass layers may all have the same thickness).
Regarding claim 5, Ma et al. teaches the package substrate of claim 1, wherein a thickness of the first sub-core layer (1057a) and the second sub-core layer (1057b) are approximately 100µm or less (paragraph 40: the glass layers may be 50µm thick).
Regarding claim 6, Ma et al. teaches the package substrate of claim 1, wherein a thickness of the first sub-core layer (1057a) is different than a thickness of the second sub-core layer (1057b) (paragraph 40: the glass layers may each have a different thickness).
Regarding claim 7, Ma et al. teaches the package substrate of claim 1, wherein the core (150) further comprises:
A third sub-core layer (1057a) (Fig. 10F and paragraph 94: second two-layer structure comprises an additional glass layer 1057a);
A fourth sub-core layer (1057b) (Fig. 10F and paragraph 94: second two-layer structure comprises an additional glass layer 1057b), wherein the via (1065) passes through the third sub-core layer (1057a) and the fourth sub-core layer (1057b) (Fig. 10F and paragraph 94: the thru-holes 1065 extend through the additional two-layer structure 1008b, which comprises glass layers 1057a, 1057b).
Regarding claim 23, Ma et al. teaches an electronic system, comprising:
a board (see Fig. 1G and paragraph 38: the lower set of electrically conductive terminals 125 is designed to be mated to a mainboard, motherboard, or another circuit board);
a package substrate (100), coupled to the board, wherein the package substrate (100) comprises:
a core (150) (Fig. 1B and paragraph 32: core layer 150), comprising:
a first sub-core layer (1057a) (Figs. 10E-10G and paragraphs 93-95: first glass layer 1057a);
a second sub-core layer (1057b) (Figs. 10E-10G and paragraphs 93-95: second glass layer 1057b coupled to glass layer 1057a);
a via (1065) through the first sub-core layer (1057a) and the second sub-core layer (1057b) (Figs. 10E-10G and paragraphs 93-94: thru-holes 1065 formed in first and second glass layers 1057a, 1057b), wherein the via (1065) is a single structure continuous through the first sub-core layer (1057a) and the second sub-core layer (1057b) (Fig. 1B and paragraph 39: the via extends continuously through core layers) and comprises a first portion having a first hourglass shape in the first sub-core layer (1057a) and a second portion having a second hourglass shape in the second sub-core layer (1057b) (see Figs. 10E-10G and paragraphs 93-94), the first hourglass shape and the second hourglass shape completely filled with a conductive material in a cross-sectional perspective filled (paragraph 35: the thru-holes are filled by conductive material), the first hourglass shape having a top width the same as a bottom width, and the second hourglass shape having a top width the same as a bottom width (see Figs. 10E-10F and paragraphs 93-94: the top 1091 of one through hole 1065 corresponds to the bottom 1093 of the thru-hole 1065 above it, such that they are of the same diameter);
a front-side buildup layer (130) over the core (150) (Fig. 1B and paragraph 39); and
a backside buildup layer (140) under the core (150) (Fig. 1B and paragraph 39);
a die (210) coupled to the package substrate (100) (Fig. 2 and paragraph 54: IC die 210 is electrically and mechanically coupled to the package substrate 100).
Regarding claim 25, Ma et al. teaches the electronic system of claim 23, further comprising: an adhesive (1058) between the first sub-core layer (1057a) and the second sub-core layer (1057b) (Figs. 10E-10G and paragraphs 93-97: bonding layer 1058).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al., in further view of Kim et al. (US 2015/0083476 A1), hereinafter referred to as Kim et al.
Regarding claim 3, Ma et al. teaches the package substrate of claim 1, but does not teach that the first sub-core layer and the second sub-core layer comprise a fiber reinforced material.
Kim et al. does teach that the first sub-core layer and the second sub-core layer comprise a fiber reinforced material (Kim et al. paragraph 56).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the insulating layers of Ma et al. from a glass-fiber reinforced resin as taught by Kim et al. because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious engineering choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
Claim(s) 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al., in further view of Iwai et al. (US 2020/0203266 A1), hereinafter referred to as Iwai et al.
Regarding claim 8, Ma et al. teaches the package substrate of claim 1, but does not teach that a first signal trace is in the front- side buildup layer, and wherein a second signal trace is in the backside buildup layer.
Iwai et al. does teach a first signal trace (131) is in the front-side buildup layer (100), and wherein a second signal trace (131) is in the backside buildup layer (100) (paragraph 103: conductive traces 131 on the surfaces of the layers 100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the package substrate of Ma et al. with conductive traces as taught by Iwai et al. to improve or modify the functionality of the device according to the needs of the designer (Iwai et al. paragraph 103).
Regarding claim 9, Ma et al. in view of Iwai et al. teaches the package substrate of claim 8, wherein a signal for the second signal trace passes through the core (Iwai et al. paragraph 103: the conductor 131 passes through the through hole 120 as conductors 140, 150).
Regarding claim 10, Ma et al. teaches the package substrate of claim 1, but does not teach that a maximum diameter of the via is approximately 100µm or less.
Iwai et al. does teach that the maximum diameter of the via (120) is approximately 100µm or less (paragraph 83: the vias 120 have opening diameters of 20 µm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the vias of Ma et al. with a maximum diameter of 75 µm or less as taught by Iwai et al. because a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 11, Ma et al. in view of Iwai et al. teaches the package substrate of claim 10, but does not teach that the maximum diameter of the via is approximately 75µm or less (Iwai et al. paragraph 83: the vias 120 have opening diameters of 20 µm).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al. in view of Maruyama et al. (US 2011/0024172 A1), hereinafter referred to as Maruyama et al.
Regarding claim 24, Ma et al. teaches the electronic system of claim 23, but does not teach that the die has bumps with a first pitch and wherein the vias have the first pitch.
Maruyama et al. does teach that the die has bumps with a first pitch and wherein the vias have the first pitch (Maruyama et al. Fig. 1 and paragraph 150: each solder bump 3 is connected to an electrode on one of the vias 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the die bumps with the same pitch as the via as taught by Maruyama et al. because such an arrangement provides each terminal of the die access to the internal layers of the board (Maruyama et al. paragraph 150).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John B Freal whose telephone number is (571)272-4056. The examiner can normally be reached Mon-Fri 7:00-3:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Thompson can be reached at (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN B FREAL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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