Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Claim Rejections under 35 U.S.C. § 102/103, filed 10/07/2025, with respect to the rejection(s) of claim(s) 1-25 under U.S.C. § 102/103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as detailed below.
Applicant's arguments filed 10/07/2025 have been fully considered but they are not persuasive. The drawing objection has not been addressed and/or corrected.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show wherein the first HSIO phy and the second HSIO phy breakout laterally in opposite directions in the package substrate. as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 7-9, 11-14, 17-18, 20, 21, & 24 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoya et al. (US 2013/0016477) [Hereinafter Yokoya] & Li et al (US 2020/0105719) [Hereinafter Li].
Regarding claim 1, Yokoya teaches An electronic package, [fig. 2/6] comprising:
a package substrate [230, para 26];
a base [110, para 26] coupled to the package substrate;
a die [120, para 25] coupled to the base;
and a memory die module over the die [130/210, para 25-26/30], wherein the memory die module is communicatively coupled [coupled through TSV 161 of the interposer 160 as noted in para 29-30] to the die through interconnects [fig. 2, TSV 161, para 24] laterally spaced apart [fig. 2].
Yokoya fails to explicitly disclose wherein the memory die module is communicatively coupled to the die through interconnects laterally spaced apart from the die and through routing provided on the base.
However Li teaches wherein the memory die module [fig. 2A, memory die 211, para 53/44] is communicatively coupled to the die [fig. 2A, die 210, para 53/44] through interconnects [fig. 2A, through mold vias 260, para 53] laterally spaced apart from the die (fig. 2A, 210) and through routing [fig. 2A, interconnects 235, para 53] provided on the base [fig. 2A, substrate 202, para 52].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the interconnects to be laterally spaced apart from the die and through routing to reduce the overall package size and improve performance and package density. This allows for shorter interconnects, higher bandwidth, and lower power consumption.
Regarding claim 3, Yokoya/Li teaches The electronic package of claim 1, wherein one or more redistribution layers are provided on one or both horizontal surfaces of the base [Yokoya, para 25; wherein a redistribution layer may be on the bottom side 122 of the TSV die thereby on one horizontal surface of the base].
Regarding claim 7, Yokoya/Li teaches the electronic package of claim 1, wherein the communicative coupling between the memory die module and the die does not pass into the package substrate [Yokoya, fig. 2; wherein the TSVs don’t pass into the PCB 230].
Regarding claim 8, Yokoya/Li teaches The electronic package of claim 1, wherein the memory die module comprises:
a memory package substrate [Yokoya, 130, para 21];
a memory die [Yokoya, 210, para 30];
and a mold layer [Yokoya, 610/417, fig. 6, para 32-33] over and around the memory die.
Yokoya/Li fails to explicitly disclose a plurality of stacked memory dies;
and a mold layer over and around the plurality of stacked memory dies.
However, Yokoya further teaches in an exemplary embodiment [fig. 2, para 26] wherein “The top die 210 is shown including optional TSVs 215 that allows another die (not shown) to be attached to the top die 210.”
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to attach another memory die to the top die 210, thereby resulting in a plurality of dies.
Furthermore, one of ordinary skill in the art would understand wherein another memory die is mounting to the top die 210, then the external heat sink material would also be mounted over and around that die as well. Thereby meeting the claim limitation for improved heat dissipation.
Regarding claim 9, Yokoya/Li teaches the electronic package of claim 1, wherein a width of the memory die module is greater than a width of the die [Yokoya, fig. 2].
Regarding claim 11, Yokoya teaches [fig. 2/6] an electronic package, comprising:
a mold layer [140/240, fig. 2/6];
a die [120, para 25] coupled to the mold layer;
and a memory die module [130/210, para 25-26] above the die and coupled to the mold layer, wherein the memory die module is communicatively coupled [coupled through TSV 161 of the interposer 160 as noted in para 29-30] to the die through routing provided [161, para 24] on the mold layer.
Yokoya fails to explicitly disclose wherein the memory die module is communicatively coupled to the die through interconnects laterally spaced apart from the die and through routing provided on the base.
However Li teaches wherein the memory die module [fig. 2A, memory die 211, para 53/44] is communicatively coupled to the die [fig. 2A, die 210, para 53/44] through interconnects [fig. 2A, through mold vias 260, para 53] laterally spaced apart from the die (fig. 2A, 210) and through routing [fig. 2A, interconnects 235, para 53] provided on the base [fig. 2A, substrate 202, para 52].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the interconnects to be laterally spaced apart from the die and through routing to reduce the overall package size and improve performance and package density. This allows for shorter interconnects, higher bandwidth, and lower power consumption.
Regarding claim 12, Yokoya/Li teaches the electronic package of claim 11, further comprising: vias through the mold layer [Yokoya, fig. 2/6; wherein TSVs 161 goes through layer 240 of the mold layer].
Regarding claim 13, Yokoya/Li teaches the electronic package of claim 12, wherein one or more redistribution layers are provided on one or both horizontal surfaces of the mold layer [Yokoya, para 25; wherein a redistribution layer may be on the bottom side 122 of the TSV die thereby on one horizontal surface of the layer 140 of the mold layer.].
Regarding claim 14, Yokoya/Li teaches The electronic package of claim 11, wherein a die is provided over the mold layer [Yokoya, 140/240, para 26-27].
Yokoya/Li fails to explicitly disclose a plurality of dies provided over the mold layer.
Yokoya further teaches in an exemplary embodiment [fig. 2/6, para 26] wherein “The top die 210 is shown including optional TSVs 215 that allows another die (not shown) to be attached to the top die 210.”
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to attach another memory die to the top die 210, thereby resulting in a plurality of dies over the mold layer.
Regarding claim 17, Yokoya/Li teaches The electronic package of claim 11, wherein the memory die module comprises:
a memory package substrate [Yokoya, 130, para 20-21];
a memory die [Yokoya, 210, para 30];
and a second mold layer [Yokoya, 610/417, fig. 6; wherein the layers protect the device and improve heat dissipation] over and around the memory die.
Yokoya/Li fails to explicitly disclose a plurality of stacked memory die;
and a second mold layer over and around the plurality of stacked memory dies.
Yokoya further teaches in an exemplary embodiment [fig. 2/6, para 26] wherein “The top die 210
is shown including optional TSVs 215 that allows another die (not shown) to be attached to the top die 210.”
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to attach another memory die to the top die 210, thereby resulting in a plurality of dies wherein one of ordinary skill in the art would understand the second mold layer to be over and around the plurality of stacked memory dies for improved heat dissipation.
Regarding claim 18, Yokoya/Li teaches [Yokoya, fig. 2] the electronic package of claim 11, wherein a width [Yokoya, horizontal width] of the memory die module [Yokoya, 130/210, fig. 2] is greater than a width [Yokoya, horizontal width] of the die [Yokoya, 120, fig. 2].
Regarding claim 20, Yokoya teaches the electronic package of claim 11, wherein mold layer is coupled to a package substrate [Yokoya, fig. 2; wherein the mold layer is coupled to the package substrate 230 by the BGA 135 and workpiece 110].
Regarding claim 21, Yokoya teaches an electronic package, comprising:
a base [110, para 26];
a die [120, para 25] with a first width [horizontal width of 120] coupled to the base [fig. 2];
and a memory die module [130/210] with a second width [width of 210, fig. 2] coupled to the base [fig. 2], wherein the second width is greater than the first width [fig. 2], wherein the die is provided between the base and the memory die [fig. 2], and wherein the memory die module is coupled to the die through routing [161, para 24] on the base [fig. 2].
Yokoya fails to explicitly disclose wherein the memory die module is communicatively coupled to the die through interconnects laterally spaced apart from the die and through routing provided on the base.
However Li teaches wherein the memory die module [fig. 2A, memory die 211, para 53/44] is communicatively coupled to the die [fig. 2A, die 210, para 53/44] through interconnects [fig. 2A, through mold vias 260, para 53] laterally spaced apart from the die (fig. 2A, 210) and through routing [fig. 2A, interconnects 235, para 53] provided on the base [fig. 2A, substrate 202, para 52].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the interconnects to be laterally spaced apart from the die and through routing to reduce the overall package size and improve performance and package density. This allows for shorter interconnects, higher bandwidth, and lower power consumption.
Regarding claim 24, Yokoya teaches an electronic system, comprising:
A board [230, para 26];
a package substrate [110, para 26] coupled to the board;
and a multi-die module [130/120/210, fig. 2] coupled to the package substrate, wherein the multi-die module comprises:
a base [130, para 21];
a die [120, para 25] with a first width [horizontal width] coupled to the base [fig. 2];
and a memory die module [210, para 30] with a second width [horizontal width] coupled to the base, wherein the second width is greater than the first width [fig. 2], and wherein the memory die module is coupled to the base by vias [161, para 24] to the die [fig. 2].
Yokoya fails to explicitly disclose wherein the memory die module is coupled to the base by vias laterally spaced apart from the die.
However Li teaches wherein the memory die module [fig. 2A, memory die 211, para 53/44] is coupled to the base [fig. 2A, substrate 202, para 52] by vias [fig. 2A, through mold vias 260, para 53] laterally spaced apart from the die (fig. 2A, 210).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the interconnects to be laterally spaced apart from the die and through routing to reduce the overall package size and improve performance and package density. This allows for shorter interconnects, higher bandwidth, and lower power consumption.
Claim(s) 2, 22-23, & 25 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoya and Li as applied to claims 1, 3, 7-9, 11-14, 17-18, 20, 21, & 24 and further in view of Lin et al. (US 2014/0057391) [Hereinafter Lin].
Regarding claim 2, Yokoya/Li teaches The electronic package of claim 1, wherein the base [Yokoya, 110] comprises an organic substrate [Yokoya, para 20].
Yokoya/Li fails to explicitly disclose wherein the base comprises silicon.
However, Lin teaches an analogous package wherein the substrate layer 16 [fig. 1E] may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate [abstract & para 14].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to substitute the organic substrate by Yokoya with a silicon substrate as taught by Lin. Based on the rationale of simple substitution of one known element for another to obtain predictable results (MPEP 2143.I.B) such as better heat management and/or allowance for higher electrical interconnection.
Regarding claim 22, Yokoya/Li teaches The electronic package of claim 21, wherein the base is a package substrate such as an organic substrate [Yokoya, para 20].
Yokoya/Li fails to explicitly disclose wherein the base is a mold layer.
However, Lin teaches an analogous package wherein the substrate layer 16 [fig. 1E] may be formed from an epoxy, a resin, or another material. [para 14].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to substitute the organic substrate with an epoxy or a resin substrate as a mold layer as taught by Lin to protect the substrate from thermal effects.
Regarding 23, Yokoya/Li teaches The electronic package of claim 21, wherein the base comprises an organic substrate [Yokoya, para 20].
Yokoya/Li fails to explicitly teach wherein the base comprises silicon.
However, Lin teaches an analogous package wherein the substrate layer 16 [fig. 1E] may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate [para 14].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to substitute the organic substrate with a silicon substrate as an alternative as taught by Lin. Furthermore, the substituted component and their function as a substrate material were known in the art resulting in mechanical stability and good temperature tolerance.
Regarding claim 25, Yokoya/Li teaches The electronic system of claim 24, wherein the base is an organic substrate [Yokoya, para 20].
Yokoya/Li fails to explicitly disclose wherein the base is a mold layer or the base comprises silicon.
However, Lin teaches an analogous package wherein the substrate layer 16 [fig. 1E] may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate [abstract & para 14]. Para 14 further states in an embodiment, the substrate 16 is formed from an epoxy, a resin, or another material.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to substitute the organic substrate with a silicon substrate, epoxy, or a resin as an alternative as taught by Lin as the substituted component and their function were known in the art to provide a substrate with good mechanical stability and temperature tolerance.
Claims 4 & 5 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoya and Lin as applied to claims 1, 3, 7-9, 11-14, 17-18, 20, 21, & 24 and further in view of Hutton et al. (US 2019/0215280) [Hereinafter Hutton].
Regarding claim 4, Yokoya/Li teaches The electronic package of claim 1, wherein the die [Yokoya, 120] is a TSV die, which is included in logic/processor dies [Yokoya, para 3].
Yokoya/Li fails to explicitly disclose wherein a first memory physical layer (phy) is at a first edge of the die and a second memory phy is at a second edge of the die.
However, Hutton teaches wherein a first memory physical layer [1562, para 72] (phy) is at a first edge of the die [1500, para 71; wherein a FPGA is considered a logic chip die] and a second memory phy [annotated fig. 15] is at a second edge of the die.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the physical (phy) layers to be placed at the edges of the die (shoreline) as the primary interface for data transfer between layers.
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Annotated Fig. 15
Regarding claim 5, Yokoya/Li/Hutton teaches the electronic package of claim 4, wherein a first high speed I/O (HSIO) phy [Hutton, 1566, annotated fig. 15; wherein the disclosure is related to a device for high-speed data passing as noted in para 6] and a second HSIO phy [Hutton, 1566, annotated fig. 15; wherein the disclosure is related to a device for high-speed data passing as noted in para 6] are located between the first memory phy and the second memory phy.
Claim(s) 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoya and Li as applied to claims 1, 3, 7-9, 11-14, 17-18, 20, 21, & 24 and further in view of Lee et al (2016/0358899) [Hereinafter Lee].
Regarding claim 15, Yokoya/Li teaches The electronic package of claim 14, wherein the plurality of dies are communicatively coupled to each other by a bridge [Yokoya, interposer 160, para 29-30].
Yokoya/Li fails to explicitly disclose wherein the bridge is embedded in the mold layer.
However, Lee teaches conventional memory stack structures known in the art, utilize interposers that occupy a relatively large amount of die area (para 22) and decreasing the interconnect length which may improve signal integrity and power integrity is desired. In light of this desire, Lee teaches an interposer wherein the interposer may be formed within a photo definable mold 108 (fig. 1, para 27) thereby decreasing interconnect length.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee & Yokoya to comprise a plurality of dies communicatively coupled to each other by a bridge (interposer) embedded in the mold layer to decrease interconnect length resulting in reduced package size, and improving signal/power integrity as taught by Lee.
Regarding claim 16, Yokoya/Li/Lee teaches wherein the plurality of dies are embedded in a second mold layer [Yokoya, 610/417, para 32-33, fig. 6; wherein the plurality of dies is fixed in and surrounded by mold layer 610/417 which protects the device and enhances power dissipation].
Claim(s) 10 & 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoya and Li as applied to claims 1, 3, 7-9, 11-14, 17-18, 20, 21, & 24 and further in view of Yang et al. (US 2016/0099231) [Hereinafter Yang].
Regarding claim 10, Yokoya/Li teaches The electronic package of claim 1, wherein the die 120 is a TSV die, which is included in logic/processor dies [Yokoya, para 3].
Yokoya/Li fails to explicitly disclose wherein the die is a system on a chip (SoC).
However, Yang teaches an analogous package on package assembly wherein an SoC die [302, para 21, fig. 1] is a logic die also including TSVs.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the die of Yokoyama to comprise a system on a chip (SoC) to achieve higher component density in devices as taught by Yang.
Regarding claim 19, Yokoya/Li teaches The electronic package of claim 18, wherein the memory die module is coupled to the mold layer through a dispensing process [Yokoyo, para 30].
Yokoya fails to explicitly disclose wherein the memory die module is coupled to the mold layer by solder balls.
However, Yang teaches an analogous memory package wherein the memory die module [400a, para 19, fig. 3] is coupled to the mold layer [312, para 23, fig. 3] by solder balls [452, fig. 3].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to couple the memory die module to the mold layer by solder balls to establish a strong mechanical and electrical connection between components.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, Yokoya/Li/Hutton teaches The electronic package of claim 5,
The prior art of record singularly and/or in combination fails to explicitly teach wherein the first HSIO phy and the second HSIO phy breakout laterally in opposite directions in the package substrate.
Thereby claim 6 contains allowable subject matter and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FELIX B ANDREWS whose telephone number is (703)756-1074. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm ET.
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/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812