Prosecution Insights
Last updated: April 20, 2026
Application No. 17/833,608

ON PACKAGE INTERCONNECT ARCHITECTURE FOR HIGH-SPEED MEMORY

Non-Final OA §102§112
Filed
Jun 06, 2022
Examiner
JUNG, MICHAEL YOO LIM
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
93%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
1019 granted / 1241 resolved
+14.1% vs TC avg
Moderate +11% lift
Without
With
+11.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
41 currently pending
Career history
1282
Total Applications
across all art units

Statute-Specific Performance

§101
2.1%
-37.9% vs TC avg
§103
29.0%
-11.0% vs TC avg
§102
35.0%
-5.0% vs TC avg
§112
27.6%
-12.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1241 resolved cases

Office Action

§102 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION In response to a restriction requirement mailed on 10/17/2025, the Applicant elected Invention I (Group) drawn to a substrate encompassing claims 1-14, without traverse in a response filed on 12/17/2025. Non-elected Invention II (Group II) drawn to an electronic package encompassing claims 15-24 is withdrawn. Elected claims 1-14 are examined below. Specification The specification is objected to, because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: ON PACKAGE INTERCONNECT ARCHITECTURE FOR HIGH-SPEED MEMORY HAVING TRACES WITH ALTERNATING PATTERNS Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 10 is indefinite, because it is unclear what “DDR” is referring to as DDR has not been defined in the Specification. Claim Rejections - 35 USC § 1021 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 6 and 10-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Patent No. US 7,994,631 B1 to Zhang (“Zhang”). Fig. 3 of Zhang has been provided to support the rejections below: PNG media_image1.png 322 522 media_image1.png Greyscale Regarding independent claim 1, Zhang teaches a package substrate (see Fig.) comprising: a core 321 (col. 4, ln 15-54 - “A protective layer 321, such as a dielectric layer…”); a first layer 318 (col. 4, ln 15-54 - “another metal layer 318 comprising power traces is applied”) on the core 321, wherein the first layer 318 comprises a first (power) plane; a second layer 316 (col. 4, ln 15-54 - “a metal layer 316”) on the first layer 318, wherein the second layer 316 comprises first (signal) traces and second (ground) traces arranged in an alternating pattern (see Fig. 3); a third layer 328 (col 4, ln 55-67 - “a metal layer 328”) on the second layer 316, wherein the third layer 328 comprises third (signal) traces and fourth (ground) traces arranged in an alternating pattern (see Fig. 3); and a fourth layer 330 (col. 4, ln 55-67 - “A power plane 330”) over the third layer 328, wherein the fourth layer 330 comprises a second (power) plane. Regarding claim 2, Zhang teaches the first (signal) traces that are configured to be first signaling traces and the second (ground) traces that are configured to be first ground traces, and wherein the third (signal) traces are configured to be second signaling traces and the fourth (ground) traces are configured to be second ground traces. Regarding claim 6, Zhang teaches the first signal traces that include single ended signaling traces (see Fig. 3). Regarding claim 10, a limitation of “are part of a single DDR byte” of the wherein clause of claim 10 is a statement of an intended use so the limitation does not structurally distinguish the claimed package substrate over the package substrate taught by Zhang. Regarding claim 11, Zhang teaches overlap of the first signal traces (of the metal layer 316) and the second signal traces (of the metal layer 328) that only occur at a bump breakout region (see Fig. 3). Regarding claim 12, Zhang teaches the package substrate that further comprises four routing layers 312, 308, 304, 324 (col. 4, ln 15-54 - “…where a first metal layer 304 comprising power traces is applied on a first side…A metal layer 308 comprising ground conductors is provided on a second side of the dielectric layer 303…The metal layer 312 also comprises alternating conductive traces coupling input/out signals and a ground signal…”; col. 4, ln 55-67 - “In particular, another metal layer 324 is applied, comprising alternating conductive traces coupling input/output signals and a ground signal…”) on an opposite side of the core from the first layer 318. Regarding claim 13, Zhang teaches a dielectric layer 303 (col. 4, ln 15-54 - “a thick dielectric layer 303”) that is provided between the second layer 316 and the third layer 328. Regarding claim 14, Zhang teaches a thickness of the dielectric layer 303 that is greater than 12 microns (col. 5, ln 45-59 - “However, thick dielectric layers may have a thickness of approximately 800 micrometers…”). Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: Claim 3 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 and the intervening claim 2 or the base claim 1 is amended to include all of the limitations of claim 3 and the intervening claim 2. Claims 4 and 5 are allowable for depending on the allowable claim 3. Claim 7 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 and the intervening claims 2 and 6 or the base claim 1 is amended to include all of the limitations of claim 7 and the intervening claims 2 and 6. Claims 8 and 9 are allowable for depending on the allowable claim 7. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Patent No. US 11,259,403 B1 to Wang et al. Patent No. US 9,111,675 B1 to Kireev Patent No. US 7,531,751 B2 to Hosomi et al. Patent No. US 6,239,485 B1 to Peters et al. Pub. No. US 2017/0286725 A1 to Lewis Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL JUNG/Primary Examiner, Art Unit 2817 23 January 2026 1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Read full office action

Prosecution Timeline

Jun 06, 2022
Application Filed
Sep 13, 2022
Response after Non-Final Action
Jan 23, 2026
Non-Final Rejection — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS EACH WITH A FILLED TRENCH WITHIN A STADIUM STRUCTURE OF AT LEAST ONE BLOCK
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PACKAGE BUMPS OF A PACKAGE SUBSTRATE HAVING DIAGONAL PACKAGE BUMPS
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
93%
With Interview (+11.2%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 1241 resolved cases by this examiner. Grant probability derived from career allow rate.

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