Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action follows the decision of Pre-Appeal Brief Conference on 07/28/2026, and the prosecution on the merits is reopened. Amendment filed on 02/24/2026 has been entered. Claims 1, 7, 11, 16, 19 have been amended. Claims 11 – 20 have been withdrawn. Claims 1 – 10 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 ̶ 6, 8 – 10 are rejected under 35 U.S.C. 103 as being unpatentable over Wu ( Pub. No. US 20200328212 A1 ), hereinafter Wu.
PNG
media_image1.png
935
1430
media_image1.png
Greyscale
Regarding Independent Claim 1 (Currently Amended), Wu teaches a three-dimensional semiconductor device, comprising:
a first active region ( Wu, FIG. 3A, 210; [0040], PMOS 112 includes a fin or a wire 210 having a channel region and source/drain regions ) on a substrate ( Wu, [0035], substrate ), the first active region ( Wu, FIG. 3A, 210; [0040], PMOS 112 includes a fin or a wire 210 having a channel region and source/drain regions ) including a first source/drain pattern ( Wu, [0040], the source region of the fin 210, the drain region of the fin 210 ) and first semiconductor patterns ( Wu, [0040], a fin or a wire 210 having a channel region … the gate 120 wrapping around the channel region of the fin 210; [0042], The gate 210 includes a gate dielectric layer, one or more work function adjustment layers and a body gate electrode layer in some embodiments; [0050], In some embodiments, two fins 110 and two fins 210 are horizontally arranged, respectively ) connected to the first source/drain pattern ( Wu, [0040], the source region of the fin 210, the drain region of the fin 210 );
a first active contact ( Wu, FIG. 3A, 235; [0040], drain contact 235 ) on the first source/drain pattern ( Wu, [0040], the source region of the fin 210, the drain region of the fin 210 );
a second active region ( Wu, FIG. 3A, 110; [0040], NMOS 111 includes a fin or a wire 110 having a channel region and source/drain regions ) on the first active region ( Wu, FIG. 3A, 210; [0040], PMOS 112 includes a fin or a wire 210 having a channel region and source/drain regions ) and the first active contact ( Wu, FIG. 3A, 235; [0040], drain contact 235 ), the second active region ( Wu, FIG. 3A, 110; [0040], NMOS 111 includes a fin or a wire 110 having a channel region and source/drain regions ) including a second source/drain pattern ( Wu, [0040], the source region of the fin 110, the drain region of the fin 110 ) and second semiconductor patterns ( Wu, [0040], a fin or a wire 110 having a channel region … a gate structure 120 wrapping around the channel region of the fin 110; [0042], The gate 210 includes a gate dielectric layer, one or more work function adjustment layers and a body gate electrode layer in some embodiments; [0050], In some embodiments, two fins 110 and two fins 210 are horizontally arranged, respectively ) connected to the second source/drain pattern ( Wu, [0040], the source region of the fin 110, the drain region of the fin 110 );
a second active contact ( Wu, FIG. 3A, 130; [0040], source contact 130 ) on the second source/drain pattern ( Wu, [0040], the source region of the fin 110, the drain region of the fin 110 );
a gate electrode ( Wu, FIG. 3A, 120; [0040], gate structure 120 ) that vertically extends from the first semiconductor patterns ( Wu, [0040], a fin or a wire 210 having a channel region … the gate 120 wrapping around the channel region of the fin 210; [0042], The gate 210 includes a gate dielectric layer, one or more work function adjustment layers and a body gate electrode layer in some embodiments; [0050], In some embodiments, two fins 110 and two fins 210 are horizontally arranged, respectively ) toward the second semiconductor patterns ( Wu, [0040], a fin or a wire 110 having a channel region … a gate structure 120 wrapping around the channel region of the fin 110; [0042], The gate 210 includes a gate dielectric layer, one or more work function adjustment layers and a body gate electrode layer in some embodiments; [0050], In some embodiments, two fins 110 and two fins 210 are horizontally arranged, respectively );
a first power line ( Wu, FIG. 6, power supply line Vdd 310 ) below the first active region ( Wu, FIG. 6, wire 210 having a channel region and source/drain regions ) and a second power line ( Wu, FIG. 6, power supply line Vss 320 ) below the first active region ( Wu, FIG. 6, wire 210 having a channel region and source/drain regions ); and
a first metal layer ( Wu, [0048], metal wiring level (M0) ) on the gate electrode ( Wu, FIG. 3A, 120; [0040], gate structure 120 ) and the second active contact( Wu, FIG. 3A, 130; [0040], source contact 130 ),
the first active contact ( Wu, FIG. 3A, 235; [0040], drain contact 235 ) including
a first connection part ( Wu, FIG. 3A, part of 230, part of 235, the part is connected with source/drain in 210; [0040], source contact 230 wrapping around the source region of the fin 210, drain contact 235 wrapping around the drain region of the fin 210 ) connected to the first source/drain pattern ( Wu, [0040], the source region of the fin 210, the drain region of the fin 210 );
and
a first pad part ( Wu, the part connected with via, as shown in FIG. 3A, 230, 235; [0040], source contact 230, drain contact 235 ) that horizontally extends from the first connection part ( Wu, FIG. 3A, part of 230, part of 235, the part is connected with source/drain in 210; [0040], source contact 230 wrapping around the source region of the fin 210, drain contact 235 wrapping around the drain region of the fin 210 ),
the second active contact ( Wu, FIG. 3A, 130; [0040], source contact 130 ) including
a second connection part ( Wu, FIG. 3A, part of 130, part of 135, the part is connected with source/drain in 110; [0040], source contact 130 wrapping around the source region of the fin 110, drain contact 135 wrapping around the drain region of the fin 110 ) connected to the second source/drain pattern ( Wu, [0040], the source region of the fin 110, the drain region of the fin 110 ); and
a second pad part ( Wu, the part connected with via, as shown in FIG. 3A, 130, 135; [0040], source contact 130, drain contact 135 ) that horizontally extends from the second connection part ( Wu, FIG. 3A, part of 130, part of 135, the part is connected with source/drain in 110; [0040], source contact 130 wrapping around the source region of the fin 110, drain contact 135 wrapping around the drain region of the fin 110 ),
the first pad part ( Wu, the part connected with via, as shown in FIG. 3A, 230, 235; [0040], source contact 230, drain contact 235 ) being horizontally offset from the second active contact ( Wu, FIG. 3A, 130; [0040], source contact 130 ),
the second pad part ( Wu, the part connected with via, as shown in FIG. 3A, 130, 135; [0040], source contact 130, drain contact 135 ) being horizontally offset from the first active contact ( Wu, FIG. 3A, 235; [0040], drain contact 235 ),
the first pad part ( Wu, the part connected with via, as shown in FIG. 3A, 230, 235; [0040], source contact 230, drain contact 235 ) being electrically connected through a first via ( Wu, FIG. 3A, 330, 340; [0046], bottom via contact 330, top via contact 340 ) to one of the first power line ( Wu, FIG. 3A, 310, 320; [0039], one of the power supply lines (power rail) Vdd 310 (e.g., positive potential) and Vss 320 (e.g., negative or ground potential) ) and a first wiring line ( Wu, FIG. 3A, 350, 360, 370; [0047], signal lines 350, 360 and 370 ) in the first metal layer ( Wu, [0048], metal wiring level (M0) ),
the second pad part ( Wu, the part connected with via, as shown in FIG. 3A, 130, 135; [0040], source contact 130, drain contact 135 ) being electrically connected through a second via ( Wu, FIG. 3A, 340, 342; [0046], top via contact 340; [0047], via contact 342 ) to one of the second power line ( Wu, FIG. 3A, 310, 320; [0039], one of the power supply lines (power rail) Vdd 310 (e.g., positive potential) and Vss 320 (e.g., negative or ground potential) ) and a second wiring line ( Wu, FIG. 3A, 350, 360, 370; [0047], signal lines 350, 360 and 370 ) in the first metal layer ( Wu, [0048], metal wiring level (M0) ), and
the first via ( Wu, FIG. 3A, 330; [0046], bottom via contact 330 ) extends past and is horizontally offset from the second active contact ( Wu, FIG. 3A, 130; [0040], source contact 130 ),
wherein the first semiconductor patterns ( Wu, [0040], a fin or a wire 210 having a channel region … the gate 120 wrapping around the channel region of the fin 210; [0042], The gate 210 includes a gate dielectric layer, one or more work function adjustment layers and a body gate electrode layer in some embodiments ) are vertically overlapped with each other and are spaced apart from the second source/drain pattern ( Wu, [0040], the source region of the fin 110, the drain region of the fin 110 ),
wherein the second semiconductor patterns ( Wu, [0040], a fin or a wire 110 having a channel region … a gate structure 120 wrapping around the channel region of the fin 110; [0042], The gate 210 includes a gate dielectric layer, one or more work function adjustment layers and a body gate electrode layer in some embodiments ) are vertically overlapped with each other and are spaced apart from the first source/drain pattern ( Wu, [0040], the source region of the fin 210, the drain region of the fin 210 ),
wherein a lowermost portion of the first active contact ( Wu, FIG. 2A, the lowermost portion of 340 on 235; [0040], drain contact 235 ) is disposed at a higher level than a lowermost portion of the first source/drain pattern ( Wu, FIG. 2A, the lowermost portion of 210 in 235; [0040], the source region of the fin 210, the drain region of the fin 210 ),
wherein a lowermost portion of the second active contact ( Wu, FIG. 3A, the lowermost portion of 340 on 130; [0040], source contact 130 ) is disposed at a higher level than a lowermost portion of the second source/drain pattern ( Wu, FIG. 3A, the lowermost portion of 110 in 130; [0040], the source region of the fin 110, the drain region of the fin 110 ).
Regarding Claim 2 (Original), Wu teaches the device as claimed in claim 1, on which this claim is dependent, Wu further teaches:
wherein the first connection part ( Wu, FIG. 3A, part of 230, part of 235, the part is connected with source/drain in 210; [0040], source contact 230 wrapping around the source region of the fin 210, drain contact 235 wrapping around the drain region of the fin 210 ) and the second connection part ( Wu, FIG. 3A, part of 130, part of 135, the part is connected with source/drain in 110; [0040], source contact 130 wrapping around the source region of the fin 110, drain contact 135 wrapping around the drain region of the fin 110 ) vertically overlap each other.
Regarding Claim 3 (Original), Wu teaches the device as claimed in claim 2, on which this claim is dependent, Wu further teaches:
wherein the first source/drain pattern ( Wu, [0040], the source region of the fin 210, the drain region of the fin 210 ) vertically overlaps the first connection part ( Wu, FIG. 3A, part of 230, part of 235, the part is connected with source/drain in 210; [0040], source contact 230 wrapping around the source region of the fin 210, drain contact 235 wrapping around the drain region of the fin 210 ), and
the second source/drain pattern ( Wu, [0040], the source region of the fin 110, the drain region of the fin 110 ) vertically overlaps the second connection part ( Wu, FIG. 3A, part of 130, part of 135, the part is connected with source/drain in 110; [0040], source contact 130 wrapping around the source region of the fin 110, drain contact 135 wrapping around the drain region of the fin 110 ).
Regarding Claim 4 (Original), Wu teaches the device as claimed in claim 1, on which this claim is dependent, Wu further teaches:
wherein the first via ( Wu, FIG. 3A, 340, 330, 342, 344; [0046], top via contact 340, bottom via contact 330; [0047], via contact 342, via contact 344 ) is electrically connected to the first wiring line ( Wu, FIG. 3A, 350, 360, 370; [0047], signal lines 350, 360 and 370 ), and
the first via ( Wu, FIG. 3A, 330; FIG. 3C, 330; [0046], bottom via contact 330 ) is spaced apart from a sidewall of the second active contact ( Wu, FIG. 3A, 130; FIG. 3C, 130; [0040], source contact 130 ).
Regarding Claim 5 (Original), Wu teaches the device as claimed in claim 1, on which this claim is dependent, Wu further teaches:
wherein the second via ( Wu, FIG. 3A, 340, 342; [0046], top via contact 340; [0047], via contact 342 ) is electrically connected to the second power line ( Wu, FIG. 3A, 310, 320; [0039], one of the power supply lines (power rail) Vdd 310 (e.g., positive potential) and Vss 320 (e.g., negative or ground potential) ), and
the second via ( Wu, FIG. 3A, 340, 342; [0046], top via contact 340; [0047], via contact 342 ) is spaced apart from a sidewall of the first active contact ( Wu, FIG. 3A, 235; [0040], drain contact 235 ).
Regarding Claim 6 (Original), Wu teaches the device as claimed in claim 1, on which this claim is dependent, Wu further teaches:
wherein the first active region ( Wu, FIG. 3A, 210; [0040], PMOS 112 includes a fin or a wire 210 having a channel region and source/drain regions ) is one of a PMOSFET region ( Wu, FIG. 3A, PMOS 112 ) and an NMOSFET region, and
the second active region ( Wu, FIG. 3A, 110; [0040], NMOS 111 includes a fin or a wire 110 having a channel region and source/drain regions ) is the other of a PMOSFET region and an NMOSFET region ( Wu, FIG. 3A, NMOS 111 ).
Regarding Claim 8 (Original), Wu teaches the device as claimed in claim 1, on which this claim is dependent, Wu further teaches: further comprising:
a power delivery network ( Wu, [0038], deep contact (e.g., a contact connecting a source or a drain to a buried power supply line located below the CFET) ) on a bottom surface of the substrate ( Wu, [0035], substrate ); and
a plurality of through vias ( Wu, [0038], deep contact ) that electrically connect the first and second power lines ( Wu, FIG. 3A, 310, 320; [0039], one of the power supply lines (power rail) Vdd 310 (e.g., positive potential) and Vss 320 (e.g., negative or ground potential) ) to the power delivery network ( Wu, [0038], deep contact (e.g., a contact connecting a source or a drain to a buried power supply line located below the CFET) ) .
Regarding Claim 9 (Original), Wu teaches (Original) the device as claimed in claim 1, on which this claim is dependent, Wu further teaches:
wherein at least a portion of the first via ( Wu, FIG. 3A, 330; [0046], bottom via contact 330 ) vertically overlaps the first wiring line ( Wu, FIG. 3A, 360; [0047], signal lines 360 ), and
at least a portion of the second via ( Wu, FIG. 3A, 342; [0047], via contact 342 ) vertically overlaps the second wiring line ( Wu, FIG. 3A, 350; [0047], signal lines 350 ).
Regarding Claim 10 (Original), Wu teaches (Original) the device as claimed in claim 1, on which this claim is dependent, Wu further teaches:
wherein the first active contact ( Wu, FIG. 3A, 235; [0040], drain contact 235 ) further includes a third pad part ( Wu, the part connected with via, as shown in FIG. 3A, 135; [0040], drain contact 135 ) that stands opposite to the first pad part ( Wu, the part connected with via, as shown in FIG. 3A, 235; [0040], drain contact 235 ),
the third pad part ( Wu, the part connected with via, as shown in FIG. 3A, 135; [0040], drain contact 135 ) is horizontally offset from the second active contact ( Wu, FIG. 3A, 130; [0040], source contact 130 ), and
the third pad part ( Wu, the part connected with via, as shown in FIG. 3A, 135; [0040], drain contact 135 ) is electrically connected through a third via ( Wu, FIG. 3A, 342; [0047], via contact 342 ) to a third wiring line ( Wu, FIG. 3A, 350; [0047], signal lines 350 ) in the first metal layer ( Wu, [0048], metal wiring level (M0) ).
Allowable Subject Matter
Claim 7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 02/24/2026 have been fully considered but they are not persuasive.
Applicant’s remarks regarding Claim 1: on page 11, line 3 from bottom, applicant’s argument cited “ Furthermore, as seen below in FIG. 4A of the instant application, each of the first and second active contacts AC1, AC2, have lower levels above lower levels of the respective semiconductor patterns SP1-3 and SP4-6. ”; on page 13, line 1 from bottom, applicant’s argument cited “ Applicants have amended claim 1 to include "wherein the first semiconductor patterns are vertically overlapped with each other and are spaced apart from the second source/drain pattern, wherein the second semiconductor patterns are vertically overlapped with each other and are spaced apart from the first source/drain pattern, wherein a lowermost portion of the first active contact is disposed at a higher level than a lowermost portion of the first source/drain pattern, and wherein a lowermost portion of the second active contact is disposed at a higher level than a lowermost portion of the second source/drain pattern," and contend that the cited art does not disclose or suggest at least the features of amended claim 1. ”.
Examiner’s response: please refer to claim 1 in Claim Rejections - 35 USC § 102 of this office action, cited “ wherein the first semiconductor patterns ( Wu, [0040], a fin or a wire 210 having a channel region … the gate 120 wrapping around the channel region of the fin 210; [0042], The gate 210 includes a gate dielectric layer, one or more work function adjustment layers and a body gate electrode layer in some embodiments ) are vertically overlapped with each other and are spaced apart from the second source/drain pattern ( Wu, [0040], the source region of the fin 110, the drain region of the fin 110 ),
wherein the second semiconductor patterns ( Wu, [0040], a fin or a wire 110 having a channel region … a gate structure 120 wrapping around the channel region of the fin 110; [0042], The gate 210 includes a gate dielectric layer, one or more work function adjustment layers and a body gate electrode layer in some embodiments ) are vertically overlapped with each other and are spaced apart from the first source/drain pattern ( Wu, [0040], the source region of the fin 210, the drain region of the fin 210 ),
wherein a lowermost portion of the first active contact ( Wu, FIG. 2A, the lowermost portion of 340 on 235; [0040], drain contact 235 ) is disposed at a higher level than a lowermost portion of the first source/drain pattern ( Wu, FIG. 2A, the lowermost portion of 210 in 235; [0040], the source region of the fin 210, the drain region of the fin 210 ),
wherein a lowermost portion of the second active contact ( Wu, FIG. 3A, the lowermost portion of 340 on 130; [0040], source contact 130 ) is disposed at a higher level than a lowermost portion of the second source/drain pattern ( Wu, FIG. 3A, the lowermost portion of 110 in 130; [0040], the source region of the fin 110, the drain region of the fin 110 ). ”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights