DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on Nov. 18th 2025 has been entered. Claims 1-11 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Komiya et al. (US 20190287997) in view of Sasaki et al. (US 20160086973) and Maruyama et al. (US 20190355742).
Regarding claim 1, Komiya teaches a semiconductor storage device (memory device; Abstract) comprising:
a substrate (fig. 3, source layer SL, a polysilicon layer provided on a silicon substrate (not illustrated); para. 0046);
an interconnection layer region (region around select gate SGS; para. 0018) on the substrate (SL);
a multi-layered body (fig. 2A, inter-layer insulating films 15, word lines WL1, and word line WL2 inter-layer insulating films 25; para. 0025) on the interconnection layer region (SGS region), the multi-layered body (15, WL1, 25, WL2) including a plurality of conductive layers (WL1, WL2) and a plurality of insulating layers (15, 25), the plurality of the conductive layers (WL1, WL2) and the plurality of the insulating layers (15, 25) being alternately stacked one layer by one layer in a first direction (vertical direction), and the first direction being a thickness direction (vertical direction) of the substrate (SL); and
a columnar part (columnar body PB, semiconductor base SB; para. 0027, 0028) including a semiconductor body (semiconductor layer SF; para. 0027) and a memory part (charge trap film CT of memory film MF; para. 0036), the semiconductor body (SF) extending in the first direction (vertical direction), the memory part (CT of MF) being between the semiconductor body (SF) and each of the plurality of the conductive layers (WL1, WL2), the columnar part (PB, SB) penetrating the multi-layered body (15, WL1, 25, WL2), and the columnar part (PB, SB) being connected (through insulating film 31; para. 0028) to the interconnection layer region (SGS), wherein
the multi-layered body (15, WL1, 25, WL2) has an end portion (bottom 15) facing the interconnection layer region (SGS) as an end (bottom end) thereof in the first direction (vertical direction),
the columnar part (PB, SB) includes a first portion (top portion of PB with CA) and a second portion (bottom portion of insulating film 33 and SB; para. 0039), the second portion (bottom portion) being closer to the substrate (SL) than the first portion (top portion),
the first portion (top portion) has a center (center of CA) and a first surface (side surface of PB),
the second portion (bottom portion) has a center (center of middle SB) and a second surface (side surface of bottom portion),
a second direction (horizontal direction) crossing the first direction (vertical direction), and
each of the first portion (top portion) includes a first insulating film (blocking insulating film BLK; para. 0036), the first insulating film (BLK) being provided on the first surface (side surface of PB), and the interconnection layer region (SGS) is connected to the second surface (side surface of bottom portion).
Komiya fails to explicitly teach the center of the second portion in a second direction is displaced in the second direction with respect to the center of the first portion in the second direction.
However, Sasaki teaches the center of the second portion (Sasaki: fig. 13B, center of the lower portion of columnar portion CL at first stacked unit 11; para. 0164, similar to center of SB of Komiya, as a first center in the first portion, which is same as the center in the second portion of Komiya) in a second direction (horizontal direction) is displaced in the second direction (horizontal direction) with respect to the center of the first portion (Sasaki: center of CL at second stacked unit 12; para. 0164, similar to the center of higher portion PB of Komiya, as a second center in the first portion of Komiya) in the second direction (horizontal direction).
Sasaki and Komiya are considered to be analogous to the claimed invention because they are in the same field of semiconductor storage device.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Komiya and Sasaki in order to achieve the predictable result of the central axis of the holes not matching due to the alignment shift of the opening patterns, which is common in the manufacture (Sasaki: para. 0060).
In addition, Komiya in view of Sasaki fails to explicitly teach the end portion of the multi-layered body includes an end surface of the multi- layered body at a boundary position between the multi-layered body and the interconnection layer region;
the first portion being at the end surface of the multi-layered body;
the second portion includes the first insulating film being provided on the second surface.
However, Maruyama teaches the end portion of the multi-layered body (Maruyama: fig. 11, word lines WL, insulating films 45; para. 0054, similar to 15, WL1 of Komiya) includes an end surface (Maruyama: bottom surface of bottom 45) of the multi- layered body (Maruyama: WL, 45) at a boundary position (Maruyama: boundary of bottom 45) between the multi-layered body (Maruyama: WL, 45) and the interconnection layer region (Maruyama: select gate SGS, semiconductor layer 20; para. 0018, 0019, similar to SGS region of Komiya);
the first portion (Maruyama: top portion of columnar bodies CL; para. 0018) being at the end surface (Maruyama: bottom surface of bottom 45) of the multi-layered body (Maruyama: WL, 45);
the second portion (Maruyama: bottom portion of CL) includes the first insulating film (Maruyama: third insulating film 57 of memory film 50; para. 0033, similar to BLK of Komiya) being provided on the second surface (Maruyama: side surface of bottom portion).
Maruyama, Sasaki and Komiya are considered to be analogous to the claimed invention because they are in the same field of semiconductor storage device.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maruyama, Komiya and Sasaki in order to achieve the predictable result of structure to stabilize the electrical connection and avoid the decrease of the manufacturing yield (Maruyama: para. 0058).
Regarding claim 2, Komiya in view of Sasaki and Maruyama further teaches the semiconductor storage device according to claim 1, wherein
a width of the second portion (Komiya: fig. 3, width of SB) in the second direction (horizontal direction) is larger than a width of the first portion (Komiya: width of CA) in the second direction (horizontal direction).
Regarding claim 3, Komiya in view of Sasaki and Maruyama further teaches the semiconductor storage device according to claim 1, wherein
the columnar part (Komiya: fig. 3, PB, SB) includes a large diameter part (Komiya: SB with 31) and a small diameter part (Komiya: lower SB),
the large diameter part (Komiya: SB with 31) is provided at a portion (Komiya: portion at 31) of the columnar part (Komiya: PB, SB) at which the columnar part (Komiya: PB and SB at 31) faces the interconnection layer region (Komiya: SGS),
the large diameter part (Komiya: SB with 31) is provided at the boundary position (Komiya: position of bottom 15) between the multi-layered body (Komiya: 15, WL1, 25, WL2) and the interconnection layer region (Komiya: SGS), and
the small diameter part (Komiya: lower SB) is closer to the substrate (Komiya: SL) than the large diameter part (Komiya: SB with 31).
Regarding claim 4, Komiya in view of Sasaki and Maruyama further teaches the semiconductor storage device according to claim 1, further comprising:
an insulating part (Komiya: fig. 14B, source contact LI with insulating film 45; para. 0075) dividing the multi-layered body (Komiya: 15, WL1, 25, WL2) into a plurality of regions (Komiya: regions around 45) in the second direction (Komiya: horizontal direction), wherein
the insulating part (Komiya: 45) includes a portion (Komiya: upper portion of 45) penetrating the multi-layered body (Komiya: 15, WL1, 25, WL2) in the first direction (vertical direction) and facing the interconnection layer region (Komiya: SGS),
the insulating part (Komiya: 45) includes a third portion (Komiya: higher portion of 45 at and above bottom 15) and a fourth portion (Komiya: lower portion of 45 below bottom 15), the third portion (Komiya: higher portion of 45) being at the end portion of the multi-layered body (Komiya: bottom 15), the fourth portion (Komiya: lower portion of 45) being closer to the substrate (Komiya: SL) than the third portion (Komiya: higher portion of 45) is.
Komiya in view of Sasaki and Maruyama as applied to claim 1 fails to teach a width of the fourth portion in the second direction is larger than a width of the third portion in the second direction.
However, Maruyama teaches a width of the fourth portion (Maruyama: fig. 18, insulating film 37; para. 0030, similar to lower portion of 45 of Komiya) in the second direction (horizontal direction) is larger than a width of the third portion (Maruyama: insulating film 41 at bottom insulating films 45; para. 0030, 0032, similar to the higher portion of 45 of Komiya) in the second direction (horizontal direction).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Komiya, Sasaki and Maruyama in order to achieve the predictable result of an insulating film to suppress the movement of the atoms and stabilize the electrical connection (Maruyama: para. 0101).
Regarding claim 5, Komiya in view of Sasaki and Maruyama further teaches the semiconductor storage device according to claim 1, further comprising:
an insulating part (Komiya: fig. 14B, source contact LI with insulating film 45; para. 0075) dividing the multi-layered body (Komiya: 15, WL1, 25, WL2) into a plurality of regions (Komiya: regions around 45) in the second direction (horizontal direction), wherein
the insulating part (Komiya: 45) includes a portion (Komiya: upper portion of 45) penetrating the multi-layered body (Komiya: 15, WL1, 25, WL2) in the first direction (vertical direction) and facing the interconnection layer region (Komiya: SGS),
the insulating part (Komiya: 45) includes a third portion (Komiya: higher portion of 45 at and above bottom 15) and a fourth portion (Komiya: lower portion of 45 below bottom 15), the third portion (Komiya: higher portion of 45 with bottom at) being at the end portion of the multi-layered body (Komiya: bottom 15), and the fourth portion (Komiya: lower portion of 45) being closer to the substrate (Komiya: SL) than the third portion (Komiya: higher portion of 45),
the third portion (Komiya: higher portion of 45) has a center (Komiya: center of the higher portion of 45),
the fourth portion (Komiya: lower portion of 45) has a center (Komiya: center of the lower portion of 45).
Komiya in view of Sasaki and Maruyama as applied to claim 1 above fails to explicitly teach the center of the third portion in the second direction is displaced in the second direction with respect to the center of the fourth portion in the second direction.
However, Sasaki teaches the center of the third portion (Sasaki: fig. 13A, center of insulating separation films 61b at second intermediate layer 14; para. 0169, similar to higher portion of 45 of Komiya) in a second direction (horizontal direction) is displaced in the second direction (horizontal direction) with respect to the center of the fourth portion (Sasaki: center of insulating separation films 61a; para. 0169, similar to lower portion of 45 of Komiya) in the second direction (horizontal direction).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Komiya and Sasaki in order to achieve the predictable result of the central axis of the holes not matching due to the alignment shift of the opening patterns, which is common in the manufacture (Sasaki: para. 0060).
Regarding claim 6, Komiya in view of Sasaki and Maruyama further teaches the semiconductor storage device according to claim 1, wherein
the columnar part (Komiya: fig. 3, PB, SB) includes a large diameter part (Komiya: PB and top SB),
the large diameter part (Komiya: PB and top SB) has a circumferential portion (Komiya: SF around the part of CA with mark Ws2),
the large diameter part (Komiya: PB and top SB) is provided at a portion (Komiya: portion at bottom 15) of the columnar part (Komiya: PB, SB) at which the columnar part (Komiya: PB and SB at bottom 15) is on the interconnection layer region (Komiya: SGS),
the large diameter part (Komiya: PB and top SB) is provided at the boundary position (Komiya: position of bottom 15) between the multi-layered body (Komiya: 15, WL1, 25, WL2) and the interconnection layer region (Komiya: SGS),
the semiconductor body (Komiya: SF) includes a connection part (Komiya: SF around top CA), and
the connection part (Komiya: SF around top CA) of the semiconductor body (Komiya: SF) is on the circumferential portion (Komiya: SF around the part of CA with mark Ws2) of the large diameter part (Komiya: PB and top SB).
Regarding claim 7, Komiya in view of Sasaki and Maruyama further teaches the semiconductor storage device according to claim 1, wherein
the columnar part (Komiya: fig. 3, PB, SB) includes a maximum diameter part (Komiya: top SB) and a large diameter part (Komiya: PB),
the maximum diameter part (Komiya: top SB) is provided at a portion (Komiya: portion at bottom 15) of the columnar part (Komiya: PB, SB) at which the columnar part (Komiya: PB and SB at bottom 15) is on the interconnection layer region (Komiya: SGS), and
the maximum diameter part (Komiya: top SB) and the large diameter part (Komiya: PB) overlap each other at the boundary position (Komiya: position of bottom 15) between the multi-layered body (Komiya: 15, WL1, 25, WL2) and the interconnection layer region (Komiya: SGS).
Regarding claim 8, Komiya in view of Sasaki and Maruyama further teaches the semiconductor storage device according to claim 1, wherein the end surface (Komiya: fig. 3, surface between bottom 15 and SGS and 31) of the multi-layered body (Komiya: 15, WL1, 25, WL2) directly contacts the interconnection layer region (Komiya: SGS) at the boundary position (Komiya: position of bottom 15) between the multi-layered body (Komiya: 15, WL1, 25, WL2) and the interconnection layer region (Komiya: SGS).
Regarding claim 9, Komiya in view of Sasaki and Maruyama further teaches the semiconductor storage device according to claim 1, wherein:
the first portion (Maruyama: fig. 11, top portion of CL) is provided above the end surface (Maruyama: bottom surface of bottom 45) along the first direction (vertical direction), and
the second portion (Maruyama: bottom portion of CL) is provided below the end surface (Maruyama: bottom surface of bottom 45) along the first direction (vertical direction).
Regarding claim 10, Komiya in view of Sasaki and Maruyama further teaches the semiconductor storage device according to claim 1, wherein a bottom of the second portion (Maruyama: fig. 11, bottom of CL) is connected to a second insulating film (Maruyama: 50).
Regarding claim 11, Komiya in view of Sasaki and Maruyama further teaches the semiconductor storage device according to claim 10, wherein the second insulating film (Maruyama: fig. 11, 50) is provided between the bottom of the second portion (Maruyama: bottom of CL) and the interconnection layer region (Maruyama: region of SGS and 20)..
Response to Arguments
Applicant’s arguments with respect to claims 1-11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kanno et al. (US 20210066340) teaches the second portion includes the first insulating film being provided on the second surface.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818